a394e3262f
(cgen_parse_{{,un}signed_integer,address}): Update call to
cgen_parse_operand_fn.
(cgen_init_parse_operand): New function.
* m32r-asm.c (parse_insn_normal): cgen_init_parse_operand renamed
from cgen_asm_init_parse.
(m32r_cgen_assemble_insn): New operand `errmsg'.
Delete call to as_bad, return error message to caller.
(m32r_cgen_asm_hash_keywords): #if 0 out.
778 lines
22 KiB
C
778 lines
22 KiB
C
/* Assembler interface for targets using CGEN. -*- C -*-
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CGEN: Cpu tools GENerator
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This file is used to generate m32r-asm.c.
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Copyright (C) 1996, 1997 Free Software Foundation, Inc.
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This file is part of the GNU Binutils and GDB, the GNU debugger.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2, or (at your option)
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any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
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#include <ctype.h>
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#include <stdio.h>
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#include "ansidecl.h"
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#include "bfd.h"
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#include "m32r-opc.h"
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/* ??? The layout of this stuff is still work in progress.
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For speed in assembly/disassembly, we use inline functions. That of course
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will only work for GCC. When this stuff is finished, we can decide whether
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to keep the inline functions (and only get the performance increase when
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compiled with GCC), or switch to macros, or use something else.
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*/
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static const char *parse_insn_normal
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PARAMS ((const struct cgen_insn *, const char **, struct cgen_fields *));
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static void insert_insn_normal
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PARAMS ((const struct cgen_insn *, struct cgen_fields *, cgen_insn_t *));
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/* Default insertion routine.
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SHIFT is negative for left shifts, positive for right shifts.
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All bits of VALUE to be inserted must be valid as we don't handle
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signed vs unsigned shifts.
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ATTRS is a mask of the boolean attributes. We don't need any at the
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moment, but for consistency with extract_normal we have them. */
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/* FIXME: This duplicates functionality with bfd's howto table and
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bfd_install_relocation. */
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/* FIXME: For architectures where insns can be representable as ints,
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store insn in `field' struct and add registers, etc. while parsing. */
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static CGEN_INLINE void
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insert_normal (value, attrs, start, length, shift, total_length, buffer)
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long value;
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unsigned int attrs;
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int start, length, shift, total_length;
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char *buffer;
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{
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bfd_vma x;
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#if 0 /*def CGEN_INT_INSN*/
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*buffer |= ((value & ((1 << length) - 1))
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<< (total_length - (start + length)));
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#else
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switch (total_length)
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{
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case 8:
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x = *(unsigned char *) buffer;
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break;
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case 16:
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if (CGEN_CURRENT_ENDIAN == CGEN_ENDIAN_BIG)
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x = bfd_getb16 (buffer);
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else
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x = bfd_getl16 (buffer);
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break;
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case 32:
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if (CGEN_CURRENT_ENDIAN == CGEN_ENDIAN_BIG)
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x = bfd_getb32 (buffer);
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else
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x = bfd_getl32 (buffer);
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break;
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default :
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abort ();
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}
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if (shift < 0)
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value <<= -shift;
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else
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value >>= shift;
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x |= ((value & ((1 << length) - 1))
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<< (total_length - (start + length)));
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switch (total_length)
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{
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case 8:
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*buffer = value;
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break;
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case 16:
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if (CGEN_CURRENT_ENDIAN == CGEN_ENDIAN_BIG)
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bfd_putb16 (x, buffer);
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else
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bfd_putl16 (x, buffer);
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break;
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case 32:
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if (CGEN_CURRENT_ENDIAN == CGEN_ENDIAN_BIG)
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bfd_putb32 (x, buffer);
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else
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bfd_putl32 (x, buffer);
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break;
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default :
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abort ();
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}
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#endif
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}
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/* -- assembler routines inserted here */
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/* -- asm.c */
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/* Handle shigh(), high(). */
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static const char *
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parse_h_hi16 (strp, opindex, min, max, valuep)
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const char **strp;
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int opindex;
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unsigned long min, max;
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unsigned long *valuep;
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{
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const char *errmsg;
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/* FIXME: Need # in assembler syntax (means '#' is optional). */
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if (**strp == '#')
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++*strp;
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if (strncmp (*strp, "high(", 5) == 0)
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{
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*strp += 5;
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/* FIXME: If value was a number, right shift by 16. */
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errmsg = cgen_parse_address (strp, opindex, BFD_RELOC_M32R_HI16_ULO, valuep);
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if (**strp != ')')
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return "missing `)'";
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++*strp;
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return errmsg;
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}
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else if (strncmp (*strp, "shigh(", 6) == 0)
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{
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*strp += 6;
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/* FIXME: If value was a number, right shift by 16 (+ sign test). */
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errmsg = cgen_parse_address (strp, opindex, BFD_RELOC_M32R_HI16_SLO, valuep);
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if (**strp != ')')
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return "missing `)'";
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++*strp;
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return errmsg;
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}
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return cgen_parse_unsigned_integer (strp, opindex, min, max, valuep);
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}
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/* Handle low() in a signed context. Also handle sda().
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The signedness of the value doesn't matter to low(), but this also
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handles the case where low() isn't present. */
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static const char *
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parse_h_slo16 (strp, opindex, min, max, valuep)
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const char **strp;
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int opindex;
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long min, max;
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long *valuep;
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{
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const char *errmsg;
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/* FIXME: Need # in assembler syntax (means '#' is optional). */
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if (**strp == '#')
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++*strp;
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if (strncmp (*strp, "low(", 4) == 0)
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{
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*strp += 4;
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errmsg = cgen_parse_address (strp, opindex, BFD_RELOC_M32R_LO16, valuep);
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if (**strp != ')')
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return "missing `)'";
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++*strp;
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return errmsg;
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}
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if (strncmp (*strp, "sda(", 4) == 0)
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{
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*strp += 4;
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errmsg = cgen_parse_address (strp, opindex, BFD_RELOC_M32R_SDA16, valuep);
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if (**strp != ')')
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return "missing `)'";
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++*strp;
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return errmsg;
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}
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return cgen_parse_signed_integer (strp, opindex, min, max, valuep);
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}
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/* Handle low() in an unsigned context.
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The signedness of the value doesn't matter to low(), but this also
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handles the case where low() isn't present. */
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static const char *
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parse_h_ulo16 (strp, opindex, min, max, valuep)
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const char **strp;
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int opindex;
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unsigned long min, max;
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unsigned long *valuep;
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{
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const char *errmsg;
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/* FIXME: Need # in assembler syntax (means '#' is optional). */
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if (**strp == '#')
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++*strp;
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if (strncmp (*strp, "low(", 4) == 0)
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{
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*strp += 4;
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errmsg = cgen_parse_address (strp, opindex, BFD_RELOC_M32R_LO16, valuep);
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if (**strp != ')')
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return "missing `)'";
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++*strp;
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return errmsg;
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}
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return cgen_parse_unsigned_integer (strp, opindex, min, max, valuep);
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}
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/* -- */
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/* Main entry point for operand parsing.
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This function is basically just a big switch statement. Earlier versions
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used tables to look up the function to use, but
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- if the table contains both assembler and disassembler functions then
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the disassembler contains much of the assembler and vice-versa,
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- there's a lot of inlining possibilities as things grow,
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- using a switch statement avoids the function call overhead.
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This function could be moved into `parse_insn_normal', but keeping it
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separate makes clear the interface between `parse_insn_normal' and each of
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the handlers.
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*/
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CGEN_INLINE const char *
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m32r_cgen_parse_operand (opindex, strp, fields)
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int opindex;
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const char **strp;
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struct cgen_fields *fields;
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{
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const char *errmsg;
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switch (opindex)
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{
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case 0 :
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errmsg = cgen_parse_keyword (strp, & m32r_cgen_opval_h_gr, &fields->f_r2);
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break;
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case 1 :
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errmsg = cgen_parse_keyword (strp, & m32r_cgen_opval_h_gr, &fields->f_r1);
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break;
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case 2 :
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errmsg = cgen_parse_keyword (strp, & m32r_cgen_opval_h_gr, &fields->f_r1);
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break;
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case 3 :
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errmsg = cgen_parse_keyword (strp, & m32r_cgen_opval_h_gr, &fields->f_r2);
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break;
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case 4 :
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errmsg = cgen_parse_keyword (strp, & m32r_cgen_opval_h_cr, &fields->f_r2);
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break;
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case 5 :
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errmsg = cgen_parse_keyword (strp, & m32r_cgen_opval_h_cr, &fields->f_r1);
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break;
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case 6 :
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errmsg = cgen_parse_signed_integer (strp, 6, -128, 127, &fields->f_simm8);
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break;
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case 7 :
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errmsg = cgen_parse_signed_integer (strp, 7, -32768, 32767, &fields->f_simm16);
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break;
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case 8 :
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errmsg = cgen_parse_unsigned_integer (strp, 8, 0, 15, &fields->f_uimm4);
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break;
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case 9 :
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errmsg = cgen_parse_unsigned_integer (strp, 9, 0, 31, &fields->f_uimm5);
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break;
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case 10 :
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errmsg = cgen_parse_unsigned_integer (strp, 10, 0, 65535, &fields->f_uimm16);
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break;
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case 11 :
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errmsg = parse_h_hi16 (strp, 11, 0, 65535, &fields->f_hi16);
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break;
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case 12 :
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errmsg = parse_h_slo16 (strp, 12, -32768, 32767, &fields->f_simm16);
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break;
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case 13 :
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errmsg = parse_h_ulo16 (strp, 13, 0, 65535, &fields->f_uimm16);
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break;
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case 14 :
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errmsg = cgen_parse_address (strp, 14, 0, &fields->f_uimm24);
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break;
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case 15 :
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errmsg = cgen_parse_address (strp, 15, 0, &fields->f_disp8);
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break;
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case 16 :
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errmsg = cgen_parse_address (strp, 16, 0, &fields->f_disp16);
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break;
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case 17 :
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errmsg = cgen_parse_address (strp, 17, 0, &fields->f_disp24);
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break;
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default :
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fprintf (stderr, "Unrecognized field %d while parsing.\n", opindex);
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abort ();
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}
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return errmsg;
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}
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/* Main entry point for operand insertion.
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This function is basically just a big switch statement. Earlier versions
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used tables to look up the function to use, but
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- if the table contains both assembler and disassembler functions then
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the disassembler contains much of the assembler and vice-versa,
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- there's a lot of inlining possibilities as things grow,
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- using a switch statement avoids the function call overhead.
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This function could be moved into `parse_insn_normal', but keeping it
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separate makes clear the interface between `parse_insn_normal' and each of
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the handlers. It's also needed by GAS to insert operands that couldn't be
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resolved during parsing.
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*/
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CGEN_INLINE void
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m32r_cgen_insert_operand (opindex, fields, buffer)
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int opindex;
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struct cgen_fields *fields;
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cgen_insn_t *buffer;
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{
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switch (opindex)
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{
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case 0 :
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insert_normal (fields->f_r2, 0|(1<<CGEN_OPERAND_UNSIGNED), 12, 4, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
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break;
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case 1 :
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insert_normal (fields->f_r1, 0|(1<<CGEN_OPERAND_UNSIGNED), 4, 4, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
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break;
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case 2 :
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insert_normal (fields->f_r1, 0|(1<<CGEN_OPERAND_UNSIGNED), 4, 4, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
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break;
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case 3 :
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insert_normal (fields->f_r2, 0|(1<<CGEN_OPERAND_UNSIGNED), 12, 4, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
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break;
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case 4 :
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insert_normal (fields->f_r2, 0|(1<<CGEN_OPERAND_UNSIGNED), 12, 4, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
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break;
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case 5 :
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insert_normal (fields->f_r1, 0|(1<<CGEN_OPERAND_UNSIGNED), 4, 4, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
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break;
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case 6 :
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insert_normal (fields->f_simm8, 0, 8, 8, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
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break;
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case 7 :
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insert_normal (fields->f_simm16, 0, 16, 16, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
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break;
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case 8 :
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insert_normal (fields->f_uimm4, 0|(1<<CGEN_OPERAND_UNSIGNED), 12, 4, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
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break;
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case 9 :
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insert_normal (fields->f_uimm5, 0|(1<<CGEN_OPERAND_UNSIGNED), 11, 5, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
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break;
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case 10 :
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insert_normal (fields->f_uimm16, 0|(1<<CGEN_OPERAND_UNSIGNED), 16, 16, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
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break;
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case 11 :
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insert_normal (fields->f_hi16, 0|(1<<CGEN_OPERAND_SIGN_OPT)|(1<<CGEN_OPERAND_UNSIGNED), 16, 16, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
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break;
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case 12 :
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insert_normal (fields->f_simm16, 0, 16, 16, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
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break;
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case 13 :
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insert_normal (fields->f_uimm16, 0|(1<<CGEN_OPERAND_UNSIGNED), 16, 16, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
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break;
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case 14 :
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insert_normal (fields->f_uimm24, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_ABS_ADDR)|(1<<CGEN_OPERAND_UNSIGNED), 8, 24, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
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break;
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case 15 :
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insert_normal (fields->f_disp8, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), 8, 8, 2, CGEN_FIELDS_BITSIZE (fields), buffer);
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break;
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case 16 :
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insert_normal (fields->f_disp16, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), 16, 16, 2, CGEN_FIELDS_BITSIZE (fields), buffer);
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break;
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case 17 :
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insert_normal (fields->f_disp24, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), 8, 24, 2, CGEN_FIELDS_BITSIZE (fields), buffer);
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break;
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default :
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fprintf (stderr, "Unrecognized field %d while building insn.\n",
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opindex);
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abort ();
|
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}
|
||
}
|
||
|
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/* Main entry point for operand validation.
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||
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This function is called from GAS when it has fully resolved an operand
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that couldn't be resolved during parsing.
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The result is NULL for success or an error message (which may be
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computed into a static buffer).
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*/
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CGEN_INLINE const char *
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m32r_cgen_validate_operand (opindex, fields)
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int opindex;
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const struct cgen_fields *fields;
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{
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const char *errmsg = NULL;
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|
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switch (opindex)
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{
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case 0 :
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/* nothing to do */
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break;
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case 1 :
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/* nothing to do */
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||
break;
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||
case 2 :
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/* nothing to do */
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||
break;
|
||
case 3 :
|
||
/* nothing to do */
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||
break;
|
||
case 4 :
|
||
/* nothing to do */
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||
break;
|
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case 5 :
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/* nothing to do */
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break;
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case 6 :
|
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errmsg = cgen_validate_signed_integer (fields->f_simm8, -128, 127);
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break;
|
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case 7 :
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errmsg = cgen_validate_signed_integer (fields->f_simm16, -32768, 32767);
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break;
|
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case 8 :
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errmsg = cgen_validate_unsigned_integer (fields->f_uimm4, 0, 15);
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break;
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case 9 :
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errmsg = cgen_validate_unsigned_integer (fields->f_uimm5, 0, 31);
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break;
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case 10 :
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errmsg = cgen_validate_unsigned_integer (fields->f_uimm16, 0, 65535);
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break;
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case 11 :
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errmsg = cgen_validate_unsigned_integer (fields->f_hi16, 0, 65535);
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break;
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case 12 :
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errmsg = cgen_validate_signed_integer (fields->f_simm16, -32768, 32767);
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break;
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case 13 :
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errmsg = cgen_validate_unsigned_integer (fields->f_uimm16, 0, 65535);
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break;
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case 14 :
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/* nothing to do */
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break;
|
||
case 15 :
|
||
/* nothing to do */
|
||
break;
|
||
case 16 :
|
||
/* nothing to do */
|
||
break;
|
||
case 17 :
|
||
/* nothing to do */
|
||
break;
|
||
|
||
default :
|
||
fprintf (stderr, "Unrecognized field %d while validating operand.\n",
|
||
opindex);
|
||
abort ();
|
||
}
|
||
|
||
return errmsg;
|
||
}
|
||
|
||
cgen_parse_fn *m32r_cgen_parse_handlers[] = {
|
||
0, /* default */
|
||
parse_insn_normal,
|
||
};
|
||
|
||
cgen_insert_fn *m32r_cgen_insert_handlers[] = {
|
||
0, /* default */
|
||
insert_insn_normal,
|
||
};
|
||
|
||
void
|
||
m32r_cgen_init_asm (mach, endian)
|
||
int mach;
|
||
enum cgen_endian endian;
|
||
{
|
||
m32r_cgen_init_tables (mach);
|
||
cgen_set_cpu (& m32r_cgen_opcode_data, mach, endian);
|
||
cgen_asm_init ();
|
||
}
|
||
|
||
|
||
/* Default insn parser.
|
||
|
||
The syntax string is scanned and operands are parsed and stored in FIELDS.
|
||
Relocs are queued as we go via other callbacks.
|
||
|
||
??? Note that this is currently an all-or-nothing parser. If we fail to
|
||
parse the instruction, we return 0 and the caller will start over from
|
||
the beginning. Backtracking will be necessary in parsing subexpressions,
|
||
but that can be handled there. Not handling backtracking here may get
|
||
expensive in the case of the m68k. Deal with later.
|
||
|
||
Returns NULL for success, an error message for failure.
|
||
*/
|
||
|
||
static const char *
|
||
parse_insn_normal (insn, strp, fields)
|
||
const struct cgen_insn *insn;
|
||
const char **strp;
|
||
struct cgen_fields *fields;
|
||
{
|
||
const struct cgen_syntax *syntax = CGEN_INSN_SYNTAX (insn);
|
||
const char *str = *strp;
|
||
const char *errmsg;
|
||
const unsigned char *syn;
|
||
#ifdef CGEN_MNEMONIC_OPERANDS
|
||
int past_opcode_p;
|
||
#endif
|
||
|
||
/* If mnemonics are constant, they're not stored with the syntax string. */
|
||
#ifndef CGEN_MNEMONIC_OPERANDS
|
||
{
|
||
const char *p = syntax->mnemonic;
|
||
|
||
while (*p && *p == *str)
|
||
++p, ++str;
|
||
if (*p || (*str && !isspace (*str)))
|
||
return "unrecognized instruction";
|
||
|
||
while (isspace (*str))
|
||
++str;
|
||
}
|
||
#endif
|
||
|
||
CGEN_INIT_PARSE ();
|
||
cgen_init_parse_operand ();
|
||
#ifdef CGEN_MNEMONIC_OPERANDS
|
||
past_opcode_p = 0;
|
||
#endif
|
||
|
||
/* We don't check for (*str != '\0') here because we want to parse
|
||
any trailing fake arguments in the syntax string. */
|
||
for (syn = syntax->syntax; *syn != '\0'; )
|
||
{
|
||
/* Non operand chars must match exactly. */
|
||
/* FIXME: Need to better handle whitespace. */
|
||
if (CGEN_SYNTAX_CHAR_P (*syn))
|
||
{
|
||
if (*str == CGEN_SYNTAX_CHAR (*syn))
|
||
{
|
||
#ifdef CGEN_MNEMONIC_OPERANDS
|
||
if (*syn == ' ')
|
||
past_opcode_p = 1;
|
||
#endif
|
||
++syn;
|
||
++str;
|
||
}
|
||
else
|
||
{
|
||
/* Syntax char didn't match. Can't be this insn. */
|
||
/* FIXME: would like to return "expected char `c'" */
|
||
return "syntax error";
|
||
}
|
||
continue;
|
||
}
|
||
|
||
/* We have an operand of some sort. */
|
||
errmsg = m32r_cgen_parse_operand (CGEN_SYNTAX_FIELD (*syn),
|
||
&str, fields);
|
||
if (errmsg)
|
||
return errmsg;
|
||
|
||
/* Done with this operand, continue with next one. */
|
||
++syn;
|
||
}
|
||
|
||
/* If we're at the end of the syntax string, we're done. */
|
||
if (*syn == '\0')
|
||
{
|
||
/* FIXME: For the moment we assume a valid `str' can only contain
|
||
blanks now. IE: We needn't try again with a longer version of
|
||
the insn and it is assumed that longer versions of insns appear
|
||
before shorter ones (eg: lsr r2,r3,1 vs lsr r2,r3). */
|
||
while (isspace (*str))
|
||
++str;
|
||
|
||
if (*str != '\0')
|
||
return "junk at end of line"; /* FIXME: would like to include `str' */
|
||
|
||
return NULL;
|
||
}
|
||
|
||
/* We couldn't parse it. */
|
||
return "unrecognized instruction";
|
||
}
|
||
|
||
/* Default insn builder (insert handler).
|
||
The instruction is recorded in target byte order. */
|
||
|
||
static void
|
||
insert_insn_normal (insn, fields, buffer)
|
||
const struct cgen_insn *insn;
|
||
struct cgen_fields *fields;
|
||
cgen_insn_t *buffer;
|
||
{
|
||
const struct cgen_syntax *syntax = CGEN_INSN_SYNTAX (insn);
|
||
bfd_vma value;
|
||
const unsigned char *syn;
|
||
|
||
CGEN_INIT_INSERT ();
|
||
value = syntax->value;
|
||
|
||
/* If we're recording insns as numbers (rather than a string of bytes),
|
||
target byte order handling is deferred until later. */
|
||
#undef min
|
||
#define min(a,b) ((a) < (b) ? (a) : (b))
|
||
#if 0 /*def CGEN_INT_INSN*/
|
||
*buffer = value;
|
||
#else
|
||
switch (min (CGEN_BASE_INSN_BITSIZE, CGEN_FIELDS_BITSIZE (fields)))
|
||
{
|
||
case 8:
|
||
*buffer = value;
|
||
break;
|
||
case 16:
|
||
if (CGEN_CURRENT_ENDIAN == CGEN_ENDIAN_BIG)
|
||
bfd_putb16 (value, (char *) buffer);
|
||
else
|
||
bfd_putl16 (value, (char *) buffer);
|
||
break;
|
||
case 32:
|
||
if (CGEN_CURRENT_ENDIAN == CGEN_ENDIAN_BIG)
|
||
bfd_putb32 (value, (char *) buffer);
|
||
else
|
||
bfd_putl32 (value, (char *) buffer);
|
||
break;
|
||
default:
|
||
abort ();
|
||
}
|
||
#endif
|
||
|
||
/* ??? Rather than scanning the syntax string again, we could store
|
||
in `fields' a null terminated list of the fields that are present. */
|
||
|
||
for (syn = syntax->syntax; *syn != '\0'; ++syn)
|
||
{
|
||
if (CGEN_SYNTAX_CHAR_P (*syn))
|
||
continue;
|
||
|
||
m32r_cgen_insert_operand (CGEN_SYNTAX_FIELD (*syn), fields, buffer);
|
||
}
|
||
}
|
||
|
||
/* Main entry point.
|
||
This routine is called for each instruction to be assembled.
|
||
STR points to the insn to be assembled.
|
||
We assume all necessary tables have been initialized.
|
||
The result is a pointer to the insn's entry in the opcode table,
|
||
or NULL if an error occured (an error message will have already been
|
||
printed). */
|
||
|
||
const struct cgen_insn *
|
||
m32r_cgen_assemble_insn (str, fields, buf, errmsg)
|
||
const char *str;
|
||
struct cgen_fields *fields;
|
||
cgen_insn_t *buf;
|
||
char **errmsg;
|
||
{
|
||
const char *start;
|
||
CGEN_INSN_LIST *ilist;
|
||
|
||
/* Skip leading white space. */
|
||
while (isspace (*str))
|
||
++str;
|
||
|
||
/* The instructions are stored in hashed lists.
|
||
Get the first in the list. */
|
||
ilist = CGEN_ASM_LOOKUP_INSN (str);
|
||
|
||
/* Keep looking until we find a match. */
|
||
|
||
start = str;
|
||
for ( ; ilist != NULL ; ilist = CGEN_ASM_NEXT_INSN (ilist))
|
||
{
|
||
const struct cgen_insn *insn = ilist->insn;
|
||
|
||
#if 0 /* not needed as unsupported opcodes shouldn't be in the hash lists */
|
||
/* Is this insn supported by the selected cpu? */
|
||
if (! m32r_cgen_insn_supported (insn))
|
||
continue;
|
||
#endif
|
||
|
||
#if 1 /* FIXME: wip */
|
||
/* If the RELAX attribute is set, this is an insn that shouldn't be
|
||
chosen immediately. Instead, it is used during assembler/linker
|
||
relaxation if possible. */
|
||
if (CGEN_INSN_ATTR (insn, CGEN_INSN_RELAX) != 0)
|
||
continue;
|
||
#endif
|
||
|
||
str = start;
|
||
|
||
/* Record a default length for the insn. This will get set to the
|
||
correct value while parsing. */
|
||
/* FIXME: wip */
|
||
CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn);
|
||
|
||
/* ??? The extent to which moving the parse and insert handlers into
|
||
this function (thus removing the function call) will speed things up
|
||
is unclear. The simplicity and flexibility of the current scheme is
|
||
appropriate for now. One could have the best of both worlds with
|
||
inline functions but of course that would only work for gcc. Since
|
||
we're machine generating some code we could do that here too. Maybe
|
||
later. */
|
||
if (! (*CGEN_PARSE_FN (insn)) (insn, &str, fields))
|
||
{
|
||
(*CGEN_INSERT_FN (insn)) (insn, fields, buf);
|
||
/* It is up to the caller to actually output the insn and any
|
||
queued relocs. */
|
||
return insn;
|
||
}
|
||
|
||
/* Try the next entry. */
|
||
}
|
||
|
||
/* FIXME: We can return a better error message than this.
|
||
Need to track why it failed and pick the right one. */
|
||
{
|
||
static char errbuf[100];
|
||
sprintf (errbuf, "bad instruction `%.50s%s'",
|
||
start, strlen (start) > 50 ? "..." : "");
|
||
*errmsg = errbuf;
|
||
return NULL;
|
||
}
|
||
}
|
||
|
||
#if 0 /* This calls back to GAS which we can't do without care. */
|
||
|
||
/* Record each member of OPVALS in the assembler's symbol table.
|
||
This lets GAS parse registers for us.
|
||
??? Interesting idea but not currently used. */
|
||
|
||
void
|
||
m32r_cgen_asm_hash_keywords (opvals)
|
||
struct cgen_keyword *opvals;
|
||
{
|
||
struct cgen_keyword_search search = cgen_keyword_search_init (opvals, NULL);
|
||
const struct cgen_keyword_entry *ke;
|
||
|
||
while ((ke = cgen_keyword_search_next (&search)) != NULL)
|
||
{
|
||
#if 0 /* Unnecessary, should be done in the search routine. */
|
||
if (! m32r_cgen_opval_supported (ke))
|
||
continue;
|
||
#endif
|
||
cgen_asm_record_register (ke->name, ke->value);
|
||
}
|
||
}
|
||
|
||
#endif /* 0 */
|