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7250 commits

Author SHA1 Message Date
Nick Clifton
f8c2a96547 Update translations.
binutils * po/ca.po: New Catalan translation.
	* configure.ac (ALL_LINGUAS): Add ca.
	* configure: Regenerate.

gas	* po/fr.po: Updated French translation.
	* po/uk.po: Updated Ukraninan translation.
	* po/zh_CN.po: New simplified Chinese translation.
	* configure.ac (ALL_LINGUAS): Add zh_CN.
	* configure: Regenerate.

opcodes	* po/zh_CN.po: Updated simplified Chinese translation.
2015-11-20 12:35:43 +00:00
Matthew Wahab
c2825638b6 [AArch64] Reject invalid immediate operands to MSR PAN
The support for accessing the ARMv8.1 PSTATE field PAN allows
instructions of the form MSR PAN, #<imm> with <imm> any unsigned 4-bit
integer. However, the architecture specification requires that the
immediate is either 0 or 1.

This patch implements the constraint on the immediate, generating an
error if the immediate operand is invalid, and adds tests for the
illegal forms.

opcodes/
2015-11-19  Matthew Wahab  <matthew.wahab@arm.com>

	* aarch64-opc.c (operand_general_constraint_met_p): Check validity
	of MSR PAN immediate operand.

gas/testsuite/
2015-11-19  Matthew Wahab  <matthew.wahab@arm.com>

	* gas/aarch64/pan-illegal.d: New.
	* gas/aarch64/pan-illegal.l: New.
	* gas/aarch64/pan.s: Add tests for invalid immediates.

Change-Id: Ibb3056c975eb792104da138d94594224f56a993e
2015-11-19 14:13:45 +00:00
Matthew Wahab
56a1b672f4 [ARM] Add ARMv8.2 architecture feature and command line option.
ARMv8.2 is an architectural extension of ARMv8. This patch adds an
architecture feature macro for ARMv8.2 to the binutils ARM target
with GAS command line option -march=armv8.2-a.

gas/
2015-11-19  Matthew Wahab  <matthew.wahab@arm.com>

	* config/tc-arm.c (arm_archs): Add "armv8.2-a".
	* doc/c-arm.texi (-march): Add "armv8.2-a".

include/opcode/
2015-11-19  Matthew Wahab  <matthew.wahab@arm.com>

	* arm.h (ARM_EXT2_V8_2A): New.
	(ARM_ARCH_V8_2A): New.

Change-Id: I9e0f50e3c6cea24e6b87b8b862fd4e1cdcc1052e
2015-11-19 09:24:14 +00:00
Matthew Wahab
acb787b032 [AArch64] Add ARMv8.2 command line option and feature flag.
ARMv8.2 is an architectural extension of ARMv8. This patch adds an
architecture feature macro for ARMv8.2 to the binutils AArch64 target
with GAS command line option -march=armv8.2-a.

gas/
2015-11-19  Matthew Wahab  <matthew.wahab@arm.com>

	* config/tc-aarch64.c (aarch64_archs): Add "armv8.2-a".
	* doc/c-aarch64.texi (-march): Likewise.

include/opcode/
2015-11-19  Matthew Wahab  <matthew.wahab@arm.com>

	* aarch64.h (AARCH64_FEATURE_V8_2): New.
	(AARCH64_ARCH_V8_2): New.

Change-Id: I129232ab00234a07d18ce4b619607344acb3cbaf
2015-11-19 09:12:49 +00:00
Alan Modra
9a724e7b6b output_big_leb128 comment
* read.c (output_big_leb128): Describe "sign" parameter.
2015-11-19 17:01:59 +10:30
Alan Modra
04830f249f Recent powerpc testcase fails
On powerpcle-cygwin a couple of tests fail due to alignment.

	* gas/ppc/altivec3.d: Allow for padding at end of section.
	* gas/testsuite/gas/ppc/power9.d: Likewise.
2015-11-19 16:57:49 +10:30
Alan Modra
f29cf775fa Use default sub-segment align for non-ELF powerpc
Defining this to zero for COFF and PE meant that code sections were
padded with zeros.  The fact that no one has complained since 2006
says these targets are dead, I guess.

	* config/tc-ppc.h (SUB_SEGMENT_ALIGN): Define only for ELF.
2015-11-19 16:53:43 +10:30
Mike Frysinger
58a345fe1f gas: microblaze: fix shift overflow
This code tries to shift an integer 31 bits which triggers a werror:
gas/config/tc-microblaze.c:742:21: error: integer overflow in expression [-Werror=overflow]
  e->X_add_number |= -(1 << 31);

Cast the 1 to offsetT to match X_add_number to fix things.
2015-11-16 23:21:39 -05:00
Tristan Gingold
d8bd95efd8 Bump version to 2.26.51
bfd/
2015-11-13  Tristan Gingold  <gingold@adacore.com>

	* version.m4: Bump version to 2.26.51
	* configure: Regenerate.

binutils/
2015-11-13  Tristan Gingold  <gingold@adacore.com>

	* configure: Regenerate.

gas/
2015-11-13  Tristan Gingold  <gingold@adacore.com>

	* configure: Regenerate.

gprof/
2015-11-13  Tristan Gingold  <gingold@adacore.com>

	* configure: Regenerate.

ld/
2015-11-13  Tristan Gingold  <gingold@adacore.com>

	* configure: Regenerate.

opcodes/
2015-11-13  Tristan Gingold  <gingold@adacore.com>

	* configure: Regenerate.
2015-11-14 16:24:39 -08:00
Tristan Gingold
7feec526b7 Add markers for release 2.26
binutils/
2015-11-13  Tristan Gingold  <gingold@adacore.com>

	* NEWS: Add marker for 2.26.

gas/
2015-11-13  Tristan Gingold  <gingold@adacore.com>

	* NEWS: Add marker for 2.26.

ld/
2015-11-13  Tristan Gingold  <gingold@adacore.com>

	* NEWS: Add marker for 2.26.
2015-11-13 09:31:25 +01:00
James Greenhalgh
9c352f1c23 [AArch64] Add support for Cortex-A35
This patch adds support to the AArch64 back-end for the Cortex-A35
processor, as recently announced by ARM. The ARM Cortex-A35 provides
full support for the ARMv8-A architecture, including the CRC extension,
with optional Advanced-SIMD and Floating-Point support. We therefore set
feature flags for this CPU to AARCH64_ARCH_V8 and AARCH64_FEATURE_CRC, in
the same fashion as Cortex-A53 and Cortex-A57.

Tested in a cross environment for AArch64 with no issues.
2015-11-12 12:04:22 +00:00
Ramana Radhakrishnan
8915a9b7e8 Fix dates in Changelog for previous commit.
582cfe03cb
2015-11-12 11:14:29 +00:00
Ramana Radhakrishnan
43cdc0a8fb Add support for Cortex-A35
2015-11-12  James Greenhalgh  <james.greenhalgh@arm.com>

	* config/tc-arm.c (arm_cpus): Likewise.
	* doc/c-arm.texi (-mcpu=): Likewise.
2015-11-12 11:12:53 +00:00
Ramana Radhakrishnan
582cfe03cb Fix PR gas/19217
2015-11-11  Matthew Wahab  <matthew.wahab@arm.com>

	PR gas/19217
	* config/tc-arm.c (move_or_literal_pool): Remove redundant feature
	check.  Fix some code formatting.  Drop use of MOVT.  Add some
	comments.

2015-11-11  Matthew Wahab  <matthew.wahab@arm.com>

	PR gas/19217
        * gas/arm/thumb2_ldr_immediate_armv6t2.d: Update expected output.
2015-11-12 10:52:03 +00:00
Peter Bergner
a680de9a98 Add assembler, disassembler and linker support for power9.
include/opcode/
	* ppc.h (PPC_OPCODE_POWER9): New define.
	(PPC_OPCODE_VSX3): Likewise.

opcodes/
	* ppc-dis.c (ppc_opts): Add "power9" and "pwr9" entries.
	Add PPC_OPCODE_VSX3 to the vsx entry.
	(powerpc_init_dialect): Set default dialect to power9.
        * ppc-opc.c (insert_dcmxs, extract_dcmxs, insert_dxd, extract_dxd,
        insert_dxdn, extract_dxdn, insert_l0, extract_l0, insert_l1,
        extract_l1 insert_xtq6, extract_xtq6): New static functions.
        (insert_esync): Test for illegal L operand value.
	(DCMX, DCMXS, DXD, NDXD, L0, L1, RC, FC, UIM6, X_R, RIC, PRS, XSQ6,
	XTQ6, LRAND, IMM8, DQX, DQX_MASK, DX, DX_MASK, VXVAPS_MASK, VXVA,XVA,
	XX2VA, XVARC, XBF_MASK, XX2UIM4_MASK, XX2BFD_MASK, XX2DCMXS_MASK,
	XVA_MASK, XRLA_MASK, XBFRARB_MASK, XLRAND_MASK, POWER9, PPCVEC3,
	PPCVSX3): New defines.
	(powerpc_opcodes) <ps_cmpu0, ps_cmpo0, ps_cmpu1, ps_cmpo1, fcmpu,
	fcmpo, ftdiv, ftsqrt>: Use XBF_MASK.
	<mcrxr>: Use XBFRARB_MASK.
	<addpcis, bcdcfn., bcdcfsq., bcdcfz., bcdcpsgn., bcdctn., bcdctsq.,
	bcdctz., bcds., bcdsetsgn., bcdsr., bcdtrunc., bcdus., bcdutrunc.,
	cmpeqb, cmprb, cnttzd, cnttzd., cnttzw, cnttzw., copy, copy_first,
	cp_abort, darn, dtstsfi, dtstsfiq, extswsli, extswsli., ldat, ldmx,
	lwat, lxsd, lxsibzx, lxsihzx, lxssp, lxv, lxvb16x, lxvh8x, lxvl, lxvll,
	lxvwsx, lxvx, maddhd, maddhdu, maddld, mcrxrx, mfvsrld, modsd, modsw,
	modud, moduw, msgsync, mtvsrdd, mtvsrws, paste, paste., paste_last,
	rmieg, setb, slbieg, slbsync, stdat, stop, stwat, stxsd, stxsibx,
	stxsihx, stxssp, stxv, stxvb16x, stxvh8x, stxvl, stxvll, stxvx,
	subpcis, urfid, vbpermd, vclzlsbb, vcmpneb, vcmpneb., vcmpneh,
	vcmpneh., vcmpnew, vcmpnew., vcmpnezb, vcmpnezb., vcmpnezh, vcmpnezh.,
	vcmpnezw, vcmpnezw., vctzb, vctzd, vctzh, vctzlsbb, vctzw, vextractd,
	vextractub, vextractuh, vextractuw, vextsb2d, vextsb2w, vextsh2d,
	vextsh2w, vextsw2d, vextublx, vextubrx, vextuhlx, vextuhrx, vextuwlx,
	vextuwrx, vinsertb, vinsertd, vinserth, vinsertw, vmul10cuq,
	vmul10ecuq, vmul10euq, vmul10uq, vnegd, vnegw, vpermr, vprtybd,
	vprtybq, vprtybw, vrldmi, vrldnm, vrlwmi, vrlwnm, vslv, vsrv, wait,
	xsabsqp, xsaddqp, xsaddqpo, xscmpeqdp, xscmpexpdp, xscmpexpqp,
	xscmpgedp, xscmpgtdp, xscmpnedp, xscmpoqp, xscmpuqp, xscpsgnqp,
	xscvdphp, xscvdpqp, xscvhpdp, xscvqpdp, xscvqpdpo, xscvqpsdz,
	xscvqpswz, xscvqpudz, xscvqpuwz, xscvsdqp, xscvudqp, xsdivqp,
	xsdivqpo, xsiexpdp, xsiexpqp, xsmaddqp, xsmaddqpo, xsmaxcdp,
	xsmaxjdp, xsmincdp, xsminjdp, xsmsubqp, xsmsubqpo, xsmulqp, xsmulqpo,
	xsnabsqp, xsnegqp, xsnmaddqp, xsnmaddqpo, xsnmsubqp, xsnmsubqpo,
	xsrqpi, xsrqpix, xsrqpxp, xssqrtqp, xssqrtqpo, xssubqp, xssubqpo,
	xststdcdp, xststdcqp, xststdcsp, xsxexpdp, xsxexpqp, xsxsigdp,
	xsxsigqp, xvcmpnedp, xvcmpnedp., xvcmpnesp, xvcmpnesp., xvcvhpsp,
	xvcvsphp, xviexpdp, xviexpsp, xvtstdcdp, xvtstdcsp, xvxexpdp,
	xvxexpsp, xvxsigdp, xvxsigsp, xxbrd, xxbrh, xxbrq, xxbrw, xxextractuw,
	xxinsertw, xxperm, xxpermr, xxspltib>: New instructions.
	<doze, nap, sleep, rvwinkle, waitasec, lxvx, stxvx>: Disable on POWER9.
	<tlbiel, tlbie, sync, slbmfev, slbmfee>: Add additional operands.

include/elf/
	* ppc.h (R_PPC_REL16DX_HA): New reloction.
	* ppc64.h (R_PPC64_REL16DX_HA): Likewise.

bfd/
	* elf32-ppc.c (ppc_elf_howto_raw): Add R_PPC_REL16DX_HA.
	(ppc_elf_reloc_type_lookup): Handle R_PPC_REL16DX_HA.
	(ppc_elf_addr16_ha_reloc): Likewise.
	(ppc_elf_check_relocs): Likewise.
	(ppc_elf_relocate_section): Likewise.
	(is_insn_dq_form): Handle lxv and stxv instructions.
	* elf64-ppc.c (ppc64_elf_howto_raw): Add R_PPC64_REL16DX_HA.
	(ppc64_elf_reloc_type_lookup): Handle R_PPC64_REL16DX_HA.
	(ppc64_elf_ha_reloc): Likewise.
	(ppc64_elf_check_relocs): Likewise.
	(ppc64_elf_relocate_section): Likewise.
	* bfd-in2.h: Regenerate.
	* libbfd.h: Likewise.
	* reloc.c (BFD_RELOC_PPC_REL16DX_HA): New.

elfcpp/
	* powerpc.h (R_POWERPC_REL16DX_HA): Define.

gas/
	* doc/as.texinfo (Target PowerPC): Document -mpower9 and -mpwr9.
	* doc/c-ppc.texi (PowerPC-Opts):  Likewise.
	* config/tc-ppc.c (md_show_usage): Likewise.
	(md_assemble): Handle BFD_RELOC_PPC_REL16DX_HA.
	(md_apply_fix): Likewise.
	(ppc_handle_align): Handle power9's group ending nop.

gas/testsuite/
	* gas/ppc/altivec3.s: New test.
	* gas/ppc/altivec3.d: Likewise.
	* gas/ppc/vsx3.s: Likewise.
	* gas/ppc/vsx3.d: Likewise.
	* gas/ppc/power9.s: Likewise.
	* gas/ppc/power9.d: Likewise.
	* gas/ppc/ppc.exp: Run them.
	* gas/ppc/power8.s <lxvx, lxvd2x, stxvx, stxvd2x>: Add new tests.
	* gas/ppc/power8.d: Likewise.
	* gas/ppc/vsx.s: <lxvx, stxvx>: Rename invalid mnemonics ...
	<lxvd2x, stxvd2x>: ...to this.
	* gas/ppc/vsx.d: Likewise.

gold/
	* gold/powerpc.cc (Powerpc_relocate_functions::addr16_dq): New function.
	(Powerpc_relocate_functions::addr16dx_ha): Likewise.
	(Target_powerpc::Scan::local): Handle R_POWERPC_REL16DX_HA.
	(Target_powerpc::Scan::global): Likewise.
	(Target_powerpc::Relocate::relocate): Likewise.

ld/testsuite/
	* ld-powerpc/addpcis.d: New test.
	* ld-powerpc/addpcis.s: New test.
	* ld-powerpc/powerpc.exp: Run it.
2015-11-11 19:52:52 -06:00
Jim Wilson
6b21c2bf57 Add Qualcomm qdf24xx support.
gas/
	* config/tc-aarch64.c (aarch64_cpus): Add qdf24xx.
	* config/tc-arm.c (arm_cpus): Likewise.
	* doc/c-arm.texi, doc/c-aarch64.texi: Likewise.
2015-11-10 09:19:45 -08:00
Dominik Vogt
8d3842cd15 gas: Fix left shift of negative value.
This patch fixes all occurences of left-shifting negative constants in C cod
which is undefined by the C standard.

gas/ChangeLog:

        * read.c (parse_bitfield_cons): Fix left shift of negative value.
        * config/tc-xstormy16.c (md_section_align): Likewise.
        * config/tc-xgate.c (md_section_align): Likewise.
        * config/tc-visium.c (md_section_align): Likewise.
        * config/tc-v850.c (md_section_align): Likewise.
        * config/tc-tic6x.c (md_section_align): Likewise.
        * config/tc-sh.c (SH64PCREL32_M, SH64PCREL48_M, SH64PCREL32_M)
        (MOVI_32_M, MOVI_48_M, MOVI_32_M, md_section_align): Likewise.
        * config/tc-sh64.c (shmedia_md_estimate_size_before_relax): Likewise.
        * config/tc-score.c (s3_section_align): Likewise.
        * config/tc-score7.c (s7_section_align): Likewise.
        * config/tc-s390.c (md_section_align): Likewise.
        * config/tc-rx.c (md_section_align): Likewise.
        * config/tc-rl78.c (md_section_align): Likewise.
        * config/tc-ppc.c (md_section_align): Likewise.
        * config/tc-or1k.c (md_section_align): Likewise.
        * config/tc-nds32.c (md_section_align): Likewise.
        * config/tc-mt.c (md_section_align): Likewise.
        * config/tc-msp430.c (md_section_align): Likewise.
        * config/tc-mn10300.c (md_section_align): Likewise.
        * config/tc-mn10200.c (md_section_align): Likewise.
        * config/tc-mips.c (md_section_align): Likewise.
        * config/tc-microblaze.c (parse_imm): Likewise.
        * config/tc-mep.c (md_section_align): Likewise.
        * config/tc-m68k.c (md_section_align): Likewise.
        * config/tc-m68hc11.c (md_section_align): Likewise.
        * config/tc-m32r.c (md_section_align): Likewise.
        * config/tc-m32c.c (md_section_align): Likewise.
        * config/tc-lm32.c (md_section_align): Likewise.
        * config/tc-iq2000.c (md_section_align): Likewise.
        * config/tc-ip2k.c (md_section_align): Likewise.
        * config/tc-ia64.c (dot_save, dot_vframe): Likewise.
        * config/tc-i960.c (md_number_to_field, md_section_align): Likewise.
        * config/tc-i386.c (md_section_align): Likewise.
        * config/tc-i370.c (md_section_align): Likewise.
        * config/tc-frv.c (md_section_align): Likewise.
        * config/tc-fr30.c (md_section_align): Likewise.
        * config/tc-epiphany.c (md_section_align): Likewise.
        * config/tc-d30v.c (md_section_align): Likewise.
        * config/tc-d10v.c (md_section_align): Likewise.
        * config/tc-cr16.c (l_cons): Likewise.
        * config/tc-bfin.c (md_section_align): Likewise.
        * config/tc-arm.c (md_section_align): Likewise.
        * config/tc-arc.c (md_section_align): Likewise.
        * config/bfin-parse.y (expr_1): Likewise.

gas/testsuite/ChangeLog:

        * gas/all/test-gen.c (random_order_16s, random_order_24s)
        (random_order_32s): Fix left shift of negative value.
2015-11-09 17:12:57 +01:00
Robert Suchanek
be7fe1cddb Move copy_u.w to MSA64 ASE, remove copy_u.d.
opcodes/ChangeLog:

	* mips-opc.c (mips_builtin_opcodes): Change "copy_u.w" to MSA64 ASE,
	remove "copy_u.d".

gas/testsuite/ChangeLog:

	* gas/mips/micromips@msa.d: Remove "copy_u.w".
	* gas/mips/msa.d: Likewise.
	* gas/mips/msa.s: Likweise.
	* gas/mips/mipsr6@msa.d: Likewise.  Replace addresses with regex.
	* gas/mips/msa64.d: Add "copy_u.w".  Remove "copy_u.d".
	* gas/mips/msa64.s: Likewise.
	* gas/mips/micromips@msa64.d: Likewise.
2015-11-09 08:49:10 +00:00
Nick Clifton
854eb72b00 Disassemble RX NOP instructions as such.
opcode	* rx.h (enum RX_Opcode_ID): Add more NOP opcodes.

opcodes	* rx-decode.opc (rx_decode_opcode): Decode extra NOP
	instructions.
	* rx-decode.c: Regenerate.

tests	* gas/rx/max.d: Update expecetd disassembly.
	* gas/rx/nod.d: Likewise.
	* gas/rx/nop.sm: Add tests of more NOP instructions.
2015-11-02 14:37:33 +00:00
Nick Clifton
e292aa7a95 Fix disassembly of RX zero-offset register indirect instructions.
opcode	* rx.h (enum RX_Operand_Type): Add RX_Operand_Zero_Indirect.

opcodes	* rx-decode.opc (rx_disp): If the displacement is zero, set the
	type to RX_Operand_Zero_Indirect.
	* rx-decode.c: Regenerate.
	* rx-dis (print_insn): Handle RX_Operand_Zero_Indirect.

gas	* config/rx-parse.y: Allow zero value for 5-bit displacements.

tests	* gas/rx/mov.sm: Add tests for zero offset indirect moves.
	* gas/rx/mov.d: Update expected output.
2015-11-02 14:14:22 +00:00
Nick Clifton
a62e598977 Fix the RX assembler's section alignment parameter to use multiples of N rather than powers of N
* config/tc-rx.c (parse_rx_section): Align parameter provides a
	multiple of n argument, not a power of n argument.
2015-11-02 13:46:13 +00:00
Ed Schouten
a75cf613fd Add support for AArch64 CloudABI binaries.
ld	* Makefile.am (ALL_64_EMULATION_SOURCES): Add support for
	CloudABI on aarch64. For this target we have to make sure we use
	ELFOSABI_CLOUDABI instead of ELFOSABI_NONE.
	* configure.tgt (targ_emul): Likewise.
	* emulparams/aarch64cloudabi.sh: New file.
	* emulparams/aarch64cloudabib.sh: New file.
	* Makefile.in: Regenerate.

bfd	* config.bfd (targ_defvec): Add support for CloudABI on aarch64.
	For this target we have to make sure we use ELFOSABI_CLOUDABI
	instead of ELFOSABI_NONE.
	* configure.ac (tb): Likewise.
	* elfnn-aarch64.c: Likewise.
	* targets.c (_bfd_target_vector): Likewise.
	* configure: Regenerate.

gas	* config/tc-aarch64.c (elf64_aarch64_target_format): Select the
	cloudabi format if the TARGET_OS is cloudabi.
2015-10-29 13:49:03 +00:00
Thomas Preud'homme
941c9cadbb Fix CPS availability.
2015-10-29  Thomas Preud'homme  <thomas.preudhomme@arm.com>

gas/
    * config/tc-arm.c (insns): Guard cps by arm_ext_v6_notm instead of
    arm_ext_v6_dsp.
2015-10-29 10:37:47 +08:00
Nick Clifton
0e3536f984 Add tests for 16-bit versions of ARM teq, tst, cmp and cmn instructions.
* gas/arm/pinsn.s: New.
        * gas/arm/pinsn.d: Likewise.
2015-10-28 15:30:05 +00:00
Cupertino Miranda
6f4b1afcdc Fix errors in the gas testsuite for the ARC target.
bfd	* reloc.c (BFD_RELOC_ARC_32_PCREL): New entry.
	(ARC_TLS_DTPOFF): Arrange it in order.
	* elf32-arc.c (arc_elf_howto_ini): Update formula.
	(get_middle_endian_relocation): New function.
	(PDATA): Define.
	* bfd-in2.h: Regenerate.
	* libbfd.h: Likewise.

elf	* arc-reloc.def (ARC_32_PCREL): New definition.

gas	* config/tc-arc.c (tokenize_arguments): Avoid creating unused
	symbols when parsing relocation types.
	(md_apply_fix): Handle TLS relocations. Fix BFD_RELOC_ARC_32_PCREL
	relocation.
	(arc_check_reloc): Emit BFD_RELOC_ARC_32_PCREL relocation.
2015-10-28 13:48:00 +00:00
Vinay Kumar
c2f2875869 Fix RL78 disassembly of DE+offset addressing to always show the offset, even when zero.
PR binutils/19159
opcodes	* rl78-decode.opc (MOV): Added offset to DE register in index
	addressing mode.
	* rl78-decode.c: Regenerate.

test	* gas/rl78/pr19159.s: New test source file.
	* gas/rl78/pr19159.d: New test case.
	* gas/rl78/rl78.exp: Run the new test.
2015-10-27 15:24:40 +00:00
Vinay Kumar
4666280441 Display system registers by their names when disassembling RL78 instructions.
PR binutils/19158
opcodes	* rl78-decode.opc: Add 's' print operator to instructions that
	access system registers.
	* rl78-decode.c: Regenerate.
	* rl78-dis.c (print_insn_rl78_common): Decode all system
	registers.

tests	* gas/rl78/pr19158.s: New test source file.
	* gas/rl78/pr19158.d: New test case.
	* gas/rl78/rl78.exp: Run the new test.
2015-10-27 14:49:02 +00:00
Vinay Kumar
02f12cd466 Fix RL78 disassembly so that SP+OFFSET addressing always shows the offset, even when zero.
PR binutils/19157
opcodes	* rl78-decode.opc: Add 'a' print operator to mov instructions
	using stack pointer plus index addressing.
	* rl78-decode.c: Regenerate.

tests	* gas/rl78: New directory.
	* gas/rl78/rl78.exp: New test driver.
	* gas/rl78/pr19157.s: New test source file.
	* gas/rl78/pr19157.d: New test case.
2015-10-27 14:00:40 +00:00
Jim Wilson
ef8e6722f2 Prevent overflowing the selected_cpu_name buffer in the ARM assembler.
* config/tc-arm.c (selected_cpu_name): Increase length of array to
	accomodate "Samsung Exynos M1".
	(arm_parse_cpu): Add assertion and length check to prevent
	overfilling selected_cpu_name.
2015-10-27 09:33:08 +00:00
Nick Clifton
2213f746d3 Add support for MSP430 silicon errata to the assembler.
* config/tc-msp430.c (PUSH_1X_WORKAROUND): Delete.
	(OPTION_SILICON_ERRATA): Define.
	(OPTION_SILICON_WARN): Define.
	(md_parse_opton): Handle silicon errata options.
	(md_longopts): Add silicon errata options.
	(ms_show_usage): Report silicon errata options.
	(msp430_srcoperand): Handle silicon errata.
	(msp430_operands): Likewise. Improve nop insertion.
	(msp430_fix_adjustable): Update warning generation.
	* doc/c-msp430.texi: Document silicon errata options.

tests	* gas/msp430/errata_fixes.s: New test source file.
	* gas/msp430/errata_fixes.d: New test control file.
	* gas/msp430/errata_warns.s: New test source file.
	* gas/msp430/errata_warns.d: New test control file.
	* gas/msp430/errata_warns.l: New test message file.
	* gas/msp430/msp430.exp: Run the new tests.
	* gas/msp430/bad.l: Update expected warning messages
	* gas/msp430/msp430.exp: Run the new tests.
2015-10-22 16:25:46 +01:00
H.J. Lu
9b4c123c95 Properly check --enable-compressed-debug-sections={yes,all}
gas/

	* configure.ac: Properly check
	--enable-compressed-debug-sections={yes,all}.
	* configure: Regenerated.

ld/

	* configure.ac: Properly check
	--enable-compressed-debug-sections={yes,all}.
	* configure: Regenerated.
2015-10-22 07:44:05 -07:00
H.J. Lu
4894d80b50 Handle --enable-compressed-debug-sections=ld,gas
gas/

	PR gas/19109
	* configure.ac: Handle --enable-compressed-debug-sections=*,gas,*.
	* configure: Regenerated.

ld/

	PR gas/19109
	* configure.ac: Handle --enable-compressed-debug-sections=*,ld,*.
	* configure: Regenerated.
2015-10-22 05:18:21 -07:00
H.J. Lu
56ceb5b540 Add R_X86_64_[REX_]GOTPCRELX support to gas and ld
This patch adds support for the R_X86_64_GOTPCRELX and
R_X86_64_REX_GOTPCRELX relocations proposed in

https://groups.google.com/forum/#!topic/x86-64-abi/n9AWHogmVY0

to gas and ld.  It updates gas to generate R_X86_64_GOTPCRELX,
R_X86_64_REX_GOTPCRELX if there is a REX prefix, relocation for memory
operand, foo@GOTPCREL(%rip).  With the locally defined symbol, foo, we
convert

  mov foo@GOTPCREL(%rip), %reg

to

   lea foo(%rip), %reg

and convert

   call/jmp *foo@GOTPCREL(%rip)
to

   nop call foo/jmp foo nop

When PIC is false, convert

   test %reg, foo@GOTPCREL(%rip)
to

test $foo, %reg

and convert

   binop foo@GOTPCREL(%rip), %reg

to

   binop $foo, %reg

where binop is one of adc, add, and, cmp, or, sbb, sub, xor instructions.

bfd/

	* elf64-x86-64.c: Include opcode/i386.h.
	(x86_64_elf_howto_table): Add R_X86_64_GOTPCRELX and
	R_X86_64_REX_GOTPCRELX.
	(R_X86_64_standard): Replace R_X86_64_PLT32_BND with
	R_X86_64_REX_GOTPCRELX.
	(x86_64_reloc_map): Add BFD_RELOC_X86_64_GOTPCRELX and
	BFD_RELOC_X86_64_REX_GOTPCRELX.
	(need_convert_mov_to_lea): Renamed to ...
	(need_convert_load): This.
	(elf_x86_64_check_relocs): Handle R_X86_64_GOTPCRELX and
	R_X86_64_REX_GOTPCRELX.  Replace need_convert_mov_to_lea with
	need_convert_load.
	(elf_x86_64_gc_sweep_hook): Handle R_X86_64_GOTPCRELX and
	R_X86_64_REX_GOTPCRELX.
	(elf_x86_64_size_dynamic_sections): Likewise.
	(elf_x86_64_relocate_section): Likewise.
	(elf_x86_64_convert_mov_to_lea): Renamed to ...
	(elf_x86_64_convert_load): This.  Replace need_convert_mov_to_lea
	with need_convert_load.  Support R_X86_64_GOTPCRELX and
	R_X86_64_REX_GOTPCRELX transformations.
	* reloc.c (BFD_RELOC_X86_64_GOTPCRELX): New.
	(BFD_RELOC_X86_64_REX_GOTPCRELX): Likewise.
	* bfd-in2.h: Regenerated.
	* libbfd.h: Likewise.

gas/

	* config/tc-i386.c (tc_i386_fix_adjustable): Handle
	BFD_RELOC_X86_64_GOTPCRELX and BFD_RELOC_X86_64_REX_GOTPCRELX.
	(tc_gen_reloc): Likewise.
	(i386_validate_fix): Generate BFD_RELOC_X86_64_GOTPCRELX or
	BFD_RELOC_X86_64_REX_GOTPCRELX if fx_tcbit2 is set.
	* config/tc-i386.h (TC_FORCE_RELOCATION_LOCAL): Also return
	true for BFD_RELOC_X86_64_GOTPCRELX and
	BFD_RELOC_X86_64_REX_GOTPCRELX.

gas/testsuite/

	* gas/i386/i386.exp: Run x86-64-gotpcrel.
	* gas/i386/x86-64-gotpcrel.d: New file.
	* gas/i386/x86-64-gotpcrel.s: Likewise.
	* gas/i386/ilp32/x86-64-gotpcrel.d: Likewise.
	* gas/i386/x86-64-localpic.d: Replace R_X86_64_GOTPCREL with
	R_X86_64_REX_GOTPCRELX.
	* gas/i386/ilp32/x86-64-localpic.d: Likewise.

include/elf/

	* x86-64.h (R_X86_64_GOTPCRELX): New.
	(R_X86_64_REX_GOTPCRELX): Likewise.

ld/testsuite/

	* ld-ifunc/ifunc-5r-local-x86-64.d: Replace R_X86_64_GOTPCREL
	with R_X86_64_REX_GOTPCRELX.
	* ld-x86-64/plt-main1.rd: Likewise.
	* ld-x86-64/plt-main3.rd: Likewise.
	* ld-x86-64/plt-main4.rd: Likewise.
	* ld-x86-64/gotpcrel1.dd: New file.
	* ld-x86-64/gotpcrel1.out: Likewise.
	* ld-x86-64/gotpcrel1a.S: Likewise.
	* ld-x86-64/gotpcrel1b.c: Likewise.
	* ld-x86-64/gotpcrel1c.c: Likewise.
	* ld-x86-64/gotpcrel1d.S: Likewise.
	* ld-x86-64/load1.s: Likewise.
	* ld-x86-64/load1a.d: Likewise.
	* ld-x86-64/load1b.d: Likewise.
	* ld-x86-64/load1c.d: Likewise.
	* ld-x86-64/load1d.d: Likewise.
	* ld-x86-64/x86-64.exp: Run load1a, load1b, load1c and load1d
	tests.  Run gotpcrel1 test.
2015-10-22 04:49:38 -07:00
H.J. Lu
02a866936d Add R_386_GOT32X support to gas and ld
This patch adds support for the R_386_GOT32X relocation proposed in

https://groups.google.com/forum/#!topic/ia32-abi/GbJJskkid4I

to gas and ld.  It updates gas to generate R_386_GOT32X relocation for
memory operand, foo@GOT[(%reg)].  We must encode "mov foo@GOT, %eax"
with the 0x8b opcode, instead of the 0xb8 opcode, so that it can be
transformed to "lea foo, %eax".  With the locally defined symbol, foo,
we convert

   mov foo@GOT[(%reg1)], %reg2
to
   lea foo[@GOTOFF(%reg1)], %reg2

and convert

   call/jmp *foo@GOT[(%reg)]
to

   nop call foo/jmp foo nop

When PIC is false, convert

   test %reg1, foo@GOT[(%reg2)]
to
   test $foo, %reg1

and convert

binop foo@GOT[(%reg1)], %reg2

to

binop $foo, %reg2

where binop is one of adc, add, and, cmp, or, sbb, sub, xor instructions.

bfd/

	* elf32-i386.c: Include opcode/i386.h.
	(elf_howto_table): Add R_386_GOT32X.
	(R_386_ext2): Replace R_386_IRELATIVE with R_386_GOT32X.
	(elf_i386_reloc_type_lookup): Handle BFD_RELOC_386_GOT32X.
	(need_convert_mov_to_lea): Renamed to ...
	(need_convert_load): This.
	(elf_i386_check_relocs): Handle R_386_GOT32X.  Replace
	need_convert_mov_to_lea with need_convert_load.
	(elf_i386_gc_sweep_hook): Handle R_386_GOT32X.
	(elf_i386_size_dynamic_sections): Likewise.
	(elf_i386_relocate_section): Likewise.
	(elf_i386_convert_mov_to_lea): Renamed to ...
	(elf_i386_convert_load): This.  Replace need_convert_mov_to_lea
	with need_convert_load.  Support R_386_GOT32X transformations.
	* reloc.c (BFD_RELOC_386_GOT32X): New.
	* bfd-in2.h: Regenerated.
	* libbfd.h: Likewise.

gas/

	* config/tc-i386.c (tc_i386_fix_adjustable): Handle
	BFD_RELOC_386_GOT32X.
	(tc_gen_reloc): Likewise.
	(match_template): Force 0x8b encoding for "mov foo@GOT, %eax".
	(output_disp): Check for "call/jmp *mem", "mov mem, %reg",
	"test %reg, mem" and "binop mem, %reg" where binop is one of
	adc, add, and, cmp, or, sbb, sub, xor instructions.  Set
	fx_tcbit if the REX prefix is generated.  Set fx_tcbit2 if
	BFD_RELOC_386_GOT32X should be generated.
	(i386_validate_fix): Generate BFD_RELOC_386_GOT32X if fx_tcbit2
	is set.

gas/testsuite/

	* gas/i386/got.d: New file.
	* gas/i386/got.s: Likewise.
	* gas/i386/i386.exp: Run got.
	* gas/i386/localpic.d: Replace R_386_GOT32 with R_386_GOT32X.
	* gas/i386/mixed-mode-reloc32.d: Likewise.
	* gas/i386/reloc32.d: Likewise.

include/elf/

	* i386.h (R_386_GOT32X): New relocation.

ld/testsuite/

	* ld-i386/branch1.d: New file.
	* ld-i386/branch1.s: Likewise.
	* ld-i386/call1.d: Likewise.
	* ld-i386/call1.s: Likewise.
	* ld-i386/call2.d: Likewise.
	* ld-i386/call2.s: Likewise.
	* ld-i386/got1.dd: Likewise.
	* ld-i386/got1.out: Likewise.
	* ld-i386/got1a.S: Likewise.
	* ld-i386/got1b.c: Likewise.
	* ld-i386/got1c.c: Likewise.
	* ld-i386/got1d.S: Likewise.
	* ld-i386/jmp1.d: Likewise.
	* ld-i386/jmp1.s: Likewise.
	* ld-i386/jmp2.d: Likewise.
	* ld-i386/jmp2.s: Likewise.
	* ld-i386/load1.d: Likewise.
	* ld-i386/load1.s: Likewise.
	* ld-i386/load2.d: Likewise.
	* ld-i386/load2.s: Likewise.
	* ld-i386/load3.d: Likewise.
	* ld-i386/load3.s: Likewise.
	* ld-i386/load4.s: Likewise.
	* ld-i386/load4a.d: Likewise.
	* ld-i386/load4b.d: Likewise.
	* ld-i386/load5.s: Likewise.
	* ld-i386/load5a.d: Likewise.
	* ld-i386/load5b.d: Likewise.
	* ld-i386/load6.d: Likewise.
	* ld-i386/load6.s: Likewise.
	* ld-i386/i386.exp: Run branch1, call1, call2, jmp1, jmp2,
	load1, load2, load3, load4a, load4b, load5a, load5b and load6
	tests.  Run got1 test.
2015-10-22 04:47:07 -07:00
Alan Modra
4ee3febded Fix tests for PR 18500, revisited
Correct commit a846e9c1.

	PR gas/18500
	* gas/arm/vfpv2-ldr_immediate.d: Use parentheses, not brackets,
	to select alternatives.
	* gas/arm/vfpv3-ldr_immediate.d: Likewise.
	* gas/arm/vfpv3xd-ldr_immediate.d: Likewise.
2015-10-22 12:49:17 +10:30
Nick Clifton
a846e9c187 Fix tests for PR 18500 so that they will pass for big-endian ARM toolchains.
PR gas/18500
	* gas/arm/vfpv3xd-ldr_immediate.d: Update test for big-endian ARM
	toolchains.
	* gas/arm/vfpv3-ldr_immediate.d: Likewise.
	* gas/arm/vfpv2-ldr_immediate.d: Likewise.
2015-10-21 17:25:28 +01:00
Nick Clifton
1283d92f0e Extend description of the --enable-compressed-debug-sections configure option in gas and ld. 2015-10-21 14:57:28 +01:00
Nick Clifton
6c3bc0f82c Reset x86 Linux targets to not compressing debug sections by default. Enable compression of debug sections by default in the linker, if so configured.
PR gas/19109
.	* configure.ac: Note the 'none' is an acceptable argument to
	--enable-compressed-debug-sections.
	* configure: Regenerate.

gas	* configure.ac: Restore --enable-compressed-debug-sections.
	Do not enable compressed debug sections by default for x86 Linux
	targets.
	* configure: Regenerate.

ld	* configure.ac: Add --enable-compressed-debug-sections.
	* configure: Regenerate.
	* config.in: Regenerate.
	* ld.texinfo: Document how to determine the default action for
	debug sections.
	* ldmain.c (main): If DEFAULT_FLAG_COMPRESS_DEBUG is defined then
	set the compress_debug field of the link_info structure to
	zlib-gabi.
	* lexsup.c (elf_static_list_options): Output the default setting
	for the --compress-debug-sections option.
	* NEWS: Mention the new configure option.
2015-10-21 13:15:39 +01:00
H.J. Lu
edeefb6792 Add --enable-compressed-debug-sections={all,gas,gold,ld}
This patch removes the gas configure option:

--enable-compressed-debug-sections

and adds a toplevel configure option:

--enable-compressed-debug-sections={all,gas,gold,ld}

to enable compressed debug sections for gas, gold or ld by default.  At
the moment, this configure option is ignored by gold and ld.  For x86
Linux targets, default to compressing debug sections in gas.

	PR gas/19109
	* configure.ac: Add
	--enable-compressed-debug-sections={all,gas,gold,ld}.
	* configure: Regenerated.

gas/

	PR gas/19109
	* NEWS: Update --enable-compressed-debug-sections=.
	* configure.ac: Remove --enable-compressed-debug-sections.
	(DEFAULT_FLAG_COMPRESS_DEBUG): Check
	--enable-compressed-debug-sections={all,gas} instead of
	--enable-compressed-debug-sections.  For x86 Linux targets,
	default to compressing debug sections.
	* configure: Regenerated.
2015-10-20 08:58:25 -07:00
Nick Clifton
e12fe5554c Add a gas configure option to select the default behaviour for the generation of debug sections - compressed or uncompressed.
PR gas/19109
	* configure.ac: Add option --enable-compressed-debug-sections.
	This sets the default behaviour for compressing debug sections.
	* as.c (flag_compress_debug): Define and initialise to
	COMPRESS_DEBUG_GABI_ZLIB if DEFAULT_COMPRESS_DEBUG is set.
	(show_usage): Indicate whether --no-compress-debug-sections
	or --compress-debug-sections is the default.
	* config/tc-i386.c (flag_compress_debug): Delete definition.
	* doc/as.texinfo (--nocompress-debug-sectionas): Update
	description.
	* NEWS: Announce the new feature.
	* config.in: Regenerate.
	* configure: Regenerate.
2015-10-19 11:45:54 +01:00
Andreas Krebbel
485f23cf5c Add missing changelog entries 2015-10-14 12:19:39 +02:00
Andreas Krebbel
c46eb7b88a S/390: Fix instruction type of troo, trot, trto, and trtt.
opcodes/ChangeLog:

2015-10-14  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>

	* s390-opc.c: Fix comment.
	* s390-opc.txt: Change instruction type for troo, trot, trto, and
	trtt to RRF_U0RER since the second parameter does not need to be a
	register pair.

gas/testsuite/ChangeLog:

2015-10-14  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>

	* gas/s390/esa-g5.d: Use odd GPR for the second operand.
	* gas/s390/esa-g5.s: Likewise.
	* gas/s390/esa-z9-109.d: Likewise.
	* gas/s390/esa-z9-109.s: Likewise.
2015-10-14 10:58:41 +02:00
Nick Clifton
ede77e6963 Update list of known MSP430 MCU names.
* config/tc-msp430.c (msp430_mcu_names): Rename to
	msp430_mcu_data.  Add fields for the ISA and hardware multiply
	support.  Update with information from the latest devices.csv
	file.
	(md_parse_option): Make use of the new array.
2015-10-12 11:51:05 +01:00
Andrew Burgess
431ff0756a avr: Fix bugs in org/align tracking.
This commit fixes a few issues in the mechanism for passing information
about ".org" and ".align" directives from the assembler to the linker,
used by the avr target.

In the original commit fdd410ac7a, there
were some mistakes when writing out information about ".align"
directives:
  - An align with fill does not write out its information correctly, the
    fill data overwrites the alignment data.
  - Each alignment directive is recorded at the location where the
    previous alignment directive should be recorded, the first alignment
    directive is discarded.

In commit 137c83d69f, the data produced by
objdump is not correct:
   - It's miss-aligned due to a missing whitespace.
   - The fill data for align with fill records is not displayed
     correctly.

All of the above issues are addressed in this commit, and the test is
improved to cover these cases.

binutils/ChangeLog:

	* od-elf32_avr.c (elf32_avr_dump_avr_prop): Fix printing of align
	specific data, fix formatting for align and org data.

gas/ChangeLog:

	* config/tc-avr.c (avr_output_property_record): Fix overwrite bug
	for align and fill records.
	(avr_handle_align): Record fill information for align frags.
	(create_record_for_frag): Add next frag assertion, use correct
	address for align records.

gas/testsuite/ChangeLog:

	* gas/avr/avr-prop-1.s: Use fill in some cases.
	* gas/avr/avr-prop-1.d: Update expected results.
2015-10-12 09:43:11 +01:00
Alan Modra
d980077618 Bug 19113 - read.c stringer assertion
Fails due to signed char promotion.

	PR gas/19113
	* read.c (next_char_of_string): Mask char after escape.  Use
	CHAR_MASK rather than 0xff.
2015-10-10 10:51:20 +10:30
Yao Qi
875880c661 Avoid using 'template' C++ keyword
'template' is used in include/opcode/aarch64.h as below,

 typedef struct
 {
   const char *template;
   uint32_t value;
   int has_xt;
 } aarch64_sys_ins_reg;

and it triggers compilation errors when GDB is built in C++ mode.

In file included from git/gdb/aarch64-tdep.c:62:0:
git/gdb/../include/opcode/aarch64.h:651:15: error: expected unqualified-id before 'template'
   const char *template;

This patch is to rename field template to name.

gas/

	* config/tc-aarch64.c (md_begin): Access field 'name' rather
	than 'template'.

include/opcode/

	* aarch64.h (aarch64_sys_ins_reg) <template>: Removed.
	<name>: New field.

opcodes/

	* aarch64-dis.c (aarch64_ext_sysins_op): Access field
	'name' rather than 'template'.
	* aarch64-opc.c (aarch64_print_operand): Likewise.
2015-10-07 15:22:47 +01:00
Nick Clifton
886a250647 New ARC implementation.
bfd	* archures.c: Remove support for older ARC. Added support for new
	ARC cpus (ARC600, ARC601, ARC700, ARCV2).
	* bfd-in2.h: Likewise.
	* config.bfd: Likewise.
	* cpu-arc.c: Likewise.
	* elf32-arc.c: Totally changed file with a refactored
	inplementation of the ARC port.
	* libbfd.h: Added ARC specific relocation types.
	* reloc.c: Likewise.

gas     * config/tc-arc.c: Revamped file for ARC support.
        * config/tc-arc.h: Likewise.
        * doc/as.texinfo: Add new ARC options.
        * doc/c-arc.texi: Likewise.

ld	* configure.tgt: Added target arc-*-elf* and arc*-*-linux-uclibc*.
	* emulparams/arcebelf_prof.sh: New file
	* emulparams/arcebelf.sh: Likewise.
	* emulparams/arceblinux_prof.sh: Likewise.
	* emulparams/arceblinux.sh: Likewise.
	* emulparams/arcelf_prof.sh: Likewise.
	* emulparams/arcelf.sh: Likewise.
	* emulparams/arclinux_prof.sh: Likewise.
	* emulparams/arclinux.sh: Likewise.
	* emulparams/arcv2elfx.sh: Likewise.
	* emulparams/arcv2elf.sh: Likewise.
	* emultempl/arclinux.em: Likewise.
	* scripttempl/arclinux.sc: Likewise.
	* scripttempl/elfarc.sc: Likewise.
	* scripttempl/elfarcv2.sc: Likewise
	* Makefile.am: Add new ARC emulations.
	* Makefile.in: Regenerate.
	* NEWS: Mention the new feature.

opcodes * arc-dis.c: Revamped file for ARC support
	* arc-dis.h: Likewise.
	* arc-ext.c: Likewise.
	* arc-ext.h: Likewise.
	* arc-opc.c: Likewise.
	* arc-fxi.h: New file.
	* arc-regs.h: Likewise.
	* arc-tbl.h: Likewise.

binutils * readelf.c (get_machine_name): Remove A5 reference. Add ARCompact
	and ARCv2.
	(get_machine_flags): Handle EM_ARCV2 and EM_ARCOMPACT.
	(guess_is_rela): Likewise.
	(dump_relocations): Likewise.
	(is_32bit_abs_reloc): Likewise.
	(is_16bit_abs_reloc): Likewise.
	(is_none_reloc): Likewise.
	* NEWS: Mention the new feature.

include	* dis-asm.h (arc_get_disassembler): Correct declaration.
	* arc-reloc.def: Macro file with definition of all relocation
	types.
	* arc.h: Changed macros for the newly supported ARC cpus.  Altered
	enum defining the supported relocations.
	* common.h: Changed EM_ARC_A5 definition to EM_ARC_COMPACT. Added
	macro for EM_ARC_COMPACT2.
        * arc-func.h: New file.
        * arc.h: Likewise.
2015-10-07 14:20:19 +01:00
Renlin Li
43a357f99f [GAS][AARCH64]Add TLSDESC large memory model support.
bfd/

2015-10-02  Renlin Li <renlin.li@arm.com>

	* elfnn-aarch64.c (elfNN_aarch64_howto_table): Check overflow for
	BFD_RELOC_AARCH64_TLSDESC_OFF_G1.

gas/

2015-10-02  Renlin Li <renlin.li@arm.com>

	* config/tc-aarch64.c (s_tlsdescadd): New.
	(s_tlsdescldr): New.
	(md_pseudo_table): Handle tlsdescadd and tlsdescldr pseudo ops.
	(reloc_table): Add entries for BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC and
	BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC.
	(process_movw_reloc_info): Support AARCH64_TLSDESC_OFF_G1 and
	    AARCH64_TLSDESC_OFF_G0_NC.
	(md_apply_fix): Likewise.
	(aarch64_force_relocation): Likewise.

gas/testsuite/

2015-10-02  Renlin Li <renlin.li@arm.com>

	* gas/aarch64/reloc-tlsdesc_off_g0_nc.d: New.
	* gas/aarch64/reloc-tlsdesc_off_g0_nc.s: New.
	* gas/aarch64/reloc-tlsdesc_off_g1.d: New.
	* gas/aarch64/reloc-tlsdesc_off_g1.s: New.
	* gas/aarch64/tls-desc.d: New.
	* gas/aarch64/tls-desc.s: New.
2015-10-02 17:56:09 +01:00
Renlin Li
3b957e5b07 [Binutils][AARCH64]Add TLS IE large memory support.
bfd/

2015-10-02  Renlin Li <renlin.li@arm.com>

	* reloc.c: Make AARCH64_TLSIE_MOVW_GOTTPREL_G1 and
	AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC defined in alphabetical order.
	* libbfd.h: Regenerate.
	* bfd-in2.h: Likewise.
	* elfnn-aarch64.c (elfNN_aarch64_howto_table): Make
	TLSIE_MOVW_GOTTPREL_G1 check overflow.
	(aarch64_reloc_got_type): Add support for TLSIE_MOVW_GOTTPREL_G1
	and TLSIE_MOVW_GOTTPREL_G0_NC.
	(elfNN_aarch64_final_link_relocate): Likewise.
	(elfNN_aarch64_relocate_section): Likewise.
	(elfNN_aarch64_gc_sweep_hook): Likewise.
	(elfNN_aarch64_check_relocs): Likewise.
	* elfxx-aarch64.c (_bfd_aarch64_elf_put_addend): Likewise.
	(_bfd_aarch64_elf_resolve_relocation): Likewise.

gas/

2015-10-02  Renlin Li <renlin.li@arm.com>

	* config/tc-aarch64.c (reloc_table): Add two entries for
	gottprel_g0_nc and gottprel_g1.
	(process_movw_reloc_info): Add support.
	(md_apply_fix): Likewise.
	(aarch64_force_relocation): Likewise.

gas/testsuite/

2015-10-02  Renlin Li <renlin.li@arm.com>

	* gas/aarch64/reloc-gottprel_g0_nc.d: New.
	* gas/aarch64/reloc-gottprel_g0_nc.s: New.
	* gas/aarch64/reloc-gottprel_g1.d: New.
	* gas/aarch64/reloc-gottprel_g1.s: New.

ld/testsuite/

2015-10-02  Renlin Li <renlin.li@arm.com>

	* ld-aarch64/tls-large-ie.d: New.
	* ld-aarch64/tls-large-ie.s: New.
	* ld-aarch64/aarch64-elf.exp: Run new test.
2015-10-02 17:56:08 +01:00
Renlin Li
3e8286c0d2 [GAS][AARCH64]Add BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC support.
bfd/

2015-10-02  Renlin Li <renlin.li@arm.com>

	* reloc.c (BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC): New entry.
	* elfnn-aarch64.c (elfNN_aarch64_howto_table): New entry for
	BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC.
	* libbfd.h: Regenerate.
	* bfd-in2.h: Likewise

gas/

2015-10-02  Renlin Li <renlin.li@arm.com>

	* config/tc-aarch64.c (reloc_table): New relocation modifier tlsgd_g0_nc.
	(process_movw_reloc_info): Support BFD_RELOC_AARCH64_TLSGD_MOVW_G1.
	(md_apply_fix): Likewise.
	(aarch64_force_relocation): Likewise.

gas/testsuite/

2015-10-02  Renlin Li <renlin.li@arm.com>

	* gas/aarch64/reloc-tlsgd_g0_nc.d: New.
	* gas/aarch64/reloc-tlsgd_g0_nc.s: New.
2015-10-02 17:56:08 +01:00