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Display system registers by their names when disassembling RL78 instructions.

Browse source 
PR binutils/19158
opcodes	* rl78-decode.opc: Add 's' print operator to instructions that
	access system registers.
	* rl78-decode.c: Regenerate.
	* rl78-dis.c (print_insn_rl78_common): Decode all system
	registers.

tests	* gas/rl78/pr19158.s: New test source file.
	* gas/rl78/pr19158.d: New test case.
	* gas/rl78/rl78.exp: Run the new test.
This commit is contained in:
Vinay Kumar 2015-10-27 14:49:02 +00:00 committed by Nick Clifton
parent 02f12cd466
commit 4666280441
8 changed files with 81 additions and 13 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

7
gas/testsuite/ChangeLog
View file

@ -1,3 +1,10 @@
2015-10-27 Nick Clifton <nickc@redhat.com>
PR binutils/19158
* gas/rl78/pr19158.s: New test source file.
* gas/rl78/pr19158.d: New test case.
* gas/rl78/rl78.exp: Run the new test.
2015-10-27 Nick Clifton <nickc@redhat.com>
PR binutils/19157

19
gas/testsuite/gas/rl78/pr19158.d Normal file
View file

@ -0,0 +1,19 @@
#objdump: -d --prefix-addresses --show-raw-insn
#name: PR19158: RL78: Show the system registers in disassembly
.*: +file format .*rl78.*
Disassembly of section .text:
0+000 <.*> 8e f8[ ]+mov[ ]+a, spl
0+002 <.*> 9e f8[ ]+mov[ ]+spl, a
0+004 <.*> ce f8 7b[ ]+mov[ ]+spl, #123
0+007 <.*> 61 ab f8[ ]+xch[ ]+a, spl
0+00a <.*> ae f8[ ]+movw[ ]+ax, sp
0+00c <.*> be f8[ ]+movw[ ]+sp, ax
0+00e <.*> cb f8 34 12[ ]+movw[ ]+sp, #0x1234
0+012 <.*> 61 ab fa[ ]+xch[ ]+a, psw
0+015 <.*> 61 ab f9[ ]+xch[ ]+a, sph
0+018 <.*> 61 ab fc[ ]+xch[ ]+a, cs
0+01b <.*> 61 ab fd[ ]+xch[ ]+a, es
0+01e <.*> 61 ab fe[ ]+xch[ ]+a, pmc
0+021 <.*> 61 ab ff[ ]+xch[ ]+a, mem

20
gas/testsuite/gas/rl78/pr19158.s Normal file
View file

@ -0,0 +1,20 @@
.text
.set sfr, 0xffff8
mov a, sfr
mov sfr, a
mov sfr, #123
xch a, sfr
.set sfrp, 0xffff8
movw ax, sfrp
movw sfrp, ax
movw sfrp, #0x1234
xch a, 0xffffa
xch a, 0xffff9
xch a, 0xffffc
xch a, 0xffffd
xch a, 0xffffe
xch a, 0xfffff

1
gas/testsuite/gas/rl78/rl78.exp
View file

@ -20,4 +20,5 @@
if [expr [istarget "rl78-*-*"]] then {
run_dump_test "pr19157"
run_dump_test "pr19158"
}

9
opcodes/ChangeLog
View file

@ -1,3 +1,12 @@
2015-10-27 Vinay Kumar <vinay.g@kpit.com>
PR binutils/19158
* rl78-decode.opc: Add 's' print operator to instructions that
access system registers.
* rl78-decode.c: Regenerate.
* rl78-dis.c (print_insn_rl78_common): Decode all system
registers.
2015-10-27 Vinay Kumar <vinay.g@kpit.com>
PR binutils/19157

18
opcodes/rl78-decode.c
View file

@ -2477,14 +2477,14 @@ rl78_decode_opcode (unsigned long pc AU,
break;
case 0xab:
{
/** 0110 0001 1010 1011 xch %0, %1 */
/** 0110 0001 1010 1011 xch %0, %s1 */
if (trace)
{
printf ("\033[33m%s\033[0m %02x %02x\n",
"/** 0110 0001 1010 1011 xch %0, %1 */",
op[0], op[1]);
}
SYNTAX("xch %0, %1");
SYNTAX("xch %0, %s1");
#line 1232 "rl78-decode.opc"
ID(xch); DR(A); SM(None, SFR);
@ -4566,14 +4566,14 @@ rl78_decode_opcode (unsigned long pc AU,
break;
case 0x9e:
{
/** 1001 1110 mov %0, %1 */
/** 1001 1110 mov %s0, %1 */
if (trace)
{
printf ("\033[33m%s\033[0m %02x\n",
"/** 1001 1110 mov %0, %1 */",
op[0]);
}
SYNTAX("mov %0, %1");
SYNTAX("mov %s0, %1");
#line 780 "rl78-decode.opc"
ID(mov); DM(None, SFR); SR(A);
@ -4979,14 +4979,14 @@ rl78_decode_opcode (unsigned long pc AU,
break;
case 0xbe:
{
/** 1011 1110 movw %0, %1 */
/** 1011 1110 movw %s0, %1 */
if (trace)
{
printf ("\033[33m%s\033[0m %02x\n",
"/** 1011 1110 movw %0, %1 */",
"/** 1011 1110 movw %s0, %1 */",
op[0]);
}
SYNTAX("movw %0, %1");
SYNTAX("movw %s0, %1");
#line 901 "rl78-decode.opc"
ID(mov); W(); DM(None, SFR); SR(AX);
@ -5098,14 +5098,14 @@ rl78_decode_opcode (unsigned long pc AU,
break;
case 0xcb:
{
/** 1100 1011 movw %0, #%1 */
/** 1100 1011 movw %s0, #%1 */
if (trace)
{
printf ("\033[33m%s\033[0m %02x\n",
"/** 1100 1011 movw %0, #%1 */",
op[0]);
}
SYNTAX("movw %0, #%1");
SYNTAX("movw %s0, #%1");
#line 898 "rl78-decode.opc"
ID(mov); W(); DM(None, SFR); SC(IMMU(2));

8
opcodes/rl78-decode.opc
View file

@ -776,7 +776,7 @@ rl78_decode_opcode (unsigned long pc AU,
break;
}
/** 1001 1110 mov %0, %1 */
/** 1001 1110 mov %s0, %1 */
ID(mov); DM(None, SFR); SR(A);
/*----------------------------------------------------------------------*/
@ -894,10 +894,10 @@ rl78_decode_opcode (unsigned long pc AU,
/** 1011 1101 movw %0, %1 */
ID(mov); W(); DM(None, SADDR); SR(AX);
/** 1100 1011 movw %0, #%1 */
/** 1100 1011 movw %s0, #%1 */
ID(mov); W(); DM(None, SFR); SC(IMMU(2));
/** 1011 1110 movw %0, %1 */
/** 1011 1110 movw %s0, %1 */
ID(mov); W(); DM(None, SFR); SR(AX);
/*----------------------------------------------------------------------*/
@ -1228,7 +1228,7 @@ rl78_decode_opcode (unsigned long pc AU,
/** 0110 0001 1010 1000 xch %0, %1 */
ID(xch); DR(A); SM(None, SADDR);
/** 0110 0001 1010 1011 xch %0, %1 */
/** 0110 0001 1010 1011 xch %0, %s1 */
ID(xch); DR(A); SM(None, SFR);
/** 0000 1000 xch a, x */

12
opcodes/rl78-dis.c
View file

@ -265,6 +265,18 @@ print_insn_rl78_common (bfd_vma addr, disassemble_info * dis, RL78_Dis_Isa isa)
PR (PS, "psw");
else if (oper->addend == 0xffff8 && do_sfr && opcode.size == RL78_Word)
PR (PS, "sp");
else if (oper->addend == 0xffff8 && do_sfr && opcode.size == RL78_Byte)
PR (PS, "spl");
else if (oper->addend == 0xffff9 && do_sfr && opcode.size == RL78_Byte)
PR (PS, "sph");
else if (oper->addend == 0xffffc && do_sfr && opcode.size == RL78_Byte)
PR (PS, "cs");
else if (oper->addend == 0xffffd && do_sfr && opcode.size == RL78_Byte)
PR (PS, "es");
else if (oper->addend == 0xffffe && do_sfr && opcode.size == RL78_Byte)
PR (PS, "pmc");
else if (oper->addend == 0xfffff && do_sfr && opcode.size == RL78_Byte)
PR (PS, "mem");
else if (oper->addend >= 0xffe20)
PR (PS, "%#x", oper->addend);
else