2005-01-31 Jan Beulich <jbeulich@novell.com>
* config/tc-ia64.c (emit_one_bundle): Snapshot manual bundling state
before actually using it. Don't generate an error in manual bundling
mode when looking at an insn requiring slot 2 but not yet at slot 2.
Don't generate an error in manual bundling mode when looking at an
insn required to be last in its group but the required slot hasn't
been reached, yet. Allow conversion from MII to MI;I for bundle
consisting of only 2 insns with the stop between them. Suppress
various meaningless errors resulting from detecting earlier ones.
gas/testsuite/
2005-01-31 Jan Beulich <jbeulich@novell.com>
* gas/ia64/bundling.[ds]: New.
* gas/ia64/label.[ls]: New.
* gas/ia64/last.[ls]: New.
* gas/ia64/slot2.[ls]: New.
* gas/ia64/ia64.exp: Run new tests.
2005-01-31 Jan Beulich <jbeulich@novell.com>
* config/tc-ia64.c (parse_operands): Also handle alloc without first
input being ar.pfs.
gas/testsuite/
2005-01-31 Jan Beulich <jbeulich@novell.com>
* gas/ia64/pseudo.[ds]: New.
* gas/ia64/ia64.exp: Run new test.
opcodes/
2005-01-31 Jan Beulich <jbeulich@novell.com>
* ia64-gen.c (NELEMS): Define.
(shrink): Generate alias with missing second predicate register when
opcode has two outputs and these are both predicates.
* ia64-opc-i.c (FULL17): Define.
(ia64_opcodes_i): Add mov-to-pr alias without second input. Use FULL17
here to generate output template.
(TBITCM, TNATCM): Undefine after use.
* ia64-opc-m.c (ia64_opcodes_i): Add alloc alias without ar.pfs as
first input. Add ld16 aliases without ar.csd as second output. Add
st16 aliases without ar.csd as second input. Add cmpxchg aliases
without ar.ccv as third input. Add cmp8xchg16 aliases without ar.csd/
ar.ccv as third/fourth inputs. Consolidate through...
(CMPXCHG_acq, CMPXCHG_rel, CMPXCHG_1, CMPXCHG_2, CMPXCHG_4, CMPXCHG_8,
CMPXCHGn, CMP8XCHG16, CMPXCHG_ALL): Define.
* ia64-asmtab.c: Regenerate.
2005-01-28 Jan Beulich <jbeulich@novell.com>
* config/tc-ia64.c (ia64_estimate_size_before_relax): Allocate space
for personality routine pointer only if there is one.
(ia64_convert_frag): Likewise.
(generate_unwind_image): Likewise.
ld/testsuite/
2005-01-28 Jan Beulich <jbeulich@novell.com>
* ld/ia64/tlsbin.[rt]d: Widen expected offset/size ranges.
* ld/ia64/tlspic.[rt]d: Likewise.
(md_apply_fix3): Make relative branches out of range an error
instead of a warning. Display correct line number for out of
range branches/calls/memory accesses.
2005-01-27 Jan Beulich <jbeulich@novell.com>
* config/tc-ia64.c (emit_one_bundle): Change "?imbf??" to "?ibmfxx".
gas/testsuite/
2005-01-27 Jan Beulich <jbeulich@novell.com>
* gas/ia64/nop_x.[ds]: New.
* gas/ia64/ia64.exp: Run new test.
2005-01-25 Jan Beulich <jbeulich@novell.com>
* config/tc-ia64.c (emit_one_bundle): Add late resolution of move
to/from application registers dynamic insns.
(md_assemble): Defer resolution of move to/from application registers
dynamic insns when they can be issued on either the I- or M-units.
gas/testsuite/
2005-01-25 Jan Beulich <jbeulich@novell.com>
* gas/ia64/dv-waw-err.l: Don't expect ar112 move warning to refer to
M-unit.
* gas/ia64/mov-ar.[ds]: New.
* gas/ia64/ia64.exp: Run new test.
* config/tc-ia64.c (md): Add member "loc_directive_seen".
(dot_loc): New function.
(md_pseudo_table): Add entry to map .loc to dot_loc().
(emit_one_bundle): Only call dwarf2_gen_line_info() if we have
seen a .loc directive or we're generating DWARF2 debug info for
assembly source.
* v850.h (R_V850_LO16_SPLIT_OFFSET): New reloc.
bfd/
* reloc.c (BFD_RELOC_V850_LO16_SPLIT_OFFSET): New bfd_reloc_code_type.
* elf32-v850.c (v850_elf_howto_table): Add entry for
R_V850_LO16_SPLIT_OFFSET.
(v850_elf_reloc_map): Map it to BFD_RELOC_V850_LO16_SPLIT_OFFSET.
(v850_elf_perform_lo16_relocation): New function, extracted from...
(v850_elf_perform_relocation): ...here. Use it to handle
R_V850_LO16_SPLIT_OFFSET.
(v850_elf_check_relocs, v850_elf_final_link_relocate): Handle
R_V850_LO16_SPLIT_OFFSET.
* libbfd.h, bfd-in2.h: Regenerate.
gas/
* config/tc-v850.c (handle_lo16): New function.
(v850_reloc_prefix): Use it to check lo().
(md_assemble, md_apply_fix3): Handle BFD_RELOC_V850_LO16_SPLIT_OFFSET.
gas/testsuite/
* gas/v850/split-lo16.{s,d}: New test.
* gas/v850/v850.exp: Run it.
ld/testsuite/
* ld-v850: New directory.
2004-12-15 Jan Beulich <jbeulich@novell.com>
* config/obj-elf.c (obj_elf_change_section): Only set type and
attributes on new sections. Emit warning when type of re-declared
section doesn't match.
gas/testsuite/
2004-12-15 Jan Beulich <jbeulich@novell.com>
* gas/elf/section5.[els]: New.
* configure.in: Use it for arm*-*-linux-gnueabi*.
* config/tc-arm.c: Allow emulation file to set FPU_DEFAULT.
* config/te-armlinuxeabi.h: New file.
* Makefile.in: Regenerated.
* aclocal.m4: Likewise.
* configure: Likewise.
* doc/Makefile.in: Regenerated.
2004-11-25 Jan Beulich <jbeulich@novell.com>
* config/tc-i386.c (optimize_imm): Adjust immediates to only those
permissible for the selected instruction suffix.
(process_suffix): For DefaultSize instructions, suppressing the
guessing of a 'q' suffix if the instruction doesn't support it is
pointless, because only an 'l' suffix can be guessed in this place.
gas/testsuite/
2004-11-25 Jan Beulich <jbeulich@novell.com>
* gas/i386/x86-64-inval.[sl]: Remove sahf/lahf.
include/opcode/
2004-11-25 Jan Beulich <jbeulich@novell.com>
* i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
to/from test registers are illegal in 64-bit mode. Add missing
NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
(previously one had to explicitly encode a rex64 prefix). Re-enable
lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
They should be correct now.
* gas/mn10300/relax.s: Add further tests of the relaxing of branch instructions.
* gas/mn10300/relax.d: Add expected relocations.
2004-11-23 Jan Beulich <jbeulich@novell.com>
* config/tc-i386.h (CpuMMX2): Declare. Artificial classifier to
indicate the MMX extensions added by both SSE and 3DNow!A.
(Cpu3dnowA): Declare.
(CpuUnknownFlags): Update.
* config/tc-i386.c (cpu_sub_arch_name): Declare.
(cpu_arch): i586 and pentium do not imply MMX. i686 and pentiumpro do
neither imply SSE nor MMX. k6 implies MMX. k6_2 additionally implies
3DNow!. Athlon additionally implies 3DNow!A. Several new
entries (those starting with a dot are for sub-arch specification).
(set_cpu_arch): Handle sub-arch specifications.
(parse_insn): Distinguish between instructions not supported because
of insufficient CPU features and because of 64-bit mode.
* doc/c-i386.texi: Describe enhanced .arch directive.
include/opcode/
2004-11-23 Jan Beulich <jbeulich@novell.com>
* i386.h (i386_optab): paddq and psubq, even in their MMX form, are
available only with SSE2. Change the MMX additions introduced by SSE
and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
instructions by their now designated identifier (since combining i686
and 3DNow! does not really imply 3DNow!A).
include/ChangeLog
* xtensa-isa-internal.h (xtensa_interface_internal): Add class_id.
* xtensa-isa.h (xtensa_interface_class_id): New prototype.
bfd/ChangeLog
* xtensa-isa.c (xtensa_interface_class_id): New.
gas/ChangeLog
* config/tc-xtensa.c (finish_vinsn): Clear pending instruction if
there is a conflict.
(check_t1_t2_reads_and_writes): Check for both reads and writes to
interfaces that are related as determined by xtensa_interface_class_id.
* config/tc-xtensa.c (MAX_IMMED6): Change value to 65.
gas/testsuite/
* gas/xtensa/short_branch_offset.s: New.
* gas/xtensa/short_branch_offset.d: New.
* gas/xtensa/all.exp: Run new test.
