Commit graph

57 commits

Author SHA1 Message Date
Andrew Cagney
95469cebdd Replace global IPC with function argument cia or current instruction
address.
Pass cia into calls to sim_engine_stop so that breakpoints et.al. work.
1997-11-06 14:24:57 +00:00
Gavin Romig-Koch
6205f37913 * gencode.c: Add tx49 configury and insns.
* configure.in: Add tx49 configury.
	* configure: Update.
1997-10-29 19:42:49 +00:00
Gavin Romig-Koch
635ae9cb7c * sim/mips/gencode.c (build_instruction): Follow sim_write's lead in using
BigEndianMem instead of !ByteSwapMem.
1997-10-25 20:53:46 +00:00
Andrew Cagney
dad6f1f326 Add function to fetch 32bit instructions
When address translation of insn fetch fails raise exception immediatly.
Use address_word as type of all address variables (instead of unsigned64),
the former is configured as either 32 or 64 bit type.
Always compile fpu code (no #if has fpu)
1997-10-24 06:43:51 +00:00
Andrew Cagney
ea985d2472 Move register definitions and macros out of interp.c and into sim-main.h 1997-10-16 03:50:48 +00:00
Andrew Cagney
339fb14904 * gencode.c (build_instruction): Use FPR_STATE not fpr_state. 1997-10-16 03:29:47 +00:00
Andrew Cagney
8b70f83790 * gencode.c (build_instruction): For "FPSQRT", output correct number
of arguments to Recip.
1997-10-16 03:23:16 +00:00
Andrew Cagney
18c64df613 o Add support for configuring wordsize, fp hardware and target
endianness.  Provide defaults for some tier-1 mips targets.
o	Parameterize all functions with SIM_DESC.
1997-10-14 07:27:31 +00:00
Andrew Cagney
af51b8d56d Add/use SIM_AC_OPTION_BITSIZE. 1997-09-25 07:19:05 +00:00
Andrew Cagney
e63bc706fe Allow gencode.c to generate input to the igen generator. 1997-09-25 04:23:24 +00:00
Gavin Romig-Koch
c476ac5560 Add handling for 3900's SDBBP, DERET, and RFE insns.
* gencode.c (SDBBP,DERET): Added (3900) insns.
	(RFE): Turn on for 3900.
	* interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
	(dsstate): Made global.
	(SUBTARGET_R3900): Added.
	(CANCELDELAYSLOT): New.
	(SignalException): Ignore SystemCall rather than ignore and
	terminate.  Add DebugBreakPoint handling.
	(decode_coproc): New insns RFE, DERET; and new registers Debug
	and DEPC protected by SUBTARGET_R3900.
	(sim_engine_run): Use CANCELDELAYSLOT rather than clearing
	bits explicitly.
	* Makefile.in,configure.in: Add mips subtarget option.
	* configure: Update.
1997-09-20 18:22:22 +00:00
Gavin Romig-Koch
7afa8d4edc * gencode.c: Add r3900 (tx39).
* gencode.c: Fix some configuration problems by improving
	the relationship between tx19 and tx39.
1997-09-19 13:39:55 +00:00
Gavin Romig-Koch
667065d0d4 * sim/mips/gencode.c (build_instruction): Don't need to subtract 4 for
JALR, just 2.
1997-09-16 20:01:00 +00:00
Andrew Cagney
c31c13b481 Remove GCC specific `0x...LL', replace with SIGNED64 (0x...). 1997-09-09 07:02:02 +00:00
Gavin Romig-Koch
b637f306ba tx19 and related necessary changes.
* config.sub: Add tx19/r1900.
	* sim/mips/configure.in, sim/mips/gencode: Add tx19/r1900.
	* gcc/config.sub, gcc/configure: Add tx19/r1900.
	* gcc/config/mips/r1900.h, config/mips/t-r1900: New.
	* gas/config/tc-mips.c: Add tx19/r1900.

	* gcc/config/mips/mips.c: Don't build 16 bit to 32 bit stubs for
	TARGET_SOFT_FLOAT.

	* config.sub: Add "marketing-names" patch.
	* gcc/config.sub: Add "marketing-names" patch.

	* gcc/configure: Change "as" link from "../gas/as.new" to "../gas/as-new";
	Same for "ld" link.
1997-09-07 20:33:22 +00:00
Andrew Cagney
52352d38d6 Test/fix pabsh, pabsw, psrlvw. 1997-09-01 09:47:03 +00:00
Andrew Cagney
247fccdeb5 Add ABFD argument to sim_open call. Pass through to sim_config so
that image properties such as endianness can be checked.

More strongly document the expected behavour of each of the sim_*
interfaces.

Add default endian argument to simulator config macro
SIM_AC_OPTION_ENDIAN.  Use in sim_config.
1997-08-25 23:14:25 +00:00
Andrew Cagney
9204a35e78 Handle overflow from signed divide by -1. 1997-07-28 13:46:53 +00:00
Gavin Romig-Koch
c12e2e4c48 gencode.c: Two arg MADD should not assign result to /bin/bash. 1997-07-25 19:10:05 +00:00
Andrew Cagney
1e851d2c82 Fix a number of problems in the r5900 specific p* (parallel) instructions.
In particular a host endian dependency one fixed resolved most problems.
1997-07-11 03:07:29 +00:00
Jeff Law
6443523484 * gencode.c (build_instruction): Handle "pext5" according to
version 1.95 of the r5900 ISA.
Fixes pr12413 (c/h from toshiba).
1997-07-02 18:41:22 +00:00
Jeff Law
649625bb8e * gencode.c (build_instruction): Handle "ppac5" according to
version 1.95 of the r5900 ISA.
fixes pr12407 (c/h from toshiba).
1997-07-02 18:29:16 +00:00
Jeff Law
ae19b07bf8 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
Fix for pr12402 (c/h from toshiba).
1997-07-02 17:57:56 +00:00
Andrew Cagney
c7cebfa32c o Fix padd insn
o	Take an interrupt when an int event occures.
1997-06-02 15:00:43 +00:00
Andrew Cagney
50a2a69182 Watchpoint interface. 1997-05-21 06:54:13 +00:00
Gavin Romig-Koch
d654ba0acf for DIV: check for div by zero and int overflow 1997-04-21 21:26:17 +00:00
Gavin Romig-Koch
c94db67a25 Correct the overloaded DOUBLEWORD problem 1997-02-26 23:49:19 +00:00
Dawn Perchik
4580503f2c start-sanitize-r5900
* gencode.c: #ifdef out offending code until a permanent fix
	can be added.  Code is causing build errors for non-5900 mips targets.
end-sanitize-r5900
1997-02-25 07:04:39 +00:00
Gavin Romig-Koch
528031fd49 Correct test for ISA dependent bits 1997-02-20 15:48:57 +00:00
Gavin Romig-Koch
2d18fbc668 Correct flags for PMADDUW insn 1997-02-18 22:15:04 +00:00
Ian Lance Taylor
bd2f63470e * gencode.c (build_mips16_operands): Correct computation of base
address for extended PC relative instruction.
1997-02-13 19:08:55 +00:00
Gavin Romig-Koch
276c2d7dc8 Add r5900 1997-02-11 13:26:34 +00:00
Ian Lance Taylor
6389d8561c * gencode.c (build_instruction): The high order may be set in the
comparison flags at any ISA level, not just ISA 4.
1997-02-04 21:48:54 +00:00
Jim Wilson
b99125bc1c For NEC 4300 project, fix last remaining host/target endianness problem
* gencode.c (build_instruction): Use BigEndianCPU instead of
	ByteSwapMem.
1997-01-08 20:40:40 +00:00
Mark Alexander
39bf0ef4e6 * gencode.c (build_instruction): Work around MSVC++ code gen bug
that messes up arithmetic shifts.
1996-12-28 06:51:58 +00:00
Ian Lance Taylor
deffd638b5 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
force a 64 bit multiplication.
	(build_instruction) [OR]: In mips16 mode, don't do anything if the
	destination register is 0, since that is the default mips16 nop
	instruction.
1996-12-19 19:08:46 +00:00
Ian Lance Taylor
063443cf01 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
(build_endian_shift): Don't check proc64.
	(build_instruction): Always set memval to uword64.  Cast op2 to
	uword64 when shifting it left in memory instructions.  Always use
	the same code for stores--don't special case proc64.
1996-12-16 21:47:23 +00:00
Ian Lance Taylor
aaff84371e * gencode.c (build_mips16_operands): Fix base PC value for PC
relative operands.
	(build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
	jal instruction.
	* interp.c (simJALDELAYSLOT): Define.
 	(JALDELAYSLOT): Define.
	(INDELAYSLOT, INJALDELAYSLOT): Define.
	(simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
1996-12-16 20:01:15 +00:00
Jim Wilson
51c6d73375 For NEC 4100/4300 project: Add little endian support and misc cleanups.
* gencode.c (build_instruction): Use !ByteSwapMem instead of
	BigEndianMem.
	* interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
	(BigEndianMem): Rename to ByteSwapMem and change sense.
	(BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
	BigEndianMem references to !ByteSwapMem.
	(set_endianness): New function, with prototype.
	(sim_open): Call set_endianness.
	(sim_info): Use simBE instead of BigEndianMem.
	(xfer_direct_word, xfer_direct_long, swap_direct_word,
	swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
	xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
	ifdefs, keeping the prototype declaration.
	(swap_word): Rewrite correctly.
	(ColdReset): Delete references to CONFIG.  Delete endianness related
	code; moved to set_endianness.
1996-12-11 22:04:46 +00:00
Jim Wilson
6429b29698 For NEC 4100/4300 project
* gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
	* interp.c (CHECKHILO): Define away.
	(simSIGINT): New macro.
	(membank_size): Increase from 1MB to 2MB.
	(control_c): New function.
	(sim_resume): Rename parameter signal to signal_number.  Add local
	variable prev.  Call signal before and after simulate.
	(sim_stop_reason): Add simSIGINT support.
	(sim_warning, sim_error, dotrace, SignalException): Define as stdarg
	functions always.
	(sim_warning): Delete call to SignalException.  Do call printf_filtered
	if logfh is NULL.
	(AddressTranslation): Add #ifdef DEBUG around debugging message and
	a call to sim_warning.
1996-12-10 19:39:55 +00:00
Ian Lance Taylor
279cca90f4 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
16 bit instructions.
1996-11-27 16:54:21 +00:00
Ian Lance Taylor
831f59a218 Add support for mips16 (16 bit MIPS implementation):
* gencode.c (inst_type): Add mips16 instruction encoding types.
	(GETDATASIZEINSN): Define.
	(MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv.  Add
	jalx.  Add LEFT flag to mfhi and mflo.  Add RIGHT flag to mthi and
	mtlo.
	(MIPS16_DECODE): New table, for mips16 instructions.
	(bitmap_val): New static function.
	(struct mips16_op): Define.
	(mips16_op_table): New table, for mips16 operands.
	(build_mips16_operands): New static function.
	(process_instructions): If PC is odd, decode a mips16
	instruction.  Break out instruction handling into new
	build_instruction function.
	(build_instruction): New static function, broken out of
	process_instructions.  Check modifiers rather than flags for SHIFT
	bit count and m[ft]{hi,lo} direction.
	(usage): Pass program name to fprintf.
	(main): Remove unused variable this_option_optind.  Change
	``*loptarg++'' to ``loptarg++''.
	(my_strtoul): Parenthesize && within ||.
	* interp.c (sim_trace): If tracefh is NULL, set it to stderr.
	(LoadMemory): Accept a halfword pAddr if vAddr is odd.
	(simulate): If PC is odd, fetch a 16 bit instruction, and
	increment PC by 2 rather than 4.
	* configure.in: Add case for mips16*-*-*.
	* configure: Rebuild.
1996-11-26 18:12:44 +00:00
David Edelsohn
e3d12c6595 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
(SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
	* configure.in: Simplify using macros in ../common/aclocal.m4.
	* configure: Regenerated.
	* tconfig.in: New file.
1996-11-20 10:00:42 +00:00
Jackie Smith Cashion
21cea5d45d Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
* interp.c (SignalException): Check for explicit terminating
 	breakpoint value.
	* gencode.c: Pass instruction value through SignalException()
 	calls for Trap, Breakpoint and Syscall.
1996-09-26 16:42:57 +00:00
Ian Lance Taylor
149ee67274 * gencode.c (process_instructions): Call build_endian_shift when
expanding STORE RIGHT, to fix swr.
	* support.h (SIGNEXTEND): If the sign bit is not set, explicitly
	clear the high bits.
	* interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
	Fix float to int conversions to produce signed values.
1996-09-20 19:49:49 +00:00
Ian Lance Taylor
458e1f58e6 Fix multiplication, ldxc1, and floating point conversion. See ChangeLog. 1996-09-20 03:07:43 +00:00
Ian Lance Taylor
47c6ce6c2d * gencode.c (process_instructions): Correct shift count for 32
bit shift instructions.  Correct sign extension for arithmetic
	shifts to not shift the number of bits in the type.
1996-09-19 21:55:10 +00:00
Ian Lance Taylor
cc5201d78c * gencode.c (process_instructions): Correct handling of nor
instruction.
1996-09-19 19:35:09 +00:00
Jackie Smith Cashion
f24b7b69ee Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
* interp.c (sim_monitor): Improved monitor printf
 	simulation. Tidied up simulator warnings, and added "--log" option
 	for directing warning message output.
	* gencode.c: Use sim_warning() rather than WARNING macro.
1996-09-16 10:47:20 +00:00
Ian Lance Taylor
64d538ce80 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
getopt1.o, rather than on gencode.c.  Link objects together.
	Don't link against -liberty.
	(gencode.o, getopt.o, getopt1.o): New targets.
	* gencode.c: Include <ctype.h> and "ansidecl.h".
	(AND): Undefine after including "ansidecl.h".
	(ULONG_MAX): Define if not defined.
	(OP_*): Don't define macros; now defined in opcode/mips.h.
	(main): Call my_strtoul rather than strtoul.
	(my_strtoul): New static function.
1996-08-22 22:06:21 +00:00