Andrew Cagney
38d0ccc27a
Fix typo, REP_S was refering to REP_E register.
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Add test.
1997-12-08 23:44:11 +00:00
Andrew Cagney
bc6df23d14
For "trap", IBT and RIE exceptions, mask all PSW.SM. NB: Stepping
...
through an exception may not work correctly.
For GDB reads/writes to the control registers, ensure the cpu state is
updated correctly.
1997-12-08 03:22:58 +00:00
Andrew Cagney
7f48c9fe1d
Add DM (bit 4) to PSW. See 7-1 for more info.
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Test.
1997-12-04 07:01:30 +00:00
Andrew Cagney
aa49c64f3e
* d10v_sim.h (SEXT56): Define.
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* simops.c (OP_4201): For "rac", sign extend 56 bit value before
it is shifted.
* d10v_sim.h (MAX32, MIN32, MASK32, MASK40): Re-define using
SIGNED64 macro.
1997-12-03 08:03:33 +00:00
Andrew Cagney
d294a657d5
For "msbu", subtract unsigned product from ACC,
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Test.
1997-12-02 07:18:53 +00:00
Andrew Cagney
9420287ed2
For "mulxu", store unsigned product in ACC.
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Test.
1997-12-02 06:37:09 +00:00
Andrew Cagney
51b057f27b
For sub2w, compute carry according to negated addition rules.
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Test.
1997-12-02 00:27:27 +00:00
Andrew Cagney
51624b4bf6
Test rachi instruction.
1997-11-10 08:27:15 +00:00
