like all the other targets.
* doc/internals.texi (CPU backend): Add missing word in
md_flush_pending_output description. Fix typo in md_convert_frag
description.
start-sanitize-tic80
* config/tc-tic80: Minor comment additions/changes.
end-sanitize-tic80
does not actually work, though:
* configure.in (i386-sequent-bsd*): New target.
* configure: Rebuild.
* config/tc-dynix.h: New file.
* config/tc-i386.h: Define TARGET_FORMAT if TE_DYNIX.
tc-mn10200.h, tc-mn10300.h, tc-sh.h, tc-v850.h, tc-vax.h, tc-w65.h}:
Add default definition of zero for TARGET_BYTES_BIG_ENDIAN.
* config/{tc-arm.h, tc-hppa.h, tc-i386.h, tc-mips.h, tc-ns32k.h,
tc-ppc.h, tc-sparc.h}: Move definition of TARGET_BYTES_BIG_ENDIAN
to a location consistent with the rest of the target include files.
* config/tc-i386.c: Remove misleading comment.
* doc/internals.texi (CPU backend): Add description of function
md_undefined_symbol.
start-sanitize-tic80
* config/tc-tic80.c: Add code to insert predefined symbols into the
symbol table so they can be parsed by the standard expression parser.
Remove custom code that use to parse them.
* config/tc-tic80.h: Move definition of TARGET_BYTES_BIG_ENDIAN
to a location consistent with the rest of the target include files.
end-sanitize-tic80
(DVIPS): Set to dvips.
(ps, as.ps, gasp.ps): New targets.
(internals.info, gasp.dvi, internals.dvi): Set both TEXINPUTS
and MAKEINFO env variables.
(internals.ps): Use DVIPS macro.
(clean): Remove core and backup files.
(distclean): Remove temporary files from building internals.
(clean-dvi): Ditto.
* doc/internals.texi (Frags): Fix typo.
(GAS processing): Ditto.
(CPU backend): Ditto.
* ecoff.c (init_file): Use TARGET_BYTES_BIG_ENDIAN value directly.
* mpw-config.in: Define TARGET_BYTES_BIG_ENDIAN as 1.
* read.c: Remove ugly hack that dealt with config files not
correctly defining TARGET_BYTES_BIG_ENDIAN.
(target_big_endian): Use TARGET_BYTES_BIG_ENDIAN directly.
* config/arm-big.mt: Define TARGET_BYTES_BIG_ENDIAN to 1.
* config/arm-lit.mt: Define TARGET_BYTES_BIG_ENDIAN to 0.
* config/mips-big.mt: Define TARGET_BYTES_BIG_ENDIAN to 1.
* config/mips-lit.mt: Define TARGET_BYTES_BIG_ENDIAN to 0.
* config/ppc-lit.mt: Define TARGET_BYTES_BIG_ENDIAN to 1.
* config/ppc-sol.mt: Replace TARGET_BYTES_LITTLE_ENDIAN
with TARGET_BYTES_BIG_ENDIAN defined to 0.
* config/tc-arm.h: Remove use of TARGET_BYTES_LITTLE_ENDIAN
and simplify. Test value of TARGET_BYTES_BIG_ENDIAN, not just
whether it is defined or not.
* config/tc-mips.h: Remove use of TARGET_BYTES_LITTLE_ENDIAN.
* config/tc-ppc.h: Remove use of TARGET_BYTES_LITTLE_ENDIAN
and simplify. Test value of TARGET_BYTES_BIG_ENDIAN, not just
whether it is defined or not.
start-sanitize-tic80
* config/tic80.h (TARGET_FORMAT): Define to coff-tic80.
(TARGET_BYTES_BIG_ENDIAN): Define to 0.
end-sanitize-tic80
(prev_nop_frag_holds): New static variable.
(prev_nop_frag_required): New static variable.
(prev_nop_frag_since): New static variable.
(append_insn): If we aren't reordering, and prev_nop_frag is not
NULL, and we don't need any nops, then decrease the size of
prev_nop_frag. Don't insert nops because of instructions in
noreorder sections. Remember whether the previous instructions
where in noreorder sections even when not reordering.
(mips_no_prev_insn): Add preserver parameter. Change all
callers. Refer prev_nop_frag variables when appropriate.
(mips_emit_delays): Set up prev_nop_frag.
(s_mipsset): Clear prev_nop_frag if reordering.
extended instruction in a delay slot when not reordering. Set
prev_insn_valid even if not reordering.
(md_convert_frag): Warn if an extended instruction appears in a
delay slot.
symbol table.
(mips16_ip): First parse the expression, and then see whether it
came up with a register, rather than trying to first see whether
we are looking at a register.
(md_apply_fix): Handle BFD_RELOC_MIPS16_GPREL.
* config/tc-mips.c (append_insn): Output jump instruction as a
pair of 2 byte instructions, rather than as a single 4 byte
instruction.
start-sanitize-r5900
* config/tc-mips.c (md_begin): Correct test of mips_5900.
(mips_ip): Don't check INSN_ISA for a macro.
end-sanitize-r5900
instruction registers, opcodes and formats. Build internal table
for new instructions and provide callbacks for assembler and
disassembler.
* itbl-lex.l, itbl-parse.y: Lex and yacc parsers for instruction
spec table.
* itbl-ops.h: New file. Header file for itbl support.
* config/itbl-mips.h: New file. Mips specific definitions for
itbl support.
* config/tc-d10v.h (md_do_align): Add this hook to call
d10v_cleanup() when a ".align" is detected. Fixes PR11487.
* config/tc-d10v.c (find_opcode): Correctly calculate
branch displacement when .aligns are present.
(labels, current_label): New static variables.
(md_assemble): Mark current_label as text, and clear it.
(m68k_frob_label): New function.
(m68k_flush_pending_output): New function.
(m68k_frob_symbol): New function.
* config/tc-m68k.h (tc_frob_label): Define.
(md_flush_pending_output): Define.
(tc_frob_symbol): Don't warn, just call m68k_frob_symbol.
(tc_frob_coff_symbol): Likewise.
PR 11417.
to avoid warnings with the native HP compiler.
(fix_new_hppa): Similarly for the r_type argument.
(pa_build_unwind_subspace, hppa_elf_mark_end_of_function): Enclose
in an #if OBJ_ELF to keep gcc -Wall quiet.
(md_apply_fix): Always initialize "result".
Minor maintenance.
* config/tc-mn10200.c (md_assemble): Generate relocations.
mn10200 has relocs now!
* config/obj-elf.c (elf_file_symbol): When using ECOFF debugging,
pass on the new file hook.
* config/tc-alpha.c (alpha_fix_adjustable): Not quite the same as
!alpha_force_relocation, as local LITERALs can be adjusted to be
relative to the section.
immediate value.
(md_assemble): If the size is 'B', set fx_signed.
(md_apply_fix_2): Use fx_signed when checking for overflow.
* write.h (struct fix): Add fx_signed field.
* write.c (fix_new_internal): Initialize fx_no_overflow and
fx_signed fields.
(fixup_segment): Use fx_signed when checking for overflow.
* config/obj-coff.c (fixup_segment): Check fx_no_overflow and
fx_signed when checking for overflow.
* config/tc-m68k.c (m68k_index_width_default): New static
variable.
(m68k_ip): Use m68k_index_width_default to set the size of a base
register whose size was not given.
(md_longopts): Add --base-size-default-16 and
--base-size-default-32.
(md_parse_option): Handle new options.
(md_show_usage): Mention new options.
* doc/c-m68k.texi (M68K-Opts): Document new options.
includes config.h instead of host.h, tc.h instead of tp.h, and
targ-env.h instead of target-environment.h.
Also, obj-format.h includes targ-cpu.h instead of
target-processor.h.
start-sanitize-tic80
(Laying groundwork, that will be incrementally fleshed out,
for TIc80 support)
* configure.in (case ${generic_target}): Add tic80-*-coff entry.
* configure: Rebuild with autoconf.
* config/obj-coff.h (coff/tic80.h): Include if TC_TIC80 defined.
(TARGET_FORMAT): Define to "coff-tic80".
* config/tc-tic80.c: New file for TIc80 support.
* config/tc-tic80.h: New file for TIc80 support.
end-sanitize-tic80
(struct insn_label_list): Define.
(insn_labels, free_insn_labels): New static variables.
(mips_clear_insn_labels): New static function.
(append_insn): Mark all mips16 text labels, and make them odd.
Handle all labels after emitting a nop, not just one. Call
mips_clear_insn_labels rather than just clearing insn_label.
(mips_emit_delays): Add insns parameter, and use it to decide
whether to mark mips16 labels. Handle all labels, not just one.
Force mips16 labels to be odd. Change all callers.
(mips16_immed): Don't check for an odd branch target.
(md_apply_fix): Don't check mips16 mode for a branch reloc.
(mips16_extended_frag): Ignore the low bit in a branch target.
(md_convert_frag): Likewise.
(mips_no_prev_insn): Call mips_clear_insn_labels rather than just
clearing insn_label.
(mips_align, mips_flush_pending_output, s_cons): Likewise.
(s_float_cons, s_gpword): Likewise.
(s_align): Use insn_labels rather than insn_label.
(s_cons, s_float_cons, s_gpword): Likewise.
(mips_frob_file_after_relocs): New function.
(mips_define_label): Rewrite to add to insn_labels list.
* config/tc-mips.h (tc_frob_file_after_relocs): Define.
* ecoff.c (ecoff_build_symbols): If the size of a function comes
out odd, increment it.
(RELAX_MIPS16_ENCODE): Add dslot and jal_dslot arguments, and
store them. Adjust other RELAX_MIPS16 macros.
(RELAX_MIPS16_DSLOT): Define.
(RELAX_MIPS16_JAL_DSLOT): Define.
(append_insn): Pass new arguments to RELAX_MIPS16_ENCODE. Correct
handling of whether previous instruction has a fixup. Set
prev_insn_reloc_type.
(mips_no_prev_insn): Clear prev_insn_reloc_type.
(mips16_extended_frag): Use the right base address for a PC
relative add or load.
(md_convert_frag): Likewise. If a PC relative add or load is
used, record the alignment for the section.
system, don't set the section alignment to 2**4.
(s_change_sec): Likewise.
(append_insn): Call record_alignment for the section.
(md_section_align): Don't align the section size for an embedded
ELF system.
arguments, and store them. Adjust other RELAX_MIPS16 macros.
(RELAX_MIPS16_USER_SMALL): Define.
(RELAX_MIPS16_USER_EXT): Define.
(mips16_small, mips16_ext): New static variables.
(append_insn): Pass mips16_small and mips16_ext to
RELAX_MIPS16_ENCODE.
(mips16_ip): Set mips16_small and mips16_ext.
(mips16_immed): Don't check mips16_autoextend.
(mips16_extended_frag): Check USER_SMALL and USER_EXT.
* config/tc-d10v.c (md_assemble): Check to see if prev_seg
is initialized before using it.
(d10v_cleanup): No longer uses its argument, so make it void.
* config/tc-d10v.h (d10v_cleanup): Change prototype.
(tc_fix_adjustable): Don't adjust relocs against weak symbols or
pc-relative relocs.
* config/tc-mn10300.c (md_begin): Set linkrelax.
(md_assemble): Create fixups as needed.
(md_apply_fix3): Gut. It shouldn't ever get called anymore.
First stab at fixups/relocs.
the extension part of the instruction if necessary.
(mn10300_insert_operand): Accept pointer to extension word
argument. Make insn a pointer argument too. Return type
is now void. All callers changed.
So we can correct insert operands into any instruction except those
which have 32bit operands.
* config/tc-v850.c: Fix some indention problems.
(md_relax_table): Define for D9->D99 branch displacement
relaxing.
(md_convert_frag): Do something useful instead of aborting.
(md_estimate_size_before_relax): Likewise.
(md_assemble): Note if the matching instruction has a relaxable
operand. If it does, allocate frag with frag_var and don't
do any fixups.
So we can do 9bit displacement to 22bit displacement relaxing.
hacks to improve parsing of complex hi, lo, zda, etc
expressions.
(md_assemble): Don't demand and eat a trailing ')' after finding
a v850 relocation prefix. Sign extend the constant in a
BFD_RELOC_LO16 expression. Do eat a trailing ')' after a complete
operand.
(parse_cons_expression_v850): Don't eat a trailing ')' after
finding a v850 relocation prefix.
Trying to get nec's sample code to assemble. Why oh why didn't JT try
to assemble any of their code...
(TC_CONS_FIX_NEW): Likewise.
* config/tc-v850.c (parse_cons_expression_v850): New function.
(cons_fix_new_v850): Likewise.
So we can handle ".hword lo(_foo)".
(md_pcrel_from_section): New function.
* config/tc-v850.h (MD_PCREL_FROM_SECTION): Define.
So we don't screw up pc-relative jumps/calls from one section
into another section within the same .o file.
Fixes global ctors/dtors to work with DECL_ONE_ONLY stuff.
* config/obj-elf.c (elf_frob_file): Move ECOFF debug processing to ...
(elf_frob_file_after_relocs): ... here. New function.
* config/obj-elf.h (obj_from_file_after_relocs): New macro.
* write.c (write_object_file): Call *frob_after_relocs after the
call to write_relocs.
* config/tc-alpha.c: Use new BFD_RELOC_ALPHA_ELF_LITERAL reloc.
* config/tc-alpha.c (load_expression): Don't SET_VALUE on the section
symbol, as this messes up linking. Instead, expand the recursive call
inline and change up the appropriate bits to get the 0x8000 offset
in the reloc addend.
(obj_elf_section): Add the section symbol to the symbol table.
* config/obj-elf.h (obj_begin): Define.
(elf_begin): Declare.
* as.c (perform_an_assembly_pass): Call obj_begin if it is
defined.
* obj-evax.h: move openvms definitions from here to tc-alpha.c.
* tc-alpha.c: add support for vms_case_hack like in vax/vms.
(load_expression): track clobbering of base reg before jmp/jsr.
(s_alpha_file): pass case_hack flags and source filename via
symbol table to bfd.
* tc-alpha.h (TC_CONS_FIX_NEW): define
mips_cpu is 5000, set interlocks and cop_interlocks.
(mips_ip): Give a better error message if the ISA level is wrong.
(md_parse_option): Recognize -mcpu=[v][r]5000.
* config/tc-mips.c (load_register): Remove unnecessary code that
was causing the high 32bits of 64bit constants to be lost.
Fixes PR10503. The compiler was producing the assembler code:
dli $3,0xfffffffffffff
when constructing the softfloat library. Unfortunately it was being
incorrectly assembled.
routines to fetch/store the updated instruction from/to memory.
(v850_insert_operand): If the operand has a specialized insert
routine, call it.
Getting fixups closer. At least br <target> works now.
be like identical function found in tc-ppc.c.
(get_reloc): Removed.
(v850_reloc_prefix): New function, parse lo(), hi() and hi0().
(md_assemble): emit fixups.
(md_pcrel_from): renamed from md_pcrel_from_section, emit proper
displacement.
(md_apply_fix3): handle fixups/relocs.
* config/tc-v850.h (MD_PCREL_FROM_SECTION): Removed definition.
any given register table.
(register_name): Pass appropriate table and size to reg_name_search.
(system_register_name): New function.
(SYSREG_NAME_CNT): Define.
(md_assemble): Handle operands which are system registers.
Still working on the parser..
opcode doesn't want a register, then we don't have a match.
(md_assemble): Get size of the instruction from the opcode table.
So we choose the right opcode and so that we get the sizes right.
Add support for openVMS/Alpha.
* as.h (PRINTF_LIKE): Don't define if VMS, for now.
* config/obj-evax.c: New file.
* config/obj-evax.h: New file.
* config/tc-alpha.c: Add support for EVAX format if OBJ_EVAX is
defined.
* config/tc-alpha.h: Add support for EVAX format if OBJ_EVAX is
defined. Add case for bfd_target_evax_flavour.
* config/vms-a-conf.h: New file.
* conf-a-gas.com: New file.
* configure.in: Add target alpha-*-*vms*.
* configure: Rebuild.
* makefile.vms: New file.
* read.c (s_lcomm): Align bss_seg on 8 byte boundary if OBJ_EVAX.
Don't call ffs on openVMS/Alpha.
#ifndef OBJ_ELF lines. From Eric Valette <valette@crf.canon.fr>.
(tc_gen_reloc): If out of memory call as_fatal rather than
assert. If no howto found, call as_bad_where rather than
as_fatal. Change the error message slightly. Set howto to a
non-NULL value in order to keep going.
* config/tc-arm.c: Changed INSN_SIZE to variable insn_size, as
pre-cursor to adding Thumb support. Also added cpu_variant flag
information to each of the asm_flg structures.
(md_parse_option): Updated ARM7 parsing to allow 't' for
thumb/halfword support, aswell as 'm' for long multiply.
(md_show_usage): Updated help message.
(md_assemble): Check that instruction flags are applicated to the
current cpu variant.
(md_apply_fix3, tc_gen_reloc): Add BFD_RELOC_ARM_OFFSET_IMM8 and
BFD_RELOC_ARM_HWLITERAL relocation support for new halfword and
signextension instructions.
(do_ldst): Generate halfword and signextension variants if
mnemonic flags match.
(ldst_extend): Do not allow shifts in the offset field of halfword
or signextension instructions.
(validate_offset_imm): Provide check on halfword and signextension
immediate range.
(add_to_lit_pool): Merge identical literal pool values.
Wed Jul 31 15:55:12 1996 James G. Smith <jsmith@cygnus.co.uk>
* gas/arm/arm7t.s: Added.
* gas/arm/arm7t.d: Added.
* gas/arm/arm.exp: Updated to run the new test.
(cons_fix_new_hppa): Don't coke on e_esel.
(tc_gen_reloc, SOM version): Handle R_COMP2 when used
to help generate exception handling tables.
(md_apply_fix): Don't try to apply fixups with an e_esel
selector.
(hppa_fix_adjustable): Fixups with e_esel selectors
are not adjustable.
Another stab at EH on the PA.
* tc-d10v.c: Fix packaging bug. Added range checking.
Added kludge for divs instruction. Fixed minor problem with
multiple text sections.
* tc-d10v.h (d10v_cleanup): Change prototype.
Tue Jul 23 10:49:36 1996 Martin M. Hunt <hunt@pizza.cygnus.com>
* config/tc-d10v.c (md_apply_fix3): Fix all instruction
addresses to be right-shifted by 2.
end-sanitize-d10v
Mon Jul 22 11:32:36 1996 Martin M. Hunt <hunt@pizza.cygnus.com>
* config/tc-d10v.c: Many changes to get relocs working.
(register_name): No longer creates a symbol for register names.
(pre_defined_registers): moved to opcodes/d10v-opc.c.
(d10v_insert_operand): Now works correctly for either container.
* config/tc-d10v.h (d10v_cleanup): Declare.
end-sanitize-d10v
* tc-alpha.c: Patches to track current minimum alignment to reduce
the number of fragments created with frag_align.
(alpha_current_align): New static variable.
(s_alpha_text): Reset alignment to 0.
(s_alpha_data, s_alpha_rdata, s_alpha_sdata): Likewise.
(s_alpha_stringer, s_alpha_space): New functions.
(s_alpha_cons, alpha_flush_pending_output): Remove functions.
(alpha_cons_align): New function to replace both of them.
(emit_insn): Only align if alpha_current_align is less than 2;
reset alpha_current_align to 2.
(s_alpha_gprel32): Likewise.
(s_alpha_section): New function. Basically duplicate the other
alpha section change hooks. Only define for ELF.
(s_alpha_float_cons): Simplify alignment handling.
(md_pseudo_table): Only define "rdata" and "sdata" if OBJ_ECOFF.
If OBJ_ELF, define "section", "section.s", "sect", and "sect.s".
Don't define the s_alpha_cons pseudo-ops. Do define
s_alpha_stringer and s_alpha_space pseudo-ops.
(alpha_align): Skip if less than current default alignment. Set
default alignment.
* tc-alpha.h (md_flush_pending_output): Remove.
(md_cons_align): Add.
* tc-alpha.c: Add oodles of function description comments.
(md_bignum_to_chars): Remove; there are no callers.
(md_show_usage): Mention some more variants.
uaxword to use s_uacons.
(sparc_no_align_cons): New static variable.
(s_uacons): New static function.
(sparc_cons_align): If sparc_no_align_cons is set, just clear it
and return.
Wed Jul 17 14:25:13 1996 Martin M. Hunt <hunt@pizza.cygnus.com>
* config/tc-d10v.c: New file.
* config/tc-d10v.h: New file.
* configure (d10v-*-elf): New target.
* configure.in (d10v-*-elf): New target.
end-sanitize-d10v
* config/tc-alpha.c (alpha_align): Change fill parameter
to a pointer. Take NULL as 0 or nop depending on section. Change
all callers.
(s_alpha_align): Rename local variables.
* doc/as.texinfo (.align): Document action of omitted
fill parameter.
if fx_pcrel is set. Correct setting the addend case in the
OBJ_ELF case (from Andreas Schwab
<schwab@issan.informatik.uni-dortmund.de>).
(md_show_usage): Correct -mfc5200 to -m5200.
* config/tc-mips.c: Added cop_interlocks, to avoid NOP insertion
between co-processor comparisons and branches for the VR4300.
The preliminary documentation was slightly unclear on this issue, but
NEC have confirmed that there is an interlock within the CPU.
* configure.in: Add alpha-*-linuxecoff* target. Use elf for
alpha-*-linux* target. Force bfd_gas for alpha-*. Require
opcodes library for alpha.
* configure: Rebuild with autoconf 2.10.
* config/tc-alpha.c: Substantial rewrite to add ELF support and
use new opcode table.
* config/tc-alpha.h (md_undefined_symbol): Don't define.
(LOCAL_LABEL): Define differently if OBJ_ELF.
(FAKE_LABEL_NAME): Define if OBJ_ELF.
* config/alpha-opcode.h: Remove.
* config/obj-elf.h: If TC_ALPHA, define ECOFF_DEBUGGING.
* Makefile.in (TARG_CPU_DEP_alpha): Depend upon
include/opcode/alpha.h rather than config/alpha-opcode.h.
* config/tc-i386.h (md_number_to_chars): New macro.
* config/tc-alpha.c (build_operate_n, build_mem): Moved earlier in the file.
(load_symbol_address, load_expression): Use build_mem.
(build_operate): New function.
(emit_addq_r): Use it.
Wed Mar 13 22:14:14 1996 Pat Rankin <rankin@eql.caltech.edu>
* symbols.c (colon): #if VMS, use S_SET_OTHER to store `const_flag'.
Tue Mar 5 14:31:45 1996 Pat Rankin <rankin@eql.caltech.edu>
* config/tc-vax.h (NOP_OPCODE): Define.
Sun Feb 4 21:01:03 1996 Pat Rankin <rankin@eql.caltech.edu>
* config/obj-vms.h (S_IS_COMMON): Define.
(S_IS_LOCAL): Check for \002 as well as \001.
(LONGWORD_ALIGNMENT): New macro.
(SUB_SEGMENT_ALIGN): Use it.
Fri Jan 26 17:44:09 1996 Pat Rankin <rankin@eql.caltech.edu>
* config/vms-conf.h: Reconcile with conf.in.
(build_bytes): Likewise.
(skip_colonthing): Handle :32 suffix.
(get_specific): Promote L_24 to L_32 if it makes a match.
Don't always promote L_8 to L_16.
(do_a_fix_imm): Clean up L_32 and L_24 handling.
H8/S related stuff that doesn't need to be sanitized.
start-sanitize-h8s
* config/tc-h8300.c (Smode): New variable.
(h8300hmode): Turn off Hmode.
(h8300smode): New function. Turn on Smode and Hmode.
(md_pseudo_table): New ".h8300s" pseudo-op.
(parse_reg): Handle "exr" register.
(get_operand): Handle bizarre syntax for "stm.l" and "ldm.l".
Handle "mach" and "machl" operands for ldmac.
(get_specific): Handle "stm.l" and "ldm.l".
(build_bytes): Handle "stm.l" and "ldm.l"; handle MACREG operands.
* config/tc-h8300.h (COFF_MAGIC): Handle H8/S magic number.
(Smode): Declare.
end-sanitize-h8s
Sanitized H8/S stuff until we know its status.
BFD_ASSEMBLER.
(filename_list_head, filename_list_tail): Likewise.
(c_section_symbol): Remove unused BFD_ASSEMBLER version.
(obj_coff_endef, BFD_ASSEMBLER version): Don't set the debugging
flag for C_MOS, C_MOE, C_MOU, or C_EOS symbols, since they should
have a section of N_ABS rather than N_DEBUG. If we do a merge,
remove the new symbol from the list.
(obj_coff_endef, both versions): Call tag_insert even if there is
an old symbol with the same name, if the old symbol does not
happen to be a tag.
(coff_frob_symbol): Check SF_GET_TAG, C_EOF, and C_FILE outside of
the SF_GET_DEBUG condition. Don't call SA_SET_SYM_ENDNDX with a
symbol that will be moved to the end of the symbol list.
(coff_adjust_section_syms): Always call section_symbol for .text,
.data, and .bss.
(coff_frob_section): Likewise. Also, remove unused variable
strname.
