Tests that bfd_perform_reloc doesn't freak over a NONE reloc at end
of section.
gas/
* read.c (s_reloc): Match BFD_RELOC_NONE, BFD_RELOC{8,16,32,64}.
* write.c (get_frag_for_reloc): Allow match just past end of frag.
gas/testsuite/
* gas/all/none.s,
* gas/all/none.d: New test.
* gas/all/gas.exp: Run it.
- 32 128 bit vector registers (overlapping with the existing 16 64 bit
floating point registers)
- vector double instructions
- vector integer instructions
- scalar vector instructions (allowing to have more floating point
registers for scalar operations)
- vector string instructions
gas/ChangeLog:
* config/tc-s390.c (struct pd_reg): Remove.
(pre_defined_registers): Remove.
(REG_NAME_CNT): Remove.
(reg_name_search): Calculate the register number instead of doing
a lookup.
(register_name, tc_s390_regname_to_dw2regnum): Adopt to the new
reg_name_search signature.
(s390_parse_cpu): Support the new arch string z13.
(s390_insert_operand): Support for vector registers with the extra
field for the fifth bit of each vector register operand.
(md_gather_operand): Adjust to the new handling of optional
parameters.
* doc/as.texinfo: Document the z13 cpu string.
gas/testsuite/ChangeLog:
* gas/s390/esa-g5.d: Add a variant without the optional operand.
* gas/s390/esa-g5.s: Likewise.
* gas/s390/esa-z9-109.d: Likewise.
* gas/s390/esa-z9-109.s: Likewise.
* gas/s390/zarch-z9-109.d: Likewise.
* gas/s390/zarch-z9-109.s: Likewise.
* gas/s390/zarch-z10.d: For variants with a zero optional argument
it is not dumped by objdump anymore.
* gas/s390/zarch-zEC12.d: Likewise.
* gas/s390/zarch-z13.d: New file.
* gas/s390/zarch-z13.s: New file.
* gas/s390/s390.exp: Run the test for the z13 files.
include/opcode/ChangeLog:
* s390.h (s390_opcode_cpu_val): Add S390_OPCODE_Z13.
ld/testsuite/ChangeLog:
* ld-s390/tlsbin.dd: The nopr register operand is optional and not
printed if 0 anymore.
opcodes/ChangeLog:
* s390-dis.c (s390_extract_operand): Support vector register
operands.
(s390_print_insn_with_opcode): Support new operands types and add
new handling of optional operands.
* s390-mkopc.c (s390_opcode_mode_val, s390_opcode_cpu_val): Remove
and include opcode/s390.h instead.
(struct op_struct): New field `flags'.
(insertOpcode, insertExpandedMnemonic): New parameter `flags'.
(dumpTable): Dump flags.
(main): Parse flags from the s390-opc.txt file. Add z13 as cpu
string.
* s390-opc.c: Add new operands types, instruction formats, and
instruction masks.
(s390_opformats): Add new formats for .insn.
* s390-opc.txt: Add new instructions.
When runtime patching code (like e.g. done by the Linux kernel) there
may be cases where the set of stack frame alterations differs between
unpatched and patched code. Consequently the corresponding unwind data
needs patching too. Locating the right places within an FDE, however,
is rather cumbersome without a way to insert labels in the resulting
section. Hence this patch introduces a new directive, .cfi_label. Note
that with the way CFI data gets emitted currently (at the end of the
assembly process) this can't support local FB- and dollar-labels.
gas/
2015-01-12 Jan Beulich <jbeulich@suse.com>
* gas/dw2gencfi.c (cfi_add_label, dot_cfi_label): New.
(cfi_pseudo_table): Add "cfi_label".
(output_cfi_insn): Handle CFI_label.
(select_cie_for_fde): Als terminate CIE when encountering
CFI_label.
* dw2gencfi.h (cfi_add_label): Declare.
(struct cfi_insn_data): New member "sym_name".
(CFI_label): New.
* read.c (read_symbol_name): Drop "static".
* read.h (read_symbol_name): Declare.
gas/testsuite/
2015-01-12 Jan Beulich <jbeulich@suse.com>
gas/cfi/cfi-label.d, gas/cfi/cfi-label.s: New.
gas/cfi/cfi.exp: Run new tests.
These two, other than VQSHLU, didn't have their immediates properly range
checked so far.
(Re-sending unchanged from the original v2 due to never having got an
answer to https://sourceware.org/ml/binutils/2013-04/msg00121.html.)
gas/
2015-01-12 Jan Beulich <jbeulich@suse.com>
* gas/config/tc-arm.c (do_neon_shl_imm): Check immediate range.
(do_neon_qshl_imm): Likewise.
gas/testsuite/
2015-01-12 Jan Beulich <jbeulich@suse.com>
* gas/arm/neon-addressing-bad.s: Add test for invalid VSHL,
VQSHL, and VQSHLU immediates.
* gas/arm/neon-addressing-bad.l: Update accordingly.
When fixups are converted to a difference type within md_apply_fix, we
previously left the contents of VALP (the value that was initially
computed within write.c:fixup_segment) unchanged. This is harmless,
except that this value is used within write.c:fixup_segment once we
return from md_apply_fix to perform an overflow check.
In some cases, the value computed in write.c:fixup_segment is so wrong
that an overflow error can be triggered. These errors are incorrect.
This patch avoids the overflow errors by adjusting the value in
write.c:fixup_segment using the VALP pointer in md_apply_fix.
A test for this issue is included.
gas/ChangeLog:
* config/tc-avr.c (md_apply_fix): Update the contents of VALP for
diff fixups.
gas/testsuite/ChangeLog:
* gas/avr/large-debug-line-table.d: New file.
* gas/avr/large-debug-line-table.s: New file.
Have the assembler prepare for linker relaxation by default. This
means that users will be able to make use of linker relaxation without
having to adjust the assembler flags, this can make life easier when
compiling libraries.
Having this on by default in the assembler should make no difference to
the assembler code produced, however, some of the debug information will
be slightly less compressed.
A few tests needed to be updated as a result of this change as they
relied on linker relaxation support being off by default.
I've tightened up the definition of which sections can be relaxed on AVR
as part of this commit, the assembler used to think that all
non-debugging sections could be relaxed, when in reality only code
sections can be relaxed for AVR. The previous definition was not
dangerous, just over cautious. The new tighter definition allows an
extra test (gas/testsuite/gas/all/forward.d) to continue to pass.
gas/ChangeLog:
* config/tc-avr.c (struct avr_opt_s): Change link_relax to
no_link_relax, extend comment.
(enum options): Add new OPTION_NO_LINK_RELAX.
(md_longopts): Add entry for -mno-link-relax.
(md_parse_option): Handle OPTION_NO_LINK_RELAX, and update
OPTION_LINK_RELAX.
(md_begin): Initialise linkrelax from no_link_relax.
(md_show_usage): Include -mno-link-relax option.
(relaxable_section): Only allocatable code sections can be
relaxed.
* config/tc-avr.h (TC_LINKRELAX_FIXUP): Define.
gas/testsuite/ChangeLog:
* gas/all/gas.exp: Test will not pass on AVR due to linker
relaxation support.
* gas/avr/noreloc_withoutrelax.d: Add -mno-link-relax option.
* gas/avr/link-relax-elf-flag-clear.d: Likewise.
ld/testsuite/ChangeLog:
* ld/testsuite/ld-avr/relax-elf-flags-02.d: Add -mno-link-relax
option.
* ld/testsuite/ld-avr/relax-elf-flags-03.d: Likewise.
* ld/testsuite/ld-avr/relax-elf-flags-04.d: Likewise.
* ld/testsuite/ld-avr/relax-elf-flags-05.d: Likewise.
* ld/testsuite/ld-avr/relax-elf-flags-06.d: Likewise.
The AVR target uses a bit in the elf header flags to indicate if the
object was assembled ready for linker relaxation. Previously this flag
was always set, even when the object was not assembled ready for linker
relaxation.
This patch moves setting of the flag into the assembler, and sets it
only when the assembler is preparing the file for linker relaxation.
bfd/ChangeLog:
* elf32-avr.c (bfd_elf_avr_final_write_processing): Don't set
EF_AVR_LINKRELAX_PREPARED unconditionally.
gas/ChangeLog:
* config/tc-avr.c: Add include for elf/avr.h.
(avr_elf_final_processing): New function.
* config/tc-avr.h (elf_tc_final_processing): Define.
(avr_elf_final_processing): Declare
gas/testsuite/ChangeLog:
* gas/avr/link-relax-elf-flag-clear.d: New file.
* gas/avr/link-relax-elf-flag-set.d: New file.
* gas/avr/link-relax-elf-flag.s: New file.
gas/
* config/tc-mips.c (md_apply_fix): Apply alignment check
to the symbol and offset rather than *valP for
BFD_RELOC_MIPS_18_PCREL_S3. Also update the error message
for BFD_RELOC_MIPS_19_PCREL_S2.
gas/testsuite/
* gas/mips/r6-64.s: Remove .align directives from LDPC
instructions and add further tests for LDPC.
* gas/mips/r6-64-n32.d: remove the NOPs from LDPC expected
output and update for new tests.
* gas/mips/r6-64-n64.d: Likewise.
* gas/mips/ldpc-unalign.l: New file.
* gas/mips/ldpc-unalign.s: Likewise.
* gas/mips/mips.exp: Run ldpc-unalign test.
opcodes/
* mips-opc.c (mips_builtin_opcodes): Add JALRC alias for JIALC.
Remove the operand from NAL.
gas/testsuite/
* gas/mips/r6.s: Test JALRC and NAL
* gas/mips/r6-n32.d: Add expected output for JALRC and NAL.
* gas/mips/r6-n64.d: Likewise.
* gas/mips/r6.d: Likewise.
On further reading of ISA manual it appears gas should have been
treating mftb and mftbu as extended mnemonics for mfspr, for ISA 2.03
and later.
opcodes/
* ppc-opc.c (powerpc_opcodes): Make mftb* generate mfspr for
power4 and later.
gas/testsuite/
* gas/ppc/a2.d: Update for mftb change.
* gas/ppc/476.d: Likewise.
For conditional branches that need more than one trampoline to reach its
target assembler couldn't always find suitable trampoline because
post-loop condition check was placed inside the loop, resulting in
premature loop termination. Move check outside the loop.
This fixes the following build errors seen when assembling huge files
produced by gcc:
Error: jump target out of range; no usable trampoline found
Error: operand 1 of 'j' has out of range value '307307'
2014-11-25 Max Filippov <jcmvbkbc@gmail.com>
gas/
* config/tc-xtensa.c (search_trampolines): Move post-loop
condition check outside the search loop.
gas/testsuite/
* gas/xtensa/trampoline.d: Add expected output for branches.
* gas/xtensa/trampoline.s: Add test case for branches.
gas/
2014-11-21 Terry Guo <terry.guo@arm.com>
* config/tc-arm.c (md_assemble): Do not consider relaxation.
(md_convert_frag): Test and set target arch attribute accordingly.
(aeabi_set_attribute_string): Turn it into a global function.
* config/tc-arm.h (md_post_relax_hook): Enable it for ARM target.
(aeabi_set_public_attributes): Declare it.
gas/testsuite/
2014-11-21 Terry Guo <terry.guo@arm.com>
* gas/arm/attr-arch-assumption.d: New file.
* gas/arm/attr-arch-assumption.s: Likewise.
ld/testsuite/
2014-11-21 Terry Guo <terry.guo@arm.com>
* ld-arm/tls-longplt-lib.s: Require ARMv6T2.
* ld-arm/tls-longplt.s: Likewise.
* ld-arm/tls-longplt-lib.d: Updated.
* ld-arm/tls-longplt.d: Likewise.
* config/tc-aarch64.c (warn_unpredictable_ldst): Check that transfer
registers are in the GP register set. Adjust warnings. Use correct
field member for address register.
* testsuite/gas/aarch64/diagnostic.l: Update.
Structions with R_X86_64_GOTTPOFF relocation must be encoded with REX
prefix even if it isn't required by destination register. Otherwise
linker can't safely perform IE -> LE optimization.
bfd/
PR ld/17482
* elf64-x86-64.c (elf_x86_64_relocate_section): Update comments
for IE->LE transition.
gas/
PR ld/17482
* config/tc-i386.c (output_insn): Add a dummy REX_OPCODE prefix
for structions with R_X86_64_GOTTPOFF relocation for x32 if needed.
gas/testsuite/
PR ld/17482
* gas/i386/ilp32/x32-tls.d: New file.
* gas/i386/ilp32/x32-tls.s: Likewise.
ld/testsuite/
PR ld/17482
* ld-x86-64/tlsie4.dd: Updated.
bfd/
* elfxx-mips.c (update_mips_abiflags_isa): Add E_MIPS_ARCH_32R6
and E_MIPS_ARCH_64R6 support.
ld/testsuite/
* ld-mips-elf/abiflags-strip10-ph.d: New file.
* ld-mips-elf/mips-eld.exp: Run the new test.
gas/
* config/tc-mips.c (mips_elf_final_processing): Add INSN_ISA32R6
and INSN_ISA64R6 support.
gas/testsuite/
* gas/mips/elf_arch_mips32r6.d: New file.
* gas/mips/elf_arch_mips64r6.d: New file.
* gas/mips/mips.exp: Run the new tests.
binutils:
2014-10-31 Andrew Pinski <apinski@cavium.com>
Naveen H.S <Naveen.Hurugalawadi@caviumnetworks.com>
* readelf.c (print_mips_isa_ext): Print the value of Octeon3.
gas:
2014-10-31 Andrew Pinski <apinski@cavium.com>
Naveen H.S <Naveen.Hurugalawadi@caviumnetworks.com>
* config/tc-mips.c (CPU_IS_OCTEON): Handle CPU_OCTEON3.
(mips_cpu_info_table): Octeon3 enables virt ase.
* doc/c-mips.texi: Document octeon3 as an acceptable value for
-march=.
gas/testsuite:
2014-10-31 Andrew Pinski <apinski@cavium.com>
Naveen H.S <Naveen.Hurugalawadi@caviumnetworks.com>
* gas/mips/mips.exp: Add support for Octeon3 architecture.
Also add in support for running Octeon3 tests.
* gas/mips/octeon3.d: New test.
* gas/mips/octeon3.s: New test source.
opcodes:
2014-10-31 Andrew Pinski <apinski@cavium.com>
Naveen H.S <Naveen.Hurugalawadi@caviumnetworks.com>
* mips-dis.c (mips_arch_choices): Add octeon3.
* mips-opc.c (IOCT): Include INSN_OCTEON3.
(IOCT2): Likewise.
(IOCT3): New define.
(IVIRT): New define.
(mips_builtin_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
tlbinv, tlbinvf, tlbgr, tlbgwi, tlbginv, tlbginvf, tlbgwr, tlbgp, tlti
IVIRT instructions.
Extend mtm0, mtm1, mtm2, mtp0, mtp1, mtp2 instructions to take another
operand for IOCT3.
bfd:
2014-10-31 Andrew Pinski <apinski@cavium.com>
Naveen H.S <Naveen.Hurugalawadi@caviumnetworks.com>
* archures.c: Add octeon3 for mips target.
* bfd-in2.h: Regenerate.
* bfd/cpu-mips.c: Define I_mipsocteon3.
nfo_struct): Add octeon3 support.
* bfd/elfxx-mips.c: (_bfd_elf_mips_mach): Add support for
octeon3.
(mips_set_isa_flags): Add support for octeon3.
(bfd_mips_isa_ext): Add bfd_mach_mips_octeon3.
(mips_mach_extensions): Make bfd_mach_mips_octeon3 an
extension of bfd_mach_mips_octeon2.
(print_mips_isa_ext): Print the value of Octeon3.
This makes sure `HAVE_CODE_COMPRESSION' evaluates correctly when the
`.insn' directive is used at the beginning of a source file before any
instructions have been produced and that ELF file header's MIPS16 and
microMIPS ASE flags are set correctly in the case where no instructions
have been produced other than with the said directive.
gas/
* config/tc-mips.c (s_insn): Set file options.
gas/testsuite/
* gas/mips/insn-opts.d: New test.
* gas/mips/insn-opts.s: New test source.
* gas/mips/mips.exp: Run the new test.
The construct being added to the cond.s test case otherwise triggered
both the "missing closing ..." and the "stray ..." (twice) warnings in
_find_end_of_line(). As that code fragments suggests, this is needed to
support (include) files that can be used for both assembler .include
and compiler #include directives.
The write.c change is to make gas report an error if reg_section
symbols should leak in future. The tc-i386.c change is the real fix.
Note that the error isn't the most helpful, "redefined symbol cannot
be used on reloc", but I'm not inclined to improve what is really an
internal gas error. reg_section symbols shouldn't leak..
gas/
PR 17493
* write.c (adjust_reloc_syms): Don't allow symbols in reg_section
to be reduced to reg_section section symbol.
* gas/config/tc-i386.c (i386_finalize_immediate): Reject all
reg_section immediates.
gas/testsuite/
* gas/i386/inval-equ-2.l: Adjust.
Hash lookup is silly when we can attach the line table info directly
to sections instead. Worse, hash lookup fails when we have multiple
sections with the same name.
gas/
* dwarf2dbg.c (all_segs_hash): Delete.
(get_line_subseg): Delete last_seg, last_subseg, last_line_subseg.
Retrieve line_seg for section via seg_info.
* subsegs.h (segment_info_typet): Add dwarf2_line_seg.
gas/testsuite/
* gas/elf/group2.d, * gas/elf/group2.s: New test.
* gas/elf/elf.exp: Run it.
bfd/
* aoutx.h (NAME (aout, machine_type)): Add mips32r6 and mips64r6.
* archures.c (bfd_architecture): Likewise.
* bfd-in2.h (bfd_architecture): Likewise.
(bfd_reloc_code_real): Add relocs BFD_RELOC_MIPS_21_PCREL_S2,
BFD_RELOC_MIPS_26_PCREL_S2, BFD_RELOC_MIPS_18_PCREL_S3 and
BFD_RELOC_MIPS_19_PCREL_S2.
* cpu-mips.c (arch_info_struct): Add mips32r6 and mips64r6.
* elf32-mips.c: Define relocs R_MIPS_PC21_S2, R_MIPS_PC26_S2
R_MIPS_PC18_S3, R_MIPS_PC19_S2, R_MIPS_PCHI16 and R_MIPS_PCLO16.
(mips_reloc_map): Add entries for BFD_RELOC_MIPS_21_PCREL_S2,
BFD_RELOC_MIPS_26_PCREL_S2, BFD_RELOC_MIPS_18_PCREL_S3,
BFD_RELOC_MIPS_19_PCREL_S2, BFD_RELOC_HI16_S_PCREL and
BFD_RELOC_LO16_PCREL.
* elf64-mips.c: Define REL, and RELA relocations R_MIPS_PC21_S2,
R_MIPS_PC26_S2, R_MIPS_PC18_S3, R_MIPS_PC19_S2, R_MIPS_PCHI16
and R_MIPS_PCLO16.
(mips_reloc_map): Add entries for BFD_RELOC_MIPS_21_PCREL_S2,
BFD_RELOC_MIPS_26_PCREL_S2, BFD_RELOC_MIPS_18_PCREL_S3,
BFD_RELOC_MIPS_19_PCREL_S2, BFD_RELOC_HI16_S_PCREL and
BFD_RELOC_LO16_PCREL.
* elfn32-mips.c: Likewise.
* elfxx-mips.c (MIPSR6_P): New define.
(mipsr6_exec_plt_entry): New array.
(hi16_reloc_p): Add support for R_MIPS_PCHI16.
(lo16_reloc_p): Add support for R_MIPS_PCLO16.
(aligned_pcrel_reloc_p): New function.
(mips_elf_relocation_needs_la25_stub): Add support for relocs:
R_MIPS_PC21_S2 and R_MIPS_PC26_S2.
(mips_elf_calculate_relocation): Add support for relocs:
R_MIPS_PC21_S2, R_MIPS_PC26_S2, R_MIPS_PC18_S3, R_MIPS_PC19_S2,
R_MIPS_PCHI16 and R_MIPS_PCLO16.
(_bfd_elf_mips_mach): Add support for mips32r6 and mips64r6.
(mips_elf_add_lo16_rel_addend): Add support for R_MIPS_PCHI16.
(_bfd_mips_elf_check_relocs): Add support for relocs:
R_MIPS_PC21_S2 and R_MIPS_PC26_S2.
(_bfd_mips_elf_relocate_section): Add a check for unaligned
pc relative relocs.
(_bfd_mips_elf_finish_dynamic_symbol): Add support for MIPS r6
plt entry.
(mips_set_isa_flags): Add support for mips32r6 and mips64r6.
(_bfd_mips_elf_print_private_bfd_data): Likewise.
(mips_32bit_flags_p): Add support for mips32r6.
* libbfd.h (bfd_reloc_code_real_names): Add entries for
BFD_RELOC_MIPS_21_PCREL_S2, BFD_RELOC_MIPS_26_PCREL_S2,
BFD_RELOC_MIPS_18_PCREL_S3 and BFD_RELOC_MIPS_19_PCREL_S2.
* reloc.c: Document relocs BFD_RELOC_MIPS_21_PCREL_S2,
BFD_RELOC_MIPS_26_PCREL_S2, BFD_RELOC_MIPS_18_PCREL_S3 and
BFD_RELOC_MIPS_19_PCREL_S2.
binutils/
* readelf.c (get_machine_flags): Add support for mips32r6 and
mips64r6.
elfcpp/
* mips.h (E_MIPS_ARCH_32R6, E_MIPS_ARCH_64R6): New enum constants.
gas/
* config/tc-mips.c (mips_nan2008): New static global.
(mips_flag_nan2008): Removed.
(LL_SC_FMT): New define.
(COP12_FMT): Updated.
(ISA_IS_R6): New define.
(ISA_HAS_64BIT_REGS): Add mips64r6.
(ISA_HAS_DROR): Likewise.
(ISA_HAS_64BIT_FPRS): Add mips32r6 and mips64r6.
(ISA_HAS_ROR): Likewise.
(ISA_HAS_ODD_SINGLE_FPR): Likewise.
(ISA_HAS_MXHC1): Likewise.
(hilo_interlocks): Likewise.
(md_longopts): Likewise.
(ISA_HAS_LEGACY_NAN): New define.
(options): Add OPTION_MIPS32R6 and OPTION_MIPS64R6.
(mips_ase): Add field rem_rev.
(mips_ases): Updated to add which ISA an ASE was removed in.
(mips_isa_rev): Add support for mips32r6 and mips64r6.
(mips_check_isa_supports_ase): Add support to check if an ASE
has been removed in the specified MIPS ISA revision.
(validate_mips_insn): Skip '-' character.
(macro_build): Likewise.
(mips_check_options): Prevent R6 working with fp32, mips16,
micromips, or branch relaxation.
(file_mips_check_options): Set R6 floating point registers to
64 bit. Also deal with the nan2008 option.
(limited_pcrel_reloc_p): Add relocs: BFD_RELOC_MIPS_21_PCREL_S2,
BFD_RELOC_MIPS_26_PCREL_S2, BFD_RELOC_MIPS_18_PCREL_S3,
BFD_RELOC_MIPS_19_PCREL_S2, BFD_RELOC_HI16_S_PCREL and
BFD_RELOC_LO16_PCREL.
(operand_reg_mask): Add support for OP_SAME_RS_RT, OP_CHECK_PREV
and OP_NON_ZERO_REG.
(match_check_prev_operand): New static function.
(match_same_rs_rt_operand): New static function.
(match_non_zero_reg_operand): New static function.
(match_operand): Added entries for: OP_SAME_RS_RT, OP_CHECK_PREV
and OP_NON_ZERO_REG.
(insns_between): Added case to deal with forbidden slots.
(append_insn): Added support for relocs: BFD_RELOC_MIPS_21_PCREL_S2
and BFD_RELOC_MIPS_26_PCREL_S2.
(match_insn): Add support for operands -A, -B, +' and +". Also
skip '-' character.
(mips_percent_op): Add entries for %pcrel_hi and %pcrel_lo.
(md_parse_option): Add support for mips32r6 and mips64r6. Also
update the nan option handling.
(md_pcrel_from): Add cases for relocs: BFD_RELOC_MIPS_21_PCREL_S2,
BFD_RELOC_MIPS_26_PCREL_S2.
(mips_force_relocation): Prevent forced relaxation for MIPS r6.
(md_apply_fix): Add support for relocs: BFD_RELOC_MIPS_21_PCREL_S2,
BFD_RELOC_MIPS_26_PCREL_S2, BFD_RELOC_MIPS_18_PCREL_S3,
BFD_RELOC_MIPS_19_PCREL_S2, BFD_RELOC_HI16_S_PCREL and
BFD_RELOC_LO16_PCREL.
(s_mipsset): Add support for mips32r6 and mips64r6.
(s_nan): Update to support the new nan2008 framework.
(tc_gen_reloc): Add relocs: BFD_RELOC_MIPS_21_PCREL_S2,
BFD_RELOC_MIPS_26_PCREL_S2, BFD_RELOC_MIPS_18_PCREL_S3,
BFD_RELOC_MIPS_19_PCREL_S2, BFD_RELOC_HI16_S_PCREL and
BFD_RELOC_LO16_PCREL.
(mips_elf_final_processing): Updated to use the mips_nan2008.
(mips_cpu_info_table): Add entries for mips32r6 and mips64r6.
(macro): Enable ldc2, sdc2, ll, lld, swc2, sc, scd, cache, pref
macros for R6.
(mips_fix_adjustable): Make PC relative R6 relocations relative
to the symbol and not the section.
* configure.ac: Add support for mips32r6 and mips64r6.
* configure: Regenerate.
* doc/c-mips.texi: Document the -mips32r6 and -mips64r6 command line
options.
* doc/as.texinfo: Likewise.
gas/testsuite/
* gas/mips/24k-triple-stores-1.s: If testing for r6 prevent
non-supported instructions from being tested.
* gas/mips/24k-triple-stores-2.s: Likewise.
* gas/mips/24k-triple-stores-3.s: Likewise.
* gas/mips/24k-triple-stores-6.s: Likewise.
* gas/mips/beq.s: Likewise.
* gas/mips/eva.s: Likewise.
* gas/mips/ld-zero-3.s: Likewise.
* gas/mips/mips32-cp2.s: Likewise.
* gas/mips/mips32.s: Likewise.
* gas/mips/mips4.s: Likewise.
* gas/mips/add.s: Don't test the add instructions if r6, and
add padding.
* gas/mips/add.d: Check for a triple dot not a nop at the end of the
disassembly output.
* gas/mips/micromips@add.d: Likewise.
* gas/mips/mipsr6@24k-branch-delay-1.d: New file.
* gas/mips/mipsr6@24k-triple-stores-1.d: New file.
* gas/mips/mipsr6@24k-triple-stores-2-llsc.d: New file.
* gas/mips/mipsr6@24k-triple-stores-2.d: New file.
* gas/mips/mipsr6@24k-triple-stores-3.d: New file.
* gas/mips/mipsr6@24k-triple-stores-6.d: New file.
* gas/mips/mipsr6@add.d: New file.
* gas/mips/mipsr6@attr-gnu-4-1-msingle-float.l: New file.
* gas/mips/mipsr6@attr-gnu-4-1-msingle-float.s: New file.
* gas/mips/mipsr6@attr-gnu-4-1-msoft-float.l: New file.
* gas/mips/mipsr6@attr-gnu-4-1-msoft-float.s: New file.
* gas/mips/mipsr6@attr-gnu-4-2-mdouble-float.l: New file.
* gas/mips/mipsr6@attr-gnu-4-2-mdouble-float.s: New file.
* gas/mips/mipsr6@beq.d: New file.
* gas/mips/mipsr6@bge.d: New file.
* gas/mips/mipsr6@bgeu.d: New file.
* gas/mips/mipsr6@blt.d: New file.
* gas/mips/mipsr6@bltu.d: New file.
* gas/mips/mipsr6@branch-misc-1.d: New file.
* gas/mips/mipsr6@branch-misc-2-64.d: New file.
* gas/mips/mipsr6@branch-misc-2pic-64.d: New file.
* gas/mips/mipsr6@branch-misc-4-64.d: New file.
* gas/mips/mipsr6@cache.d: New file.
* gas/mips/mipsr6@eva.d: New file.
* gas/mips/mipsr6@jal-svr4pic-noreorder.d: New file.
* gas/mips/mipsr6@jal-svr4pic.d: New file.
* gas/mips/mipsr6@ld-zero-2.d: New file.
* gas/mips/mipsr6@ld-zero-3.d: New file.
* gas/mips/mipsr6@loc-swap-dis.d: New file.
* gas/mips/mipsr6@mips32-cp2.d: New file.
* gas/mips/mipsr6@mips32-imm.d: New file.
* gas/mips/mipsr6@mips32.d: New file.
* gas/mips/mipsr6@mips32r2.d: New file.
* gas/mips/mipsr6@mips4-fp.d: New file.
* gas/mips/mipsr6@mips4-fp.l: New file.
* gas/mips/mipsr6@mips4-fp.s: New file.
* gas/mips/mipsr6@mips4.d: New file.
* gas/mips/mipsr6@mips5-fp.d: New file.
* gas/mips/mipsr6@mips5-fp.l: New file.
* gas/mips/mipsr6@mips5-fp.s: New file.
* gas/mips/mipsr6@mips64.d: New file.
* gas/mips/mipsr6@msa-branch.d: New file.
* gas/mips/mipsr6@msa.d: New file.
* gas/mips/mipsr6@pref.d: New file.
* gas/mips/mipsr6@relax-swap3.d: New file.
* gas/mips/r6-64-n32.d: New file.
* gas/mips/r6-64-n64.d: New file.
* gas/mips/r6-64-removed.l: New file.
* gas/mips/r6-64-removed.s: New file.
* gas/mips/r6-64.s: New file.
* gas/mips/r6-attr-none-double.d: New file.
* gas/mips/r6-n32.d: New file.
* gas/mips/r6-n64.d: New file.
* gas/mips/r6-removed.l: New file.
* gas/mips/r6-removed.s: New file.
* gas/mips/r6.d: New file.
* gas/mips/r6.s: New file.
* gas/mips/mipsr6@mips32-dsp.d: New file.
* gas/mips/mipsr6@mips32-dspr2.d: New file.
* gas/mips/mipsr6@mips32r2-ill.l: New file.
* gas/mips/mipsr6@mips32r2-ill.s: New file.
* gas/mips/cache.s: Add r6 instruction varients.
* gas/mips/mips.exp: Add support for the mips32r6 and mips64r6
architectures. Also prevent non r6 supported tests from running.
Finally, add in support for running the new r6 tests.
(run_dump_test_arch): Add support for mipsr6 tests.
(run_list_test_arch): Add support for using files of the
form arch@testname.l .
include/elf/
* mips.h: Add relocs: R_MIPS_PC21_S2, R_MIPS_PC26_S2, R_MIPS_PC18_S3,
R_MIPS_PC19_S2, R_MIPS_PCHI16 and R_MIPS_PCLO16.
(E_MIPS_ARCH_32R6): New define.
(E_MIPS_ARCH_64R6): New define.
include/opcode/
* mips.h (mips_operand_type): Add new entries: OP_SAME_RS_RT,
OP_CHECK_PREV and OP_NON_ZERO_REG. Add descriptions for the MIPS R6
instruction arguments: -a, -b, -d, -s, -t, -u, -v, -w, -x, -y, -A, -B,
+I, +O, +R, +:, +\, +", +;
(mips_check_prev_operand): New struct.
(INSN2_FORBIDDEN_SLOT): New define.
(INSN_ISA32R6): New define.
(INSN_ISA64R6): New define.
(INSN_UPTO32R6): New define.
(INSN_UPTO64R6): New define.
(mips_isa_table): Add INSN_UPTO32R6 and INSN_UPTO64R6.
(ISA_MIPS32R6): New define.
(ISA_MIPS64R6): New define.
(CPU_MIPS32R6): New define.
(CPU_MIPS64R6): New define.
(cpu_is_member): Add cases for CPU_MIPS32R6, and CPU_MIPS64R6.
ld/
* ldmain.c (get_emulation): Add support for -mips32r6 and -mips64r6.
opcodes/
* mips-dis.c (mips_arch_choices): Add entries for mips32r6 and
mips64r6.
(parse_mips_dis_option): Allow MSA and virtualization support for
mips64r6.
(mips_print_arg_state): Add fields dest_regno and seen_dest.
(mips_seen_register): New function.
(print_insn_arg): Refactored code to use mips_seen_register
function. Add support for OP_SAME_RS_RT, OP_CHECK_PREV and
OP_NON_ZERO_REG. Changed OP_REPEAT_DEST_REG case to print out
the register rather than aborting.
(print_insn_args): Add length argument. Add code to correctly
calculate the instruction address for pc relative instructions.
(validate_insn_args): New static function.
(print_insn_mips): Prevent jalx disassembling for r6. Use
validate_insn_args.
(print_insn_micromips): Use validate_insn_args.
all the arguments are valid.
* mips-formats.h (PREV_CHECK): New define.
* mips-opc.c (decode_mips_operand): Add support for -a, -b, -d, -s,
-t, -u, -v, -w, -x, -y, -A, -B, +I, +O, +R, +:, +\, +", +;
(RD_pc): New define.
(FS): New define.
(I37): New define.
(I69): New define.
(mips_builtin_opcodes): Add MIPS R6 instructions. Exclude recoded
MIPS R6 instructions from MIPS R2 instructions.
