operands. Update opcode table as appropriate.
(IMM32): Add MN10300_OPERAND_SPLIT flag.
(mn10300_opcodes): Fix single bit error in mov imm32,dn insn.
Cleaning up a little.
Attempting to insert most 32bit operands.
And a bug found by assembler testsuite.
movbu, movhu instructions. Check bit patterns for more bit
operations. Check bit patterns for various 16bit call, retf
and ret instructions.
* gas/mn10300/other.s: Update operands for better test coverage.
Improving testsuite coverage.
the extension part of the instruction if necessary.
(mn10300_insert_operand): Accept pointer to extension word
argument. Make insn a pointer argument too. Return type
is now void. All callers changed.
So we can correct insert operands into any instruction except those
which have 32bit operands.
operands (for indexed load/stores). Fix bitpos for DI
operand. Add SN8N_SHIFT8, IMM8_SHIFT8, and D16_SHIFT for the
few instructions that insert immediates/displacements in the
middle of the instruction. Add IMM8E for 8 bit immediate in
the extended part of an instruction.
(mn10300_operands): Use new opcodes as appropriate.
Opcode table changes so we can correctly insert everything except
32bit operands.
a data/address register that appears in register field 0
and register field 1.
(mn10300_opcodes): Use DN01 and AN01 for mov/cmp imm8,DN/AN
Hacking Matsushita again. Yippie!
missing or zero-sized .text sections properly.
* mdebugread.c: Handle scRConst and scSUndefined storage classes.
* stabsread.c (scan_file_globals): Try to resolve symbols
for shared libraries from the minimal symbol table of the main
executable first.
alpha_macro emit field to expect a const argument, and change the
arg field to be const. Fix some spacing to follow the GNU
standard.
Fri Nov 1 10:32:03 1996 Richard Henderson <rth@tamu.edu>
* config/tc-alpha.c (md_parse_option): Add knowledge of 21164pc
(pca56) and 21264 (ev6) cpus.
(md_apply_fix): Private relocation types are now negative.
(alpha_force_relocation): Likewise.
(tc_gen_reloc): Likewise.
(emit_insn): Likewise.
(emit_ldXu): Do the right thing when the hardware can do byte insns.
(emit_stX): Likewise.
(emit_sextX): Likewise.
* alpha.h: Don't include "bfd.h"; private relocation types are now
negative to minimize problems with shared libraries. Organize
instruction subsets by AMASK extensions and PALcode
implementation.
(struct alpha_operand): Move flags slot for better packing.
* alpha-dis.c (print_insn_alpha): Use new NOPAL mask for
standard disassembly.
* alpha-opc.c (alpha_operands): Rearrange flags slot.
(alpha_opcodes): Add new BWX, CIX, and MAX instructions.
Recategorize PALcode instructions.
(parse_stab): Pass value to push_bincl. Call find_excl for
N_EXCL.
(struct bincl_file): Add hash, file and file_types fields.
(push_bincl): Add hash parameter. Save it in the new hash field.
Save the file number in the new file field.
(pop_bincl): Put the bincl_file on bincl_list, rather than freeing
it. Save the file types in the new file_types field.
(find_excl): New static function.
PR 10980.
* m32r-tdep.c: Improved frame_chain and fn prologue analysis.
* configure.tgt: Add entry for m32r target.
* monitor.h: Add a flag to tell monitor_store_register to use
(val, regno) instead of (regno, val).
* monitor.c: Make monitor_store_register honor the above flag.
Make monitor_exp ignore DC1/DC3 for m32r.
Increase buf size in monitor_dump_regs.
