opcode * rx.h (enum RX_Operand_Type): Add RX_Operand_Zero_Indirect.
opcodes * rx-decode.opc (rx_disp): If the displacement is zero, set the
type to RX_Operand_Zero_Indirect.
* rx-decode.c: Regenerate.
* rx-dis (print_insn): Handle RX_Operand_Zero_Indirect.
gas * config/rx-parse.y: Allow zero value for 5-bit displacements.
tests * gas/rx/mov.sm: Add tests for zero offset indirect moves.
* gas/rx/mov.d: Update expected output.
ld * Makefile.am (ALL_64_EMULATION_SOURCES): Add support for
CloudABI on aarch64. For this target we have to make sure we use
ELFOSABI_CLOUDABI instead of ELFOSABI_NONE.
* configure.tgt (targ_emul): Likewise.
* emulparams/aarch64cloudabi.sh: New file.
* emulparams/aarch64cloudabib.sh: New file.
* Makefile.in: Regenerate.
bfd * config.bfd (targ_defvec): Add support for CloudABI on aarch64.
For this target we have to make sure we use ELFOSABI_CLOUDABI
instead of ELFOSABI_NONE.
* configure.ac (tb): Likewise.
* elfnn-aarch64.c: Likewise.
* targets.c (_bfd_target_vector): Likewise.
* configure: Regenerate.
gas * config/tc-aarch64.c (elf64_aarch64_target_format): Select the
cloudabi format if the TARGET_OS is cloudabi.
This patch adds support for the R_X86_64_GOTPCRELX and
R_X86_64_REX_GOTPCRELX relocations proposed in
https://groups.google.com/forum/#!topic/x86-64-abi/n9AWHogmVY0
to gas and ld. It updates gas to generate R_X86_64_GOTPCRELX,
R_X86_64_REX_GOTPCRELX if there is a REX prefix, relocation for memory
operand, foo@GOTPCREL(%rip). With the locally defined symbol, foo, we
convert
mov foo@GOTPCREL(%rip), %reg
to
lea foo(%rip), %reg
and convert
call/jmp *foo@GOTPCREL(%rip)
to
nop call foo/jmp foo nop
When PIC is false, convert
test %reg, foo@GOTPCREL(%rip)
to
test $foo, %reg
and convert
binop foo@GOTPCREL(%rip), %reg
to
binop $foo, %reg
where binop is one of adc, add, and, cmp, or, sbb, sub, xor instructions.
bfd/
* elf64-x86-64.c: Include opcode/i386.h.
(x86_64_elf_howto_table): Add R_X86_64_GOTPCRELX and
R_X86_64_REX_GOTPCRELX.
(R_X86_64_standard): Replace R_X86_64_PLT32_BND with
R_X86_64_REX_GOTPCRELX.
(x86_64_reloc_map): Add BFD_RELOC_X86_64_GOTPCRELX and
BFD_RELOC_X86_64_REX_GOTPCRELX.
(need_convert_mov_to_lea): Renamed to ...
(need_convert_load): This.
(elf_x86_64_check_relocs): Handle R_X86_64_GOTPCRELX and
R_X86_64_REX_GOTPCRELX. Replace need_convert_mov_to_lea with
need_convert_load.
(elf_x86_64_gc_sweep_hook): Handle R_X86_64_GOTPCRELX and
R_X86_64_REX_GOTPCRELX.
(elf_x86_64_size_dynamic_sections): Likewise.
(elf_x86_64_relocate_section): Likewise.
(elf_x86_64_convert_mov_to_lea): Renamed to ...
(elf_x86_64_convert_load): This. Replace need_convert_mov_to_lea
with need_convert_load. Support R_X86_64_GOTPCRELX and
R_X86_64_REX_GOTPCRELX transformations.
* reloc.c (BFD_RELOC_X86_64_GOTPCRELX): New.
(BFD_RELOC_X86_64_REX_GOTPCRELX): Likewise.
* bfd-in2.h: Regenerated.
* libbfd.h: Likewise.
gas/
* config/tc-i386.c (tc_i386_fix_adjustable): Handle
BFD_RELOC_X86_64_GOTPCRELX and BFD_RELOC_X86_64_REX_GOTPCRELX.
(tc_gen_reloc): Likewise.
(i386_validate_fix): Generate BFD_RELOC_X86_64_GOTPCRELX or
BFD_RELOC_X86_64_REX_GOTPCRELX if fx_tcbit2 is set.
* config/tc-i386.h (TC_FORCE_RELOCATION_LOCAL): Also return
true for BFD_RELOC_X86_64_GOTPCRELX and
BFD_RELOC_X86_64_REX_GOTPCRELX.
gas/testsuite/
* gas/i386/i386.exp: Run x86-64-gotpcrel.
* gas/i386/x86-64-gotpcrel.d: New file.
* gas/i386/x86-64-gotpcrel.s: Likewise.
* gas/i386/ilp32/x86-64-gotpcrel.d: Likewise.
* gas/i386/x86-64-localpic.d: Replace R_X86_64_GOTPCREL with
R_X86_64_REX_GOTPCRELX.
* gas/i386/ilp32/x86-64-localpic.d: Likewise.
include/elf/
* x86-64.h (R_X86_64_GOTPCRELX): New.
(R_X86_64_REX_GOTPCRELX): Likewise.
ld/testsuite/
* ld-ifunc/ifunc-5r-local-x86-64.d: Replace R_X86_64_GOTPCREL
with R_X86_64_REX_GOTPCRELX.
* ld-x86-64/plt-main1.rd: Likewise.
* ld-x86-64/plt-main3.rd: Likewise.
* ld-x86-64/plt-main4.rd: Likewise.
* ld-x86-64/gotpcrel1.dd: New file.
* ld-x86-64/gotpcrel1.out: Likewise.
* ld-x86-64/gotpcrel1a.S: Likewise.
* ld-x86-64/gotpcrel1b.c: Likewise.
* ld-x86-64/gotpcrel1c.c: Likewise.
* ld-x86-64/gotpcrel1d.S: Likewise.
* ld-x86-64/load1.s: Likewise.
* ld-x86-64/load1a.d: Likewise.
* ld-x86-64/load1b.d: Likewise.
* ld-x86-64/load1c.d: Likewise.
* ld-x86-64/load1d.d: Likewise.
* ld-x86-64/x86-64.exp: Run load1a, load1b, load1c and load1d
tests. Run gotpcrel1 test.
This patch adds support for the R_386_GOT32X relocation proposed in
https://groups.google.com/forum/#!topic/ia32-abi/GbJJskkid4I
to gas and ld. It updates gas to generate R_386_GOT32X relocation for
memory operand, foo@GOT[(%reg)]. We must encode "mov foo@GOT, %eax"
with the 0x8b opcode, instead of the 0xb8 opcode, so that it can be
transformed to "lea foo, %eax". With the locally defined symbol, foo,
we convert
mov foo@GOT[(%reg1)], %reg2
to
lea foo[@GOTOFF(%reg1)], %reg2
and convert
call/jmp *foo@GOT[(%reg)]
to
nop call foo/jmp foo nop
When PIC is false, convert
test %reg1, foo@GOT[(%reg2)]
to
test $foo, %reg1
and convert
binop foo@GOT[(%reg1)], %reg2
to
binop $foo, %reg2
where binop is one of adc, add, and, cmp, or, sbb, sub, xor instructions.
bfd/
* elf32-i386.c: Include opcode/i386.h.
(elf_howto_table): Add R_386_GOT32X.
(R_386_ext2): Replace R_386_IRELATIVE with R_386_GOT32X.
(elf_i386_reloc_type_lookup): Handle BFD_RELOC_386_GOT32X.
(need_convert_mov_to_lea): Renamed to ...
(need_convert_load): This.
(elf_i386_check_relocs): Handle R_386_GOT32X. Replace
need_convert_mov_to_lea with need_convert_load.
(elf_i386_gc_sweep_hook): Handle R_386_GOT32X.
(elf_i386_size_dynamic_sections): Likewise.
(elf_i386_relocate_section): Likewise.
(elf_i386_convert_mov_to_lea): Renamed to ...
(elf_i386_convert_load): This. Replace need_convert_mov_to_lea
with need_convert_load. Support R_386_GOT32X transformations.
* reloc.c (BFD_RELOC_386_GOT32X): New.
* bfd-in2.h: Regenerated.
* libbfd.h: Likewise.
gas/
* config/tc-i386.c (tc_i386_fix_adjustable): Handle
BFD_RELOC_386_GOT32X.
(tc_gen_reloc): Likewise.
(match_template): Force 0x8b encoding for "mov foo@GOT, %eax".
(output_disp): Check for "call/jmp *mem", "mov mem, %reg",
"test %reg, mem" and "binop mem, %reg" where binop is one of
adc, add, and, cmp, or, sbb, sub, xor instructions. Set
fx_tcbit if the REX prefix is generated. Set fx_tcbit2 if
BFD_RELOC_386_GOT32X should be generated.
(i386_validate_fix): Generate BFD_RELOC_386_GOT32X if fx_tcbit2
is set.
gas/testsuite/
* gas/i386/got.d: New file.
* gas/i386/got.s: Likewise.
* gas/i386/i386.exp: Run got.
* gas/i386/localpic.d: Replace R_386_GOT32 with R_386_GOT32X.
* gas/i386/mixed-mode-reloc32.d: Likewise.
* gas/i386/reloc32.d: Likewise.
include/elf/
* i386.h (R_386_GOT32X): New relocation.
ld/testsuite/
* ld-i386/branch1.d: New file.
* ld-i386/branch1.s: Likewise.
* ld-i386/call1.d: Likewise.
* ld-i386/call1.s: Likewise.
* ld-i386/call2.d: Likewise.
* ld-i386/call2.s: Likewise.
* ld-i386/got1.dd: Likewise.
* ld-i386/got1.out: Likewise.
* ld-i386/got1a.S: Likewise.
* ld-i386/got1b.c: Likewise.
* ld-i386/got1c.c: Likewise.
* ld-i386/got1d.S: Likewise.
* ld-i386/jmp1.d: Likewise.
* ld-i386/jmp1.s: Likewise.
* ld-i386/jmp2.d: Likewise.
* ld-i386/jmp2.s: Likewise.
* ld-i386/load1.d: Likewise.
* ld-i386/load1.s: Likewise.
* ld-i386/load2.d: Likewise.
* ld-i386/load2.s: Likewise.
* ld-i386/load3.d: Likewise.
* ld-i386/load3.s: Likewise.
* ld-i386/load4.s: Likewise.
* ld-i386/load4a.d: Likewise.
* ld-i386/load4b.d: Likewise.
* ld-i386/load5.s: Likewise.
* ld-i386/load5a.d: Likewise.
* ld-i386/load5b.d: Likewise.
* ld-i386/load6.d: Likewise.
* ld-i386/load6.s: Likewise.
* ld-i386/i386.exp: Run branch1, call1, call2, jmp1, jmp2,
load1, load2, load3, load4a, load4b, load5a, load5b and load6
tests. Run got1 test.
PR gas/19109
. * configure.ac: Note the 'none' is an acceptable argument to
--enable-compressed-debug-sections.
* configure: Regenerate.
gas * configure.ac: Restore --enable-compressed-debug-sections.
Do not enable compressed debug sections by default for x86 Linux
targets.
* configure: Regenerate.
ld * configure.ac: Add --enable-compressed-debug-sections.
* configure: Regenerate.
* config.in: Regenerate.
* ld.texinfo: Document how to determine the default action for
debug sections.
* ldmain.c (main): If DEFAULT_FLAG_COMPRESS_DEBUG is defined then
set the compress_debug field of the link_info structure to
zlib-gabi.
* lexsup.c (elf_static_list_options): Output the default setting
for the --compress-debug-sections option.
* NEWS: Mention the new configure option.
This patch removes the gas configure option:
--enable-compressed-debug-sections
and adds a toplevel configure option:
--enable-compressed-debug-sections={all,gas,gold,ld}
to enable compressed debug sections for gas, gold or ld by default. At
the moment, this configure option is ignored by gold and ld. For x86
Linux targets, default to compressing debug sections in gas.
PR gas/19109
* configure.ac: Add
--enable-compressed-debug-sections={all,gas,gold,ld}.
* configure: Regenerated.
gas/
PR gas/19109
* NEWS: Update --enable-compressed-debug-sections=.
* configure.ac: Remove --enable-compressed-debug-sections.
(DEFAULT_FLAG_COMPRESS_DEBUG): Check
--enable-compressed-debug-sections={all,gas} instead of
--enable-compressed-debug-sections. For x86 Linux targets,
default to compressing debug sections.
* configure: Regenerated.
PR gas/19109
* configure.ac: Add option --enable-compressed-debug-sections.
This sets the default behaviour for compressing debug sections.
* as.c (flag_compress_debug): Define and initialise to
COMPRESS_DEBUG_GABI_ZLIB if DEFAULT_COMPRESS_DEBUG is set.
(show_usage): Indicate whether --no-compress-debug-sections
or --compress-debug-sections is the default.
* config/tc-i386.c (flag_compress_debug): Delete definition.
* doc/as.texinfo (--nocompress-debug-sectionas): Update
description.
* NEWS: Announce the new feature.
* config.in: Regenerate.
* configure: Regenerate.
* config/tc-msp430.c (msp430_mcu_names): Rename to
msp430_mcu_data. Add fields for the ISA and hardware multiply
support. Update with information from the latest devices.csv
file.
(md_parse_option): Make use of the new array.
This commit fixes a few issues in the mechanism for passing information
about ".org" and ".align" directives from the assembler to the linker,
used by the avr target.
In the original commit fdd410ac7a, there
were some mistakes when writing out information about ".align"
directives:
- An align with fill does not write out its information correctly, the
fill data overwrites the alignment data.
- Each alignment directive is recorded at the location where the
previous alignment directive should be recorded, the first alignment
directive is discarded.
In commit 137c83d69f, the data produced by
objdump is not correct:
- It's miss-aligned due to a missing whitespace.
- The fill data for align with fill records is not displayed
correctly.
All of the above issues are addressed in this commit, and the test is
improved to cover these cases.
binutils/ChangeLog:
* od-elf32_avr.c (elf32_avr_dump_avr_prop): Fix printing of align
specific data, fix formatting for align and org data.
gas/ChangeLog:
* config/tc-avr.c (avr_output_property_record): Fix overwrite bug
for align and fill records.
(avr_handle_align): Record fill information for align frags.
(create_record_for_frag): Add next frag assertion, use correct
address for align records.
gas/testsuite/ChangeLog:
* gas/avr/avr-prop-1.s: Use fill in some cases.
* gas/avr/avr-prop-1.d: Update expected results.
'template' is used in include/opcode/aarch64.h as below,
typedef struct
{
const char *template;
uint32_t value;
int has_xt;
} aarch64_sys_ins_reg;
and it triggers compilation errors when GDB is built in C++ mode.
In file included from git/gdb/aarch64-tdep.c:62:0:
git/gdb/../include/opcode/aarch64.h:651:15: error: expected unqualified-id before 'template'
const char *template;
This patch is to rename field template to name.
gas/
* config/tc-aarch64.c (md_begin): Access field 'name' rather
than 'template'.
include/opcode/
* aarch64.h (aarch64_sys_ins_reg) <template>: Removed.
<name>: New field.
opcodes/
* aarch64-dis.c (aarch64_ext_sysins_op): Access field
'name' rather than 'template'.
* aarch64-opc.c (aarch64_print_operand): Likewise.
gas * doc/c-s390.texi: Add documentation.
Add missing code markup.
* config/tc-s390.c (current_flags): New static variable.
(s390_parse_cpu): Parse cpu flags a la "+nohtm" etc.
(s390_setup_opcodes): Use cpu flags to determine the set of opcodes.
Fix indentation.
(md_parse_option): Call s390_parse_cpu with the new signature.
(s390_machine): Likewise.
Keep track of current_flags.
Simplify code a bit.
undefine MAX_HISTORY at end of function.
(s390_machinemode): undefine MAX_HISTORY at end of function.
Update an error message.
tests * gas/s390/s390.exp: Add new tests.
* gas/s390/machine-parsing-1.s: New test file.
* gas/s390/machine-parsing-1.l: Likewise.
* gas/s390/machine-parsing-2.s: Likewise.
* gas/s390/machine-parsing-2.l: Likewise.
* gas/s390/machine-parsing-3.s: Likewise.
* gas/s390/machine-parsing-3.l: Likewise.
* gas/s390/machine-parsing-4.s: Likewise.
* gas/s390/machine-parsing-4.l: Likewise.
* gas/s390/machine-parsing-5.s: Likewise.
* gas/s390/machine-parsing-5.l: Likewise.
* gas/s390/machine-parsing-6.s: Likewise.
* gas/s390/machine-parsing-6.l: Likewise.
opcode * s390.h (S390_INSTR_FLAG_HTM): New flag.
(S390_INSTR_FLAG_VX): New flag.
(S390_INSTR_FLAG_FACILITY_MASK): New flag mask.
opcodes * s390-mkopc.c (main): Parse htm and vx flag.
* s390-opc.txt: Mark instructions from the hardware transactional
memory and vector facilities with the "htm"/"vx" flag.
gas PR ld/18759
* config/tc-or1k.c (tc_gen_reloc): Correct computation of PC
relative relocs.
* config/tc-or1k.h (GAS_CGEN_PRCEL_R_TYPE): Delete.
bfd * elf32-or1k.c (R_OR1K_32_PCREL): Set pcrel_offset to TRUE.
(R_OR1K_16_PCREL): Likewise.
(R_OR1K_8_PCREL): Likewise.
ld/tests * ld-elf/eh-frame-hdr: Expect to pass on the or1k-linux target.
Some of the TC_START_LABEL implementations need to adjust the end of
the symbol, when a colon doesn't mean a label definition. That means
they need access to nul_char both the restore the NUL location (it may
be a quote rather than a colon) and to store the new nul_char. Others
need adjusting to step over a potential trailing quote.
PR gas/18581
* config/tc-aarch64.h (TC_START_LABEL): Redefine.
* config/tc-arm.c (tc_start_label_without_colon): Delete params.
Use input_line_pointer directly.
* config/tc-arm.h (TC_START_LABEL): Redefine.
(TC_START_LABEL_WITHOUT_COLON): Redefine.
(tc_start_label_without_colon): Update prototype.
* config/tc-bfin.c (bfin_start_label): Delete ptr param. Check
for NUL instead.
* config/tc-bfin.h (bfin_start_label): Update prototype.
(TC_START_LABEL): Redefine.
* config/tc-d30v.h (TC_START_LABEL): Redefine.
* config/tc-fr30.c (restore_colon): Rewrite.
(fr30_is_colon_insn): Add nul_char param. Return int. Bump
i_l_p over quote. Update restore_colon calls.
* config/tc-fr30.h (TC_START_LABEL): Redefine.
(fr30_is_colon_insn): Update prototype.
* config/tc-m32c.c (restore_colon, m32c_is_colon_insn): As above.
* config/tc-m32c.h (TC_START_LABEL): Redefine.
(m32c_is_colon_insn): Update prototype.
* config/tc-m32r.h (TC_START_LABEL): Redefine.
* config/tc-mep.h (TC_START_LABEL): Redefine.
* config/tc-nds32.h (TC_START_LABEL): Redefine.
* config/tc-tic54x.c (tic54x_start_label): Replace params with
nul_char and next_char. Step over trailing quote.
* config/tc-tic54x.h (TC_START_LABEL_WITHOUT_COLON): Redefine.
(tic54x_start_label): Update prototype.
* read.c (TC_START_LABEL): Redefine. Update invocation.
(TC_START_LABEL_WITHOUT_COLON): Update invocation.
* config/tc-nios2.c (s_nios2_set): Save initial input_line_pointer
and restore if calling s_set. Don't restore delim again.
PR gas/18581
* config/tc-mn10200.c (md_assemble <mdr>): Move restore_line_pointer
call to where input line used to be restored.
* config/tc-mn10300.c (md_assemble <usp>): Remove redundant input
line restore.
* config/tc-tilepro.c (parse_reg_expression): Add regname var.
opcodes/ChangeLog:
2015-08-25 Jose E. Marchesi <jose.marchesi@oracle.com>
* sparc-dis.c (print_insn_sparc): Handle the privileged register
%pmcdper.
gas/ChangeLog:
2015-08-25 Jose E. Marchesi <jose.marchesi@oracle.com>
* config/tc-sparc.c (priv_reg_table): New privileged register
%pmcdper.
gas/testsuite/ChangeLog:
2015-08-25 Jose E. Marchesi <jose.marchesi@oracle.com>
* gas/sparc/wrpr.s: Test writing to the privileged %pmcdper
register.
* gas/sparc/wrpr.d: ...and the expected result.
* gas/sparc/rdpr.s: Test reading from the privileged %pmcdper
register.
* gas/sparc/rdpr.d: ...and the expected result.
_start:
.byte 0f-_start
0:
Fixes
..:2: Error: floating point number invalid
..:2: Error: junk at end of line, first unrecognized character is `_'
* expr.c (operand): Rewrite handling of operands starting with "0f".
If atof_generic only parses "-" or "+", treat as expression.
* expr.c (integer_constant): Return O_absent expression if eol.
(operand): For targets with both LOCAL_LABELS_FB and
NUMBERS_WITH_SUFFIX set, treat "0b" not followed by binary
digits as a local label reference. Correct handling of 0b prefix.
If a suffix is not allowed, error on 0B.
Auto-litpools is the automated version of text-section-literals: literal
pool candidate frags are planted every N frags and during relaxation
they are turned into actual literal pools where literals are moved to
become reachable for their first reference by L32R instruction.
2015-08-12 David Weatherford <weath@cadence.com>
gas/
* config/tc-xtensa.c (struct litpool_frag, struct litpool_seg):
New structures.
(xtensa_maybe_create_literal_pool_frag): New function.
(litpool_seg_list, auto_litpools, auto_litpool_limit)
(litpool_buf, litpool_slotbuf): New static variables.
(option_auto_litpools, option_no_auto_litpools)
(option_auto_litpool_limit): New enum identifiers.
(md_longopts): Add entries for auto-litpools, no-auto-litpools
and auto-litpool-limit.
(md_parse_option): Handle option_auto_litpools,
option_no_auto_litpools and option_auto_litpool_limit.
(md_show_usage): Add help for --[no-]auto-litpools and
--auto-litpool-limit.
(xtensa_mark_literal_pool_location): Record a place for literal
pool with a call to xtensa_maybe_create_literal_pool_frag.
(get_literal_pool_location): Find highest priority literal pool
or convert candidate to literal pool when auto-litpools are used.
(xg_assemble_vliw_tokens): Create literal pool after jump
instruction.
(xtensa_check_frag_count): Create candidate literal pool every
auto_litpool_limit frags.
(xtensa_relax_frag): Add jump around literals to non-empty
literal pool.
(xtensa_move_literals): Estimate literal pool addresses and move
unreachable literals closer to their users, converting candidate
to literal pool if needed.
(xtensa_switch_to_non_abs_literal_fragment): Only emit error
about missing .literal_position in case auto-litpools are not
used.
* config/tc-xtensa.h (xtensa_relax_statesE): New relaxation
state: RELAX_LITERAL_POOL_CANDIDATE_BEGIN.
* doc/as.texinfo (Xtensa options): Document --auto-litpools and
--no-auto-litpools options.
* doc/c-xtensa.texi (Xtensa options): Likewise.
2015-08-12 Max Filippov <jcmvbkbc@gmail.com>
gas/testsuite/
* gas/xtensa/all.exp: Add auto-litpools to the list of xtensa
tests.
* gas/xtensa/auto-litpools.s: New file: auto-litpools test.
* gas/xtensa/auto-litpools.s: New file: auto-litpools test
result pattern.
PR gas/18765
* config/tc-arm.c (move_or_literal_pool): Use U suffix to remove
compile time warnings about constant expressions being shifted
into bit 31.
(do_iwmmxt_wldstd): Likewise.
(do_iwmmxt_wrwrwr_or_imm5): Likewise.
(md_assemble): Likewise.
gas * config/tc-rl78.c (rl78_abs_sym): New local variable.
(md_begin): Initialise the new symbol.
(OPIMM): Define the value to be relative to the new symbol and not
the absolute section symbol.
ld * emulparams/elf32rl78.sh (OTHER_SECTIONS): Provide a value for
the _-rl78_abs__ symbol.
tests * gas/all/struct.d: Allow for extra symbols in the output.
* gas/macros/test1.d: Likewise.
* gas/elf/elf.exp: Add an rl78 machine.
* gas/elf/sections2e-rl78: New file.
tests * binutils-all/localize-hidden-1.d: Allow for extra symbols in the
output.
* binutils-all/strip-11.d: Skip for the RL78.
This fixes a segfault when macro definitions end on the last line of a
file, and that line isn't properly terminated with a newline. gas
used to throw away the last line in cases like this, whereas in other
cases gas added the missing newline. So I've also made gas
consistently provide a missing newline.
PR gas/18687
* input-scrub.c (input_scrub_next_buffer): Rearrange and simplify
loop. Don't drop lines at end of file lacking a newline, add a
newline instead. Ensure partial_size is zero whenever
partial_where is NULL. Adjust buffer size for extra char.
(input_scrub_push, input_scrub_begin): Adjust buffer size here too.
The default compression is gABI compliant now. This patch makes the
x86 Linux assembler default to gABI compliant.
* config/tc-i386.c (flag_compress_debug): Replace
COMPRESS_DEBUG_GNU_ZLIB with COMPRESS_DEBUG_GABI_ZLIB.
All programs in binutils+gdb git repo now support gABI compression
with the SHF_COMPRESSED bit. This patch makes the zlib-gabi option
as compression default for gas, gold, ld and objcopy, instead of the
zlib-gnu option whose outputs are incompatible with gABI.
binutils/
* objcopy.c (copy_file): Set BFD_COMPRESS_GABI if not
zlib-gnu.
* doc/binutils.texi: Change --compress-debug-sections and
--compress-debug-sections=zlib to zlib-gabi.
binutils/testsuite/
* binutils-all/compress.exp: Update.
gas/
* as.c (parse_args): Make --compress-debug-sections and
--compress-debug-sections=zlib the same as
--compress-debug-sections=zlib-gabi.
* doc/as.texinfo: Change --compress-debug-sections and
--compress-debug-sections=zlib to zlib-gabi.
gold/
* compressed_output.cc (Output_compressed_section::set_final_data_size):
Make --compress-debug-sections=zlib the same as
--compress-debug-sections=zlib-gabi.
* testsuite/Makefile.am (flagstest_compress_debug_sections.check):
Expect ".debug_.*" with the SHF_COMPRESSED bit, instead of
".zdebug_".
* testsuite/Makefile.in: Regenerated.
ld/
* emultempl/elf32.em (gld${EMULATION_NAME}_handle_option): Make
--compress-debug-sections=zlib the same as
--compress-debug-sections=zlib-gabi.
* ld.texinfo: Change --compress-debug-sections=zlib to zlib-gabi.
ld/testsuite/
* ld-elf/zlibbegin.rS: Updated to .debug_.* with the
SHF_COMPRESSED bit.
* ld-elf/zlibnormal.rS: Likewise.
When generating relocation (tc_gen_reloc) 32 bit relocation fixup
is changed to new 32 bit PC relative relocation if the fixup has pc-relative
flag set.
bfd/ChangeLog
2015-07-06 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
* elf32-avr.c: Add 32 bit PC relative relocation for AVR target.
gas/ChangeLog
2015-07-06 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
* config/tc-avr.c (tc_gen_reloc): Change 32 bit relocation to
32 bit PC relative and update offset if the fixup is pc-relative.
* config/tc-avr.h (DIFF_EXPR_OK): Define to enable PC relative diff
relocs.
gas/testsuite/ChangeLog
2015-07-06 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
* gas/avr/pc-relative-reloc.d: New test for 32 bit pc relative reloc.
* gas/avr/per-function-debugline.s: New test source.
include/ChangeLog
2015-07-06 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
* elf/avr.h: Add new 32 bit PC relative relocation.
ld/testsuite/ChangeLog
2015-07-06 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
* ld-avr/gc-section-debugline.d: New test.
* ld-avr/per-function-debugline.s: Source for new test.
Back in the day support for these processors was added, we probably
didn't want to waste PPC_OPCODE bits on minor variations. I've had a
complaint that disassembly of mfspr/mtspr was wrong for power8. This
patch fixes that problem.
Note that since -m860/-m850/-m821 are new gas options enabling the
mpc8xx specific mfspr/mtspr variants it is possible that this change
will break some mpc8xx assembly code. ie. you might need to modify
makefiles to pass -m860 to gas.
include/opcode/
* ppc.h (PPC_OPCODE_750, PPC_OPCODE_7450, PPC_OPCODE_860): Define.
opcodes/
* ppc-opc.c (PPC750, PPC7450, PPC860): Define using PPC_OPCODE_*.
* ppc-dis.c (ppc_opts): Add 821, 850 and 860 entries. Add
PPC_OPCODE_7450 to 7450 entry. Add PPC_OPCODE_750 to 750cl entry.
gas/
* config/tc-ppc.c (md_show_usage): Add -m821, -m850, -m860.
* doc/c-ppc.texi (PowerPC-Opts): Likewise.
gas/testsuite/
* gas/ppc/titan.d: Correct mfmcsrr0 disassembly.
Commit 2f0c68f23b added an extra @section
.cfi_lsda:
@subsection @code{.cfi_lsda @var{encoding} [, @var{exp}]}
+@section @code{.cfi_lsda @var{encoding} [, @var{exp}]}
@code{.cfi_lsda} defines LSDA and its encoding.
It shouldn't be there.
* doc/as.texinfo (.cfi_lsda): Remove the extra @section.
ISA 2.07 (ie, POWER8) added the rfebb instruction which takes one operand
with the value of either a 0 or 1. It also defines an extended mnemonic
with no operands (ie, "rfebb") that is supposed to be equivalent to "rfebb 1".
I implemented rfebb's lone operand with PPC_OPERAND_OPTIONAL, but the
problem is, optional operands that are ommitted always default to the
value 0, which is wrong in this case. I have added support for allowing
non-zero default values by adding an additional flag PPC_OPERAND_OPTIONAL_VALUE
that specifies that the default operand value to be used is stored in the
SHIFT field of the operand field immediately following this one.
This fixes the rfebb issue. I also fixed the mftb and mfcr instructions
so they use the same mechanism. This allows us to flag invalid uses of
mfcr where we explicitly pass in a zero FXM value, like the use in a2.[sd].
include/opcode/
* ppc.h (PPC_OPERAND_OPTIONAL_VALUE): New.
(ppc_optional_operand_value): New inline function.
opcodes/
* ppc-dis.h (skip_optional_operands): Use ppc_optional_operand_value.
* ppc-opc.c (FXM4): Add non-zero optional value.
(TBR): Likewise.
(SXL): Likewise.
(insert_fxm): Handle new default operand value.
(extract_fxm): Likewise.
(insert_tbr): Likewise.
(extract_tbr): Likewise.
gas/
* config/tc-ppc.c (md_assemble): Use ppc_optional_operand_value.
Allow for optional operands without insert functions.
gas/testsuite/
* gas/ppc/power8.d: Fixup rfebb test results.
* gas/ppc/a2.s: Fix invalid mfcr test.
* gas/ppc/a2.d: Likewise.
PR gas/18541
gas * config/tc-arm.c (md_apply_fix): Add support for ADR in thumb
mode against a nearby symbol.
tests * gas/arm/thumb.s: Add test of ADR against a nearby symbol.
* gas/arm/thumb.d: Update expected output.
* gas/arm/thumb-eabi.d: Likewise.
PR gas/18481
bfd * elf32-arm.c (R_ARM_TLS_LE32): Set the special function to NULL.
gas * config/tc-arm.c (tc_gen_reloc): Include BFD_RELOC_ARM_TLS_LE32
in the same case as BFD_RELOC_ARM_TLS_IS32.
tests * gas/arm/tls.s: Add tests of the tpoff pseudo with a local
symbol.
* gas/arm/tls.d: Update expected output.
* config/tc-arm.c (is_double_a_single): Make conditional upon the
availablity of a 64-bit type. Use this type for the argument and
mantissa.
(double_to_single): Likewise.
* config/tc-arm.c (move_or_literal_pool): Use a 64-bit type for
the constant value, if available. Generate a 64-bit value from a
bignum if supported. Only perform the second optimization for
PR 18500 if the 64-bit type is available.
PR gas/18499
gas * config/tc-arm.c (move_or_literal_pool): Add support for LDR Rx,=
to MOV.w or MVN.w for Thumb2.
tests * gas/arm/thumb2_ldr_immediate_armv6.s: New test case.
* gas/arm/thumb2_ldr_immediate_armv6.d: Expected disassembly.
* gas/arm/thumb2_ldr_immediate_armv6t2.s: New test case.
* gas/arm/thumb2_ldr_immediate_armv6t2.d: Expected disassembly.
PR gas/18500
gas * config/tc-arm.c (is_double_a_single): New function.
(double_to_single): New function.
(move_or_literal_pool): Add support for converting VLDR to VMOV.
tests * gas/arm/vfpv2-ldr_immediate.s: New test case.
* gas/arm/vfpv2-ldr_immediate.d: Expected disassembly.
* gas/arm/vfpv3-ldr_immediate.s: New test case.
* gas/arm/vfpv3-ldr_immediate.d: Expected disassembly.
* gas/arm/vfpv3xd-ldr_immediate.s: New test case.
* gas/arm/vfpv3xd-ldr_immediate.d: Expected disassembly.
This patch adds the ability to automatically construct a section name
based on the prior section.
When gas is invoked with --sectname-subst, the occurrence of %S in a
section name will be substituted by the name of the current section. For
example:
.macro exception_code
.pushsection %S.exception
[exception code here]
.popsection
.endm
.text
[code]
exception_code
[...]
.section .init
[init code]
exception_code
[...]
The first and second exception_code invocations create the
.text.exception and the .init.exception sections respectively. This is
useful e.g. to discriminate between anciliary sections that are tied to
.init code and can be discarded at run time when initialization is over
vs anciliary sections tied to .text sections that need to stay resident.
* as.c (show_usage): Document --sectname-subst.
(parse_args): Add --sectname-subst.
* as.h (flag_sectname_subst): New.
* config/obj-elf.c (obj_elf_section_name): Add %S substitution.
* doc/as.texinfo: Document it.
out_debug_aranges uses frag_align to make sure the addresses start
out aligned. Using frag_align will call frag_var[_init], which will
end up calling TC_FRAG_INIT. On arm and aarch64 TC_FRAG_INIT will
generate a $d mapping symbol for the .debug_aranges to show that at
that point a sequence of data items starts.
Such a symbol pointing into a non-allocated debug section will confuse
eu-strip -g. And it seems inefficient and wrong in general to have
additional mapping symbols for debug sections, which won't contain
actual code in the first place.
Just keep track of the aranges header size and use plain padding to
align the addresses which avoids generating any mapping symbols on
aarch64 and arm.
Includes a testcase for aarch64 that PASS with this patch and shows
the extra $d mapping symbol in .debug_aranges before.
gas/ChangeLog
* dwarf2dbg.c (out_header): Document EXPR->X_add_number value,
out_debug_aranges depends on it.
(out_debug_aranges): Track size of header to properly pad header
for address alignment.
gas/testsuite/ChangeLog
* gas/aarch64/dwarf.d: New.
* gas/aarch64/dwarf.s: New.
