Commit graph

17 commits

Author SHA1 Message Date
Mike Frysinger
efac2223c4 sim: bfin: allow pushing of SP
The hardware respects this insn, and some code (like the on-chip bootrom)
uses it, so allow it.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-05-14 16:00:37 +00:00
Mike Frysinger
0427acfba0 sim: bfin: use store buffer with more 32bit insns
A bunch of 32bit insns were not using the store buffer, so when they were
used in parallel insns, they would incorrectly clobber a register early.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-04-16 17:37:55 +00:00
Mike Frysinger
d2cfa400a1 sim: bfin: handle implicit DISALGNEXCPT with video insns
When most video related insns are used in parallel with Ireg loads, the
DISALGNEXCPT insn behavior is implicitly in effect.

Reported-by: Anton Shokurov <shokurov.anton.v@yandex.ru>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-04-15 01:21:21 +00:00
Mike Frysinger
1a3af0bfc3 sim: bfin: fix sign extension with 16bit acc add insns
The current implementation attempts to handle the 16bit sign extension
itself.  Unfortunately, it gets it right in some cases.  So rather than
fix that logic, just drop it in favor of using 16bit signed casts.  Now
gcc will take care of getting the logic right.

Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-29 01:41:49 +00:00
Mike Frysinger
36aef94270 sim: bfin: handle saturation with RND12 sub insns
The current handling of the subtraction insn with the RND12 modifier
works when saturation isn't involved.  So add handling for this edge
case to match the hardware.

Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-27 04:03:05 +00:00
Mike Frysinger
fcd1ee07d3 sim: bfin: add missing VS set with add/sub insns
The 16bit add/sub insns missed setting the VS bit in ASTAT whenever the
V bit was also set.

Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-26 06:02:41 +00:00
Mike Frysinger
8e670c0a3f sim: bfin: update VIT_MAX behavior to match hardware when Acc.X bits are set
The Blackfin PRM says that the top 8 bits of the accumulator must be
cleared when using the VIT_MAX insn, so the sim has followed this spec.
Matching the hardware behavior though when the high bits are not cleared
is easy to do and doesn't break existing behavior, so go for it.

Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-24 03:14:20 +00:00
Mike Frysinger
de0addfbef sim: bfin: always do 16bit sign extension with the SEARCH insn
The Blackfin PRM does not cover this case, but the hardware is clear: even
if the search criteria is not met (and thus a new 16bit value is loaded up
into the accumulator), the accumulator undergoes 16bit sign extension.  So
simply reload the low signed 16bits in that case.

Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-24 03:13:32 +00:00
Mike Frysinger
beb378a5f2 sim: bfin: update AV and AC ASTAT bits with acc negation
The Acc=-Acc insn can overflow or carry with edge values, so make sure
we update the ASTAT bits accordingly to match the hardware.  Also fix
a thinko where we always updated AC0 even when working with A1 regs.

Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-24 03:12:16 +00:00
Mike Frysinger
8d8a97461a sim: bfin: allow byteop[123]p src regs to be the same
The hardware allows the byteop[123]p insns to use the same src reg pair,
so remove the combination check in the sim.

Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-24 03:08:15 +00:00
Mike Frysinger
227d265839 sim: bfin: handle AZ updates with 16bit adds/subs
We weren't updating AZ when doing a 16bit add or sub insn.  Implement it.

Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-15 20:10:40 +00:00
Mike Frysinger
e3809a37d4 sim: bfin: skip acc/ASTAT updates for moves
No point in moving unchanged acc values to the acc regs, and avoid
updating the acc ASTAT bits when only reading.  This fixes incorrect
changing of the ASTAT bits when they're only being read.

Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-15 20:10:12 +00:00
Mike Frysinger
86d3d8de68 sim: bfin: handle AN (negative overflows) in dsp mult insns
The current dsp mult handler does not take care of overflows which turn
values negative (and thus set AN in ASTAT).  So implement it.

Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-15 20:09:39 +00:00
Mike Frysinger
9b7509d900 sim: bfin: handle V overflows in dsp mult insns
The current dsp mult handler does not take care of overflows and updating
the V ASTAT bit.  So implement it.

Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-15 20:09:09 +00:00
Mike Frysinger
bf416ccded sim: bfin: decode ASTAT on failure
When testing ASTAT regs, specific bit differences carry a lot more meaning
than when checking the value of a data register.  So automatically decode
the bits of the two values and print things out so that people don't have
to manually do it themselves every time.

Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-15 20:08:27 +00:00
Mike Frysinger
c9329594d4 sim: bfin: handle saturation with fract multiplications
The saturation behavior with fract modes differs from non-fract modes.

Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-15 20:04:04 +00:00
Mike Frysinger
ef016f835f sim: bfin: new port
This can boot Das U-Boot and a Linux kernel.  It also supports Linux
userspace FLAT and FDPIC (dynamic and static) ELFs.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-06 00:20:21 +00:00