The support for accessing the ARMv8.1 PSTATE field PAN allows
instructions of the form MSR PAN, #<imm> with <imm> any unsigned 4-bit
integer. However, the architecture specification requires that the
immediate is either 0 or 1.
This patch implements the constraint on the immediate, generating an
error if the immediate operand is invalid, and adds tests for the
illegal forms.
opcodes/
2015-11-19 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-opc.c (operand_general_constraint_met_p): Check validity
of MSR PAN immediate operand.
gas/testsuite/
2015-11-19 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/pan-illegal.d: New.
* gas/aarch64/pan-illegal.l: New.
* gas/aarch64/pan.s: Add tests for invalid immediates.
Change-Id: Ibb3056c975eb792104da138d94594224f56a993e
opcode * rx.h (enum RX_Operand_Type): Add RX_Operand_Zero_Indirect.
opcodes * rx-decode.opc (rx_disp): If the displacement is zero, set the
type to RX_Operand_Zero_Indirect.
* rx-decode.c: Regenerate.
* rx-dis (print_insn): Handle RX_Operand_Zero_Indirect.
gas * config/rx-parse.y: Allow zero value for 5-bit displacements.
tests * gas/rx/mov.sm: Add tests for zero offset indirect moves.
* gas/rx/mov.d: Update expected output.
Nowadays aarch64_decode_insn is a public interface used by both
opcodes and gdb. However, its behaviour relies on a global variable
no_aliases, which isn't a good practise. On the other hand, In default,
no_aliases is zero, but in GDB, we do want no alias when decoding
instructions for prologue analysis (patches to be posted), so that we
can handle both instructions "add" and "mov" (an alias of "add") as
"add". The code in GDB can be simplified.
This patch adds a new argument in aarch64_decode_insn, and pass no_aliases
to it. In GDB side, always pass 1 to it.
include/opcode:
2015-10-28 Yao Qi <yao.qi@linaro.org>
* aarch64.h (aarch64_decode_insn): Update declaration.
opcodes:
2015-10-28 Yao Qi <yao.qi@linaro.org>
* aarch64-dis.c (aarch64_decode_insn): Add one argument
noaliases_p. Update comments. Pass noaliases_p rather than
no_aliases to aarch64_opcode_decode.
(print_insn_aarch64_word): Pass no_aliases to
aarch64_decode_insn.
gdb:
2015-10-28 Yao Qi <yao.qi@linaro.org>
* aarch64-tdep.c (aarch64_software_single_step): Pass 1 to
aarch64_decode_insn.
PR binutils/19159
opcodes * rl78-decode.opc (MOV): Added offset to DE register in index
addressing mode.
* rl78-decode.c: Regenerate.
test * gas/rl78/pr19159.s: New test source file.
* gas/rl78/pr19159.d: New test case.
* gas/rl78/rl78.exp: Run the new test.
PR binutils/19158
opcodes * rl78-decode.opc: Add 's' print operator to instructions that
access system registers.
* rl78-decode.c: Regenerate.
* rl78-dis.c (print_insn_rl78_common): Decode all system
registers.
tests * gas/rl78/pr19158.s: New test source file.
* gas/rl78/pr19158.d: New test case.
* gas/rl78/rl78.exp: Run the new test.
PR binutils/19157
opcodes * rl78-decode.opc: Add 'a' print operator to mov instructions
using stack pointer plus index addressing.
* rl78-decode.c: Regenerate.
tests * gas/rl78: New directory.
* gas/rl78/rl78.exp: New test driver.
* gas/rl78/pr19157.s: New test source file.
* gas/rl78/pr19157.d: New test case.
opcodes/ChangeLog:
2015-10-14 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* s390-opc.c: Fix comment.
* s390-opc.txt: Change instruction type for troo, trot, trto, and
trtt to RRF_U0RER since the second parameter does not need to be a
register pair.
gas/testsuite/ChangeLog:
2015-10-14 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* gas/s390/esa-g5.d: Use odd GPR for the second operand.
* gas/s390/esa-g5.s: Likewise.
* gas/s390/esa-z9-109.d: Likewise.
* gas/s390/esa-z9-109.s: Likewise.
'template' is used in include/opcode/aarch64.h as below,
typedef struct
{
const char *template;
uint32_t value;
int has_xt;
} aarch64_sys_ins_reg;
and it triggers compilation errors when GDB is built in C++ mode.
In file included from git/gdb/aarch64-tdep.c:62:0:
git/gdb/../include/opcode/aarch64.h:651:15: error: expected unqualified-id before 'template'
const char *template;
This patch is to rename field template to name.
gas/
* config/tc-aarch64.c (md_begin): Access field 'name' rather
than 'template'.
include/opcode/
* aarch64.h (aarch64_sys_ins_reg) <template>: Removed.
<name>: New field.
opcodes/
* aarch64-dis.c (aarch64_ext_sysins_op): Access field
'name' rather than 'template'.
* aarch64-opc.c (aarch64_print_operand): Likewise.
We want to use disas_aarch64_insn inside GDB to decode instructions, so
this patch exposes it and rename it to aarch64_decode_insn to follow
the conventions of other interfaces.
include/opcode:
2015-10-02 Yao Qi <yao.qi@linaro.org>
* aarch64.h (aarch64_decode_insn): Declare it.
opcodes:
2015-10-02 Yao Qi <yao.qi@linaro.org>
* aarch64-dis.c (disas_aarch64_insn): Remove static. Change
argument insn type to aarch64_insn. Rename to ...
(aarch64_decode_insn): ... it.
(print_insn_aarch64_word): Caller updated.
I happen to see that argument pc is not used inside disas_aarch64_insn
at all. This patch is to remove it.
OK to apply?
opcodes:
2015-10-02 Yao Qi <yao.qi@linaro.org>
* aarch64-dis.c (disas_aarch64_insn): Remove argument PC.
(print_insn_aarch64_word): Caller updated.
gas * doc/c-s390.texi: Add documentation.
Add missing code markup.
* config/tc-s390.c (current_flags): New static variable.
(s390_parse_cpu): Parse cpu flags a la "+nohtm" etc.
(s390_setup_opcodes): Use cpu flags to determine the set of opcodes.
Fix indentation.
(md_parse_option): Call s390_parse_cpu with the new signature.
(s390_machine): Likewise.
Keep track of current_flags.
Simplify code a bit.
undefine MAX_HISTORY at end of function.
(s390_machinemode): undefine MAX_HISTORY at end of function.
Update an error message.
tests * gas/s390/s390.exp: Add new tests.
* gas/s390/machine-parsing-1.s: New test file.
* gas/s390/machine-parsing-1.l: Likewise.
* gas/s390/machine-parsing-2.s: Likewise.
* gas/s390/machine-parsing-2.l: Likewise.
* gas/s390/machine-parsing-3.s: Likewise.
* gas/s390/machine-parsing-3.l: Likewise.
* gas/s390/machine-parsing-4.s: Likewise.
* gas/s390/machine-parsing-4.l: Likewise.
* gas/s390/machine-parsing-5.s: Likewise.
* gas/s390/machine-parsing-5.l: Likewise.
* gas/s390/machine-parsing-6.s: Likewise.
* gas/s390/machine-parsing-6.l: Likewise.
opcode * s390.h (S390_INSTR_FLAG_HTM): New flag.
(S390_INSTR_FLAG_VX): New flag.
(S390_INSTR_FLAG_FACILITY_MASK): New flag mask.
opcodes * s390-mkopc.c (main): Parse htm and vx flag.
* s390-opc.txt: Mark instructions from the hardware transactional
memory and vector facilities with the "htm"/"vx" flag.
This fixes the instruction format for 3 of the compare and branch
extended mnemonics. That way the extended mnemonics are actually
being found by objdump.
gas/testsuite/ChangeLog:
2015-09-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* gas/s390/zarch-z10.d: Fix testcase for some of the compare and
branch extended mnemonics.
opcodes/ChangeLog:
2015-09-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* s390-opc.txt: Fix instruction format of crj*, clrj*, and clgrj*.
This is cleanup only.
opcodes/ChangeLog:
2015-09-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* s390-opc.c: Remove unused (and broken) F_20 and FE_20 operand
types and adjust numbering accordingly. Fix some comments.
This makes objdump to be able to recognize some of the extended
mnemonics more often. It does not lead to wrong being generated.
opcodes/ChangeLog:
2015-09-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* s390-opc.c: Fix MASK_RIE_R0PI and MASK_RIE_R0PU.
gas/testsuite/ChangeLog:
2015-09-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* gas/s390/zarch-z10.d: Fix testcase for compare and branch
extended mnemonics.
This is a NOP change only relevant when reading the file or parsing it
with other tools.
opcodes/ChangeLog:
2015-09-09 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* s390-opc.c: Add OP32 definition.
* s390-opc.txt: Reduce the opcode padding of some extended
mnemonics from 6 to the actual length (which is 4).
opcodes/ChangeLog:
2015-08-25 Jose E. Marchesi <jose.marchesi@oracle.com>
* sparc-dis.c (print_insn_sparc): Handle the privileged register
%pmcdper.
gas/ChangeLog:
2015-08-25 Jose E. Marchesi <jose.marchesi@oracle.com>
* config/tc-sparc.c (priv_reg_table): New privileged register
%pmcdper.
gas/testsuite/ChangeLog:
2015-08-25 Jose E. Marchesi <jose.marchesi@oracle.com>
* gas/sparc/wrpr.s: Test writing to the privileged %pmcdper
register.
* gas/sparc/wrpr.d: ...and the expected result.
* gas/sparc/rdpr.s: Test reading from the privileged %pmcdper
register.
* gas/sparc/rdpr.d: ...and the expected result.
opcodes * i386-dis.c (print_insn): Fix decoding of three byte operands.
tests * gas/i386/intel.s: Add test of disassembly of a potential
three byte instuction at the end of a function.
* gas/i386/intel.d: Update expected disassembly.
HJ recently removed trailing space in binutils files, but unfortunately
they return when regenerating files in opcodes. This fixes the regen
process.
* cgen.sh: Trim trailing space from cgen output.
* ia64-gen.c (print_dependency_table): Don't generate trailing space.
(print_dis_table): Likewise.
* opc2c.c (dump_lines): Likewise.
(orig_filename): Warning fix.
* ia64-asmtab.c: Regenerate.
opcodes * arm-dis.c (print_insn_arm): Disassembling for all targets V6
and higher with ARM instruction set will now mark the 26-bit
versions of teq,tst,cmn and cmp as UNPREDICTABLE.
(arm_opcodes): Fix for unpredictable nop being recognized as a teq.
test * gas/arm/nops.d: New.
* gas/arm/nops.s: New.
* gas/arm/inst.d: Changed expectation file for 26-bit teq,
tst, cmn and cmp.
gas/testsuite/
PR binutils/13571
* gas/i386/i386.exp: Run i386-intel and x86_64-intel.
* gas/i386/i386-intel.d: New file.
* gas/i386/x86_64-intel.d: Likewise.
opcodes/
PR binutils/13571
* i386-dis.c (MOD_0FC3): New.
(PREFIX_0FC3): Renamed to ...
(PREFIX_MOD_0_0FC3): This.
(dis386_twobyte): Replace PREFIX_0FC3 with MOD_0FC3.
(prefix_table): Replace Ma with Ev on movntiS.
(mod_table): Add MOD_0FC3.
opcodes * arm-dis.c (print_insn_coprocessor): Added support for quarter
float bitfield format.
(coprocessor_opcodes): Changed VFP vmov reg,immediate to use new
quarter float bitfield format.
tests * gas/arm/vfpv3-const-conv.d: Update expected result due to change
of comment for vmov reg,immediate with VFP coprocessor.
Back in the day support for these processors was added, we probably
didn't want to waste PPC_OPCODE bits on minor variations. I've had a
complaint that disassembly of mfspr/mtspr was wrong for power8. This
patch fixes that problem.
Note that since -m860/-m850/-m821 are new gas options enabling the
mpc8xx specific mfspr/mtspr variants it is possible that this change
will break some mpc8xx assembly code. ie. you might need to modify
makefiles to pass -m860 to gas.
include/opcode/
* ppc.h (PPC_OPCODE_750, PPC_OPCODE_7450, PPC_OPCODE_860): Define.
opcodes/
* ppc-opc.c (PPC750, PPC7450, PPC860): Define using PPC_OPCODE_*.
* ppc-dis.c (ppc_opts): Add 821, 850 and 860 entries. Add
PPC_OPCODE_7450 to 7450 entry. Add PPC_OPCODE_750 to 750cl entry.
gas/
* config/tc-ppc.c (md_show_usage): Add -m821, -m850, -m860.
* doc/c-ppc.texi (PowerPC-Opts): Likewise.
gas/testsuite/
* gas/ppc/titan.d: Correct mfmcsrr0 disassembly.
