Add D8 for 8-bit unsigned field in short load/store insns.
(IF4A, IF4D): These both need two registers.
(IF4C, IF4D): Define. Use 8-bit unsigned field.
(v850_opcodes): For "sld.h", "sld.w", "sst.h", "sst.w", use
IF4C & IF4D. For "trap" use I5U, not I5. Add IF1 operand
for "ldsr" and "stsr".
* v850-opc.c (v850_operands): 3-bit immediate for bit insns
is unsigned.
Fixing up the parser again.
* arm-opc.h: (arm_opcodes): Added halfword and sign-extension
memory transfer instructions. Add new format string entries %h and %s.
* arm-dis.c: (print_insn_arm): Provide decoding of the new
formats %h and %s.
(print_insn_alpha_vms): Remove.
(print_insn_alpha): Make globally visible. Chose the register
names based on info->flavour.
* disassemble.c: Always return print_insn_alpha for the alpha.
* d10v-opc.c: Changes to support signed and unsigned numbers.
All instructions with the same name that have long and short forms
now end in ".l" or ".s". Divs added.
* d10v-dis.c: Changes to support signed and unsigned numbers.
* m68k-opc.c (m68k_opcodes): Make opcode masks for the ColdFire
move ccr/sr insns more strict so that the disassembler only
selects them when the addressing mode is data register.
Mon Jul 22 11:25:24 1996 Martin M. Hunt <hunt@pizza.cygnus.com>
* d10v-opc.c (pre_defined_registers): Declare.
* d10v-dis.c (print_operand): Now uses pre_defined_registers
to pick a better name for the registers.
end-sanitize-d10v
* alpha-dis.c (print_insn_alpha): No longer the user-visible
print routine. Take new regnames and cpumask arguments.
Kill the environment variable nonsense.
(print_insn_alpha_osf): New function. Do OSF/1 style regnames.
(print_insn_alpha_vms): New function. Do VMS style regnames.
* disassemble.c (disassembler): Test bfd flavour to pick
between OSF and VMS routines. Default to OSF.
the 8086 instruction set.
* i386-dis.c: General cleanups. Make most things static. Add
prototypes. Get rid of static variables aflags and dflags. Pass
them as args (to almost everything).
the 8086 instruction set.
* i386-dis.c: General cleanups. Make most things static. Add
prototypes. Get rid of static variables aflags and dflags. Pass
them as args (to almost everything).
* alpha-opc.c: New file.
* alpha-opc.h: Remove.
* alpha-dis.c: Complete rewrite to use new opcode table.
* configure.in: For bfd_alpha_arch, use alpha-opc.o.
* configure: Rebuild with autoconf 2.10.
* Makefile.in (ALL_MACHINES): Add alpha-opc.o.
(alpha-dis.o): Depend upon $(INCDIR)/opcode/alpha.h, not
alpha-opc.h.
(alpha-opc.o): New target.
to just "mode".
start-sanitize-h8s
* disassemble.c (disassembler): Handle H8/S.
* h8300-dis.c (print_insn_h8300s): New function for H8/S.
end-sanitize-h8s
Even more H8/S goo.
not "abs", which may be needed for the absolute in something
like btst #0,@10:8. Print L_3 immediates separately from other
immediates. Change ABSMOV reference to ABS8MEM.
One day we'll actually disassemble btst #0,@10:8 correctly... But not
yet. hmse.
(current_arch_mask): New static global.
(compute_arch_mask): New static function.
(print_insn_sparc): Delete sparc_v9_p. New static local
current_mach. Resort opcode table if current_mach changes.
Generalize "insn not supported" test.
(compare_opcodes): Prefer supported opcodes to nonsupported ones.
Delete test for v9/!v9.
* sparc-opc.c (MASK_*): Use SPARC_OPCODE_ARCH_MASK.
(v6notlet): Define.
(brfc): Split into CBR and FBR for coprocessor/fp branches.
(brfcx): Renamed to FBRX.
(condfc): Renamed to CONDFC. Pass v6notlet to CBR (standard
coprocessor mnemonics are not supported on the sparclet).
(condf): Renamed to CONDF.
(SLCBCC2): Delete F_ALIAS flag.
* configure: Rebuild.
* Makefile.in (SHLIB_DEP): New variable.
(LIBIBERTY_LISTS, BFD_LIST): New variables.
(stamp-piclist): Depend upon LIBIBERTY_LISTS and BFD_LIST. If
COMMON_SHLIB, add them to piclist with appropriate modifications.
($(SHLIB)): Depend upon $(SHLIB_DEP). Don't check COMMON_SHLIB
here: just use piclist.
* i386-dis.c (onebyte_has_modrm): New static array.
(twobyte_has_modrm): New static array.
(print_insn_i386): Only fetch the mod/reg/rm byte if it is needed.
(reg): Add HX instructions.
start-sanitize-i960xl
The HX instructions are the XL instructions, so this just involves
arranges for them to not be sanitized.
end-sanitize-i960xl
Alan Modra <alan@spri.levels.unisa.edu.au>:
* configure.in: Add AC_ARG_ENABLE for shared and commonbfdlib.
New substitutions: ALLLIBS, PICFLAG, SHLIB, SHLIB_CC,
SHLIB_CFLAGS, COMMON_SHLIB, SHLINK.
* configure: Rebuild.
* Makefile.in (ALLLIBS): New variable.
(PICFLAG, SHLIB, SHLIB_CC, SHLIB_CFLAGS): New variables.
(COMMON_SHLIB, SHLINK): New variables.
(.c.o): If PICFLAG is set, compile twice, once PIC, once normal.
(STAGESTUFF): Remove variable.
(all): Depend upon $(ALLLIBS) rather than $(TARGETLIB).
(stamp-piclist, piclist): New targets.
($(SHLIB), $(SHLINK)): New targets.
($(OFILES)): Depend upon stamp-picdir.
(disassemble.o): Build twice if PICFLAG is set.
(MOSTLYCLEAN): Add pic/*.o.
(clean): Remove $(SHLIB), $(SHLINK), piclist, and stamp-piclist.
(distclean): Remove pic and stamp-picdir.
(install): Install shared libraries.
(stamp-picdir): New target.
If DISASM_RAW_INSN, print insn in hex. Handle v9a as opcode
architecture.
(print_insn_sparc64): Deleted.
* disassemble.c (disassembler, case bfd_arch_sparc): Always use
print_insn_sparc.
* alpha-opc.h (alpha_insn_set): VAX floating point opcode was
incorrectly defined as 0x16 when it should be 0x15.
(FLOAT_FORMAT_MASK): function code is 11 bits, not just 7 bits!
(alpha_insn_set): added cvtst and cvttq float ops. Also added
excb (exception barrier) which is defined in the Alpha
Architecture Handbook version 2.
* alpha-dis.c (print_insn_alpha): Fixed special-case decoding for
OPERATE_FORMAT_CODE type instructions. The bug caused mulq to be
disassembled as or, for example.
