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Author SHA1 Message Date
Richard Henderson
aa9aa96fac * elf32-sparc.c (elf32_sparc_relocate_section): Give a helpful error 
message instead of merely aborting.
        * elf64-sparc.c (sparc64_elf_relocate_section): Likewise.

        * elf64-sparc.c (sparc64_elf_check_relocs): Use SEC_ALLOC to control
        whether we output dynamic relocs instead of SEC_DEBUGGING.
        (sparc64_elf_relocate_section): Likewise.
 1997-10-31 23:53:51 +00:00
Ken Raeburn
aa2e0460a0 * config/tc-mips.c (mips_5400): New variable. 
(md_begin, md_parse_option): Handle 5400 options/names.
(macro_build, mips_ip): Check for 5400-specific instructions.
(md_longopts, OPTION_M5400, OPTION_NO_M5400): More command-line support for
5400.

* config/tc-mips.c (validate_mips_insn): New function, checks match versus mask
bits, and also verifies that all bits to be output are actually specified
somewhere.
(md_begin): Call it for 32-bit instructions, instead of doing match/mask check
here.  In case of failure, print a message, but check the rest of the opcode
table before exiting.
 1997-10-31 23:21:44 +00:00
Andrew Cagney
fcc86d82f7 Make memory regions layered (just like existing device regions) so 
that overlapping regions can be defined.
Allow the layer (level) of a memory region to be specified as part of
an address parameter to memory options.
Update simulators.
 1997-10-31 08:49:10 +00:00
Nick Clifton
d3e9ca1a88 Patches to support generating an executing environment. 
Patches from Tony Thompson at ARM:  athompso@arm.com
 1997-10-30 21:52:16 +00:00
Doug Evans
d048b52dbb * sim-core.h (sim_core_write_8): Define. 1997-10-30 21:45:12 +00:00
Nick Clifton
6e3fcdf01c Fixes to Thumb ADR pseudo op from Tony Thompson at ARM (athompso@arm.com). 1997-10-30 21:44:05 +00:00
Ian Lance Taylor
a8880edadc * ld.h (args_type): Add warn_mismatch field. 
* ldmain.c (main): Initialize warn_mismatch field.
	* lexsup.c (parse_args): Handle --no-warn-mismatch option.
	* ldlang.c (ignore_bfd_error): New static function.
	(lang_check): If warn_mismatch is false, don't warn about
	mismatched input files.
	* ld.texinfo, ld.1: Document new option.
PR 12714.
 1997-10-30 17:28:55 +00:00
Ian Lance Taylor
605ca21a04 add tx49 sanitization 1997-10-30 16:38:29 +00:00
Michael Meissner
42cf65557e Allow odd registers for ld2w and friends 1997-10-30 16:12:36 +00:00
Michael Meissner
b2ef595336 Configure gcc for d30v-*-* 1997-10-30 16:10:52 +00:00
Gavin Romig-Koch
8ed44d1968 * configure.tgt: Add tx49 configury based on 4300. 1997-10-30 02:17:25 +00:00
Gavin Romig-Koch
d649db65ad * config.sub: Add tx49 configury. 1997-10-29 23:01:41 +00:00
Gavin Romig-Koch
d020618aeb * configure.tgt: Add tx49 configury based on 4300. 1997-10-29 22:53:58 +00:00
Gavin Romig-Koch
c7227bdcf7 * include/opcode/mips.h (INSN_4900): Added. 1997-10-29 22:44:29 +00:00
Gavin Romig-Koch
a50b45f379 * include/opcode/mips.h (INSN_4900): Added. 1997-10-29 22:38:20 +00:00
Gavin Romig-Koch
da3636f762 * configure.tgt: Add tx49 configury based on 4300. 1997-10-29 22:38:09 +00:00
Gavin Romig-Koch
4ebda395f1 * config/tc-mips.c (hilo_interlocks): True for tx49. 
(md_begin): Add mips64tx49.
	(md_parse_option): Add 4900 cpu.

	* gas/mips/mips.exp: Add tx49 configury.
 1997-10-29 21:40:09 +00:00
David Taylor
6e2ac3c72d add Solaris 2.6 entry to solib_break_names list -- closes gdb/13689 
change from Casper Dik via Peter Schauer.
 1997-10-29 21:09:51 +00:00
Gavin Romig-Koch
0cca41d47a * mips-opc.c (deret,dmult,dmultu,madd,maddu,pref,sdbbp): 
Add tx49 insns and configury.
 1997-10-29 20:33:43 +00:00
Gavin Romig-Koch
6205f37913 * gencode.c: Add tx49 configury and insns. 
* configure.in: Add tx49 configury.
	* configure: Update.
 1997-10-29 19:42:49 +00:00
Andrew Cagney
01b9cd49ca common/sim-bits.h: Document ROTn macro. 
igen/{igen.c,ld-insns.h}: Document mnemonic string formats.
mips/Makefile.in: Add dependencies for files included by mips.igen
mips/vr5400.igen: checkpoint vr5400 instructions.
 1997-10-29 04:02:30 +00:00
Ken Raeburn
a0539c6102 * mips-opc.c (ffc, ffs): Fix mask. 1997-10-28 23:03:12 +00:00
Michael Meissner
8357d96073 Add eit_vb, int_s, and int_m control registers 1997-10-28 21:36:04 +00:00
Andrew Cagney
89d0973831 Add support for 16 byte quantities to sim-endian macro H2T. 
Add model-filter field to option, include, model anf function igen records
 1997-10-28 07:10:36 +00:00
Ken Raeburn
336ffb472f add a couple more notes to comment 1997-10-28 04:18:25 +00:00
Ken Raeburn
a3066d9ac8 Duh. Check in the vr5400 stuff from the directory that doesn't have 
it sanitized out this time...
 1997-10-28 03:44:27 +00:00
Ken Raeburn
581c03af3e added vr5400 stuff, fixed "not" mask 1997-10-28 03:42:29 +00:00
Ken Raeburn
b410ea2b2b checkpoint vr5400 additions 1997-10-28 03:33:38 +00:00
Andrew Cagney
a86809d323 Implement sim_core_{read,write}_word using sim_core_{read,write}_<N>. 1997-10-28 02:13:09 +00:00
Stan Shebs
4f9cfe69b4 * configure.in: Remove a "second pass" of tweaking noconfigdirs, 
is no longer needed.
Getting the General Magic roaches hiding in the corners...
 1997-10-27 21:20:35 +00:00
Doug Evans
084219a513 * sem-ops.h (U{DIV,MOD}[BHSD]I): Use unsigned division. 1997-10-27 20:45:56 +00:00
Jason Merrill
b0137926d0 * Makefile.in: check-target-libio depends on all-target-libstdc++. 1997-10-27 20:04:58 +00:00
Doug Evans
c3e3e4ad2f * sim-endian.h: Disable 16 byte support. 
So things will build.
 1997-10-27 19:47:24 +00:00
Doug Evans
374b95c1b0 * sim-n-endian.h: Add TAGS entrys for 16 byte versions. 1997-10-27 19:25:59 +00:00
Doug Evans
2fc2f8d8a4 Fix typo. 1997-10-27 19:25:05 +00:00
Andrew Cagney
16bd5d6e52 Separate r5900 specifoc and mips16 instructions. 
Add support for this to configure (vr5400 target only)
 1997-10-27 07:55:24 +00:00
Andrew Cagney
90ad43b2de Add mips64vr5400 to configuration list 
Mark mipsIV instructions as being implemented by the vr5400.
Sanitize.
 1997-10-27 06:42:13 +00:00
Andrew Cagney
e2880fadf3 Add include-file support to igen. 1997-10-27 06:30:35 +00:00
Andrew Cagney
f45dd42b32 Add 128 bit transfers to sim core. 1997-10-27 03:00:12 +00:00
Gavin Romig-Koch
635ae9cb7c * sim/mips/gencode.c (build_instruction): Follow sim_write's lead in using 
BigEndianMem instead of !ByteSwapMem.
 1997-10-25 20:53:46 +00:00
Andrew Cagney
b5da31ac7c Correct name of file given in ChangeLog for change: Pass lma_p and 
sim_write args to sim_load_file.
 1997-10-25 05:04:25 +00:00
Ian Lance Taylor
e59390a7eb * config/tc-ppc.c (md_assemble): When handling @l, always sign 
extend if the operand expects a signed value.
PR 13667.
 1997-10-24 21:29:10 +00:00
David Taylor
022278948f fix for PR 13618 -- gdb incorrectly reports thread information. 
If other systems besides nm-sun4sol2 exhibit the problem, they may need
definitions of FIND_NEW_THREADS and a corresponding support function.
 1997-10-24 21:04:39 +00:00
Ian Lance Taylor
c14d0cc015 * config/tc-mips.h (LOCAL_LABELS_DOLLAR): Don't define; use 
default which is to permit dollar labels.
PR 13645.
 1997-10-24 20:03:16 +00:00
Richard Henderson
1bb6aaad34 Fri Oct 24 11:19:22 1997 Jakub Jelinek <jj@sunsite.mff.cuni.cz> 
* config/tc-sparc.c (sparc_memory_model): New variable.
        (md_longopts): Add -TSO/-PSO/-RMO options.
        (md_parse_options): Handle them.
        (sparc_elf_final_processing): For 64 ELF, set required
        memory ordering in e_flags. Default to RMO and let the user
        override it through command line.

        * config/tc-sparc.h (elf_tc_final_processing): Add.
 1997-10-24 18:20:36 +00:00
Richard Henderson
ccbab31db1 Fri Oct 24 11:15:58 1997 Jakub Jelinek <jj@sunsite.mff.cuni.cz> 
* elf64-sparc.c (sparc64_elf_merge_private_bfd_data):
        New function. Avoid mixing US1 and HAL R1 code.
        Set resulting memory ordering to the strongest one used.
        (sparc64_elf_object_p): Set bfd_mach correctly.
 1997-10-24 18:14:52 +00:00
Ian Lance Taylor
6b29430fa3 sanitize for vr5400 1997-10-24 16:39:38 +00:00
Ian Lance Taylor
ae295afea4 add sparclinux.h 1997-10-24 16:03:57 +00:00
Andrew Cagney
122edc03de Add basic igen configuration to autoconf. Disable. 1997-10-24 07:54:21 +00:00
Andrew Cagney
dad6f1f326 Add function to fetch 32bit instructions 
When address translation of insn fetch fails raise exception immediatly.
Use address_word as type of all address variables (instead of unsigned64),
the former is configured as either 32 or 64 bit type.
Always compile fpu code (no #if has fpu)
 1997-10-24 06:43:51 +00:00