defaults for defined, private, and spnum fields for the
$TEXT$ and $PRIVATE$ spaces. Do not clobber spnum. Do
not reset the segment if just updating a space.
(pa_spaces_begin): Set BFD section flags for all built-in
subspaces.
* configure.in: Set ALL_OBJ_DEPS in output Makefile.
Based on suggestions from <BAILEY@hmivax.humgen.upenn.edu> (Charles Bailey):
* vmsconf.sh: In generated file, get ".obj" suffix right, build source files
from other directories into objects in the current directory, and specify PSECT
attributes explicitly to linker. Also added missing label.
* Makefile.in (stamp-mk.com): Reference new variable VMS_OTHER_OBJS for list of
non-local object files, instead of listing them here.
(VMS_OTHER_OBJS): New variable, added more libiberty files.
* make-gas.com: Regenerated.
* config/ho-vms.h (unlink): Define as delete.
* config-gas.com: Fix quoting on TARGET_CANONICAL definition. Delete files
before creating them.
* config/tc-mips.c (macro_build): Permit BFD_RELOC_PCREL_LO16 for
certain cases of 'i', 'j' and 'o'. Change 'u' to take an
argument, the reloc type.
(load_register): Pass reloc type to macro_build for 'u'.
(macro): Likewise. For M_LA_AB permit a difference expression
when generating embedded PIC code between an arbitrary symbol and
a symbol in the .text section.
(mips_force_relocation): Force BFD_RELOC_PCREL_HI16_S and
BFD_RELOC_PCREL_LO16 to be emitted.
(md_apply_fix): Check that most relocs are not PC relative.
Handle BFD_RELOC_PCREL_HI16_S and BFD_RELOC_PCREL_LO16.
(tc_gen_reloc): Change #error to as_fatal. Handle
BFD_RELOC_PCREL_LO16 and BFD_RELOC_PCREL_HI16_S.
macro_build for nori case.
(SWITCH_TABLE): Define.
(mips_force_relocation): Force a relocation for a switch table
entry.
(md_apply_fix): Write switch table entry value into file.
(tc_gen_reloc): Use BFD_RELOC_GPREL32 for a switch table entry,
and set the addend to the difference between the reloc address and
the subtrahend.
(elf_tc_make_sections): Likewise.
(hppa_tc_make_sections, hppa_tc_symbol): Delete extern decls.
* config/tc-hppa.c (hppa_tc_make_sections): Delete function.
(hppa_tc_symbol): Likewise.
* config/obj-elf.c (elf_frob_file): Delete elf_tc_symbol and
elf_tc_make_sections stuff. It was there to support PA braindamage
which has been fixed, and in the case of elf_tc_make_sections is
redundant with elf_tc_final_processing.
embedded PIC code, accept the difference between two local symbols
as being constant.
(mips_force_relocation): Only force a reloc to be generated for a
PC relative fixup.
(md_apply_fix): For BFD_RELOC_32 and BFD_RELOC_LO16, put the fixup
value into the file if the fixup will not generate a reloc.
(ppc_arch): Check for PPC_OPCODE_PPC before PPC_OPCODE_POWER.
(md_begin): If an instruction has a size specific flag set, only
add it if we are assembling that size.
branch with an instruction that uses $at, in case the branch is
later expanded.
(macro): If EMBEDDED_PIC, case M_JAL_A may use $at.
(md_pcrel_from): If not OBJ_AOUT, return 4 for an undefined symbol
to make it pcrel_offset.
(tc_gen_reloc): If not OBJ_AOUT, set the reloc addend to
reloc->address; another gruesome hack to get gas reloc handling to
do the right thing.
(mips_pic): Change from int to enum mips_pic_level. Change all
uses (0 becomes NO_PIC, 2 becomes SVR4_PIC).
(load_address): Handle EMBEDDED_PIC.
(macro): Handle EMBEDDED_PIC in all PIC cases.
(md_parse_option): Accept -membedded-pic to use EMBEDDED_PIC. If
OBJ_ELF, accept -KPIC and -call_shared to use SVR4_PIC and accept
-non_shared to use NO_PIC (this is how the Irix 5 assembler
works). Do not permit -G with SVR4_PIC.
(s_abicalls): Warn if -G was used, and force -G 0.
(tc_gen_reloc): Set reloc->addend to 0 for a PC relative reloc for
anything but a.out, not just for ELF. For ECOFF, don't generate a
BFD_RELOC_16_PCREL_S2 reloc unless using EMBEDDED_PIC.
with S_GET_VALUE. Skip debug symbols to avoid "a really nasty bug". (From
Holger Teutsch, holger@botbso.rhein-main.de.)
(VMS_write_object_file): For "__vt.*" symbols, set S_GET_OTHER field. (Also
from Holger Teutsch.) Watch for a would-be register mask that spans frags.
* config/alpha-opcode.h (ldif, ldig, ldis, ldit): New patterns.
* config/tc-alpha.c (lit8_sec, lit4_sec, lit8_sym, lit4_sym): New variables.
(create_literal_section): New function.
(create_lita_section): Now a macro.
(get_lit8_offset, get_lit4_offset): New functions.
(maybe_set_gp): New function.
(select_gp_value): Call it.
(load_expression): Preserve addend if symbol is a section symbol.
(alpha_ip): Handle new operand type `F' for floating-point constants; store
them in .lit{4,8} sections.
(alpha_ip, case 'G'): Emit LITUSE relocations for symbol exprs.
(obj_coff_section): Declare.
(obj_pseudo_table): Make it available only if MANY_SECTIONS.
(obj_symbol_to_chars) [CROSS_COMPILE]: Some attemps to make this work. It
still doesn't. It now fails to compile, instead of silently compiling to do
nothing.
* config/obj-coff.h (SEPARATE_STAB_SECTIONS): Define only if MANY_SECTIONS.
(OBJ_PROCESS_STAB) [! MANY_SECTIONS]: New macro, just emits a warning.
ic960coff.
* config/ic960coff.mt: New file.
* config/obj-coffbfd.h [TC_I960]: Include coff/i960.h.
(TARGET_FORMAT) [TC_I960]: Use coff-Intel-little.
* config/te-ic960.h (CROSS_COMPILE): Don't undef this. We'll always build
little-endian object files.
* config/tc-i960.c (md_reloc_size): Don't define at all if BFD or
BFD_ASSEMBLER is defined.
(mem_fmt): Since COFF doesn't handle callx relocations yet, treat them like
normal 32-bit relocations.
(md_apply_fix): For callx relocations, store zero.
(tc_bout_fix_to_chars): Store symbol idx for all callx relocations, regardless
of link-relax setting.
(tc_coff_fix2rtype, tc_coff_sizemachdep): New functions.
(i960_handle_align) [! OBJ_BOUT]: If link-relax option is selected, print an
error message and clear it.
* config/tc-i960.h (BFD_ARCH, COFF_FLAGS, COFF_MAGIC, TC_COUNT_RELOC,
TC_COFF_FIX2RTYPE, TC_COFF_SIZEMACHDEP, tc_fix_adjustable): New macros.
(tc_coff_fix2rtype, tc_coff_sizemachdep): Declare.
