2004-11-23 Jan Beulich <jbeulich@novell.com>
* config/tc-i386.h (CpuMMX2): Declare. Artificial classifier to
indicate the MMX extensions added by both SSE and 3DNow!A.
(Cpu3dnowA): Declare.
(CpuUnknownFlags): Update.
* config/tc-i386.c (cpu_sub_arch_name): Declare.
(cpu_arch): i586 and pentium do not imply MMX. i686 and pentiumpro do
neither imply SSE nor MMX. k6 implies MMX. k6_2 additionally implies
3DNow!. Athlon additionally implies 3DNow!A. Several new
entries (those starting with a dot are for sub-arch specification).
(set_cpu_arch): Handle sub-arch specifications.
(parse_insn): Distinguish between instructions not supported because
of insufficient CPU features and because of 64-bit mode.
* doc/c-i386.texi: Describe enhanced .arch directive.
include/opcode/
2004-11-23 Jan Beulich <jbeulich@novell.com>
* i386.h (i386_optab): paddq and psubq, even in their MMX form, are
available only with SSE2. Change the MMX additions introduced by SSE
and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
instructions by their now designated identifier (since combining i686
and 3DNow! does not really imply 3DNow!A).
2004-11-04 Jan Beulich <jbeulich@novell.com>
* config/tc-i386.c (set_intel_syntax): Allow % in symbol names when
intel syntax and no register prefix, allow $ in symbol names when
intel syntax.
(set_16bit_gcc_code_flag): Replace literal 'l' by LONG_MNEM_SUFFIX.
(intel_float_operand): Add fourth return value indicating math control
operations. Make classification more precise.
(md_assemble): Complain if memory operand of mov[sz]x has no size
specified.
(parse_insn): Translate word operands to floating point instructions
operating on integers as well as control instructions to short ones
as expected by AT&T syntax. Translate 'd' suffix to short one only for
floating point instructions operating on non-integer operands.
(match_template): Remove fldcw special case. Adjust q-suffix handling
to permit it on fild/fistp/fisttp in AT&T mode.
(process_suffix): Don't guess DefaultSize insns' suffix from
stackop_size for certain floating point control instructions. Guess
suffix for branch and [ls][gi]dt based on flag_code. Split error
messages for Intel and AT&T syntax, and make the condition more strict
for the former. Adjust suppressing of generation of operand size
overrides.
(intel parser): Allow the full set of MASM operators. Add FWORD, TBYTE,
OWORD, and XMMWORD operand size specifiers (TBYTE replaces XWORD). Add
more error checking.
* config/tc-i386.h (BYTE_PTR WORD_PTR DWORD_PTR QWORD_PTR XWORD_PTR
SHORT OFFSET_FLAT FLAT NONE_FOUND): Remove unused defines.
gas/testsuite/
2004-11-04 Jan Beulich <jbeulich@novell.com>
* gas/i386/i386.exp: Execute new tests intelbad and intelok.
* gas/i386/intelbad.[sl]: New test to check for various things not
permitted in Intel mode.
* gas/i386/intel.d, gas/i386/opcode.d, gas/i386/x86-64-opcode.d:
Adjust for change to segment register store.
* gas/i386/intelok.[sd]: New test to check various Intel mode specific
things get handled correctly.
* gas/i386/x86_64.[sd]: Remove unsupported constructs referring to
'high' and 'low' parts of an operand, which the parser previously
accepted while neither telling that it's not supported nor that it
ignored the remainder of the line following these supposed keywords.
include/opcode/
2004-11-04 Jan Beulich <jbeulich@novell.com>
* i386.h (sldx_Suf): Remove.
(FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
(q_FP): Define, implying no REX64.
(x_FP, sl_FP): Imply FloatMF.
(i386_optab): Split reg and mem forms of moving from segment registers
so that the memory forms can ignore the 16-/32-bit operand size
distinction. Adjust a few others for Intel mode. Remove *FP uses from
all non-floating-point instructions. Unite 32- and 64-bit forms of
movsx, movzx, and movd. Adjust floating point operations for the above
changes to the *FP macros. Add DefaultSize to floating point control
insns operating on larger memory ranges. Remove left over comments
hinting at certain insns being Intel-syntax ones where the ones
actually meant are already gone.
opcodes/
2004-11-04 Jan Beulich <jbeulich@novell.com>
* i386-dis.c (Eq, Edqw, indirEp, Gdq, I1): Define.
(indirEb): Remove.
(Mp): Use f_mode rather than none at all.
(t_mode, dq_mode, dqw_mode, f_mode, const_1_mode): Define. t_mode
replaces what previously was x_mode; x_mode now means 128-bit SSE
operands.
(dis386): Make far jumps and calls have an 'l' prefix only in AT&T
mode. movmskpX's, pextrw's, and pmovmskb's first operands are Gdq.
pinsrw's second operand is Edqw.
(grps): 1-bit shifts' and rotates' second operands are I1. cmpxchg8b's
operand is Eq. movntq's and movntdq's first operands are EM. s[gi]dt,
fldenv, frstor, fsave, fstenv all should also have suffixes in Intel
mode when an operand size override is present or always suffixing.
More instructions will need to be added to this group.
(putop): Handle new macro chars 'C' (short/long suffix selector),
'I' (Intel mode override for following macro char), and 'J' (for
adding the 'l' prefix to far branches in AT&T mode). When an
alternative was specified in the template, honor macro character when
specified for Intel mode.
(OP_E): Handle new *_mode values. Correct pointer specifications for
memory operands. Consolidate output of index register.
(OP_G): Handle new *_mode values.
(OP_I): Handle const_1_mode.
(OP_ESreg, OP_DSreg): Generate pointer specifications. Indicate
respective opcode prefix bits have been consumed.
(OP_EM, OP_EX): Provide some default handling for generating pointer
specifications.
* config.bfd: Include 64-bit support for i[3-7]86-*-solaris2*.
* elf64-x86-64.c (elf64_x86_64_section_from_shdr): New function.
(elf_backend_section_from_shdr): Define.
binutils/
* readelf.c (get_x86_64_section_type_name): New function.
(get_section_type_name): Use it.
gas/
* config/tc-i386.c: Include "elf/x86-64.h".
(i386_elf_section_type): New function.
* config/tc-i386.h (md_elf_section_type): Define.
(i386_elf_section_type): New prototype.
gas/testsuite/
* gas/i386/i386.exp: Don't run divide test for targets where '/'
is a comment. Run x86-64-unwind for 64-bit ELF targets.
* gas/i386/x86-64-unwind.d, gas/i386/x86-64-unwind.s: New.
include/
* elf/common.h (PT_SUNW_EH_FRAME): Define.
* elf/x86-64.h (SHT_X86_64_UNWIND): Define.
ld/
* configure.tgt: Include elf_x86_64 for i[3-7]86-*-solaris2*.
* bfd/cofflink.c (_bfd_coff_generic_relocate_section): Resolve PE weak
externals properly.
* src/gas/config/obj-coff.c (obj_coff_weak): New .weak syntax for PE weak
externals.
* binutils/doc/binutils.texi (nm): Clarify weak symbol description.
* gas/config/tc-i386.c (tc_gen_reloc): Use addend for weak symbols in TE_PE.
* gas/doc/as.texinfo (Weak): Document PE weak symbols.
* ld/ld.texinfo (WIN32): Document PE weak symbols.
2003-06-23 H.J. Lu <hongjiu.lu@intel.com>
* gas/config/tc-i386.c (md_assemble): Support Intel Precott New
Instructions.
* gas/config/tc-i386.h (CpuPNI): New.
(CpuUnknownFlags): Add CpuPNI.
gas/testsuite/
2003-06-23 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/i386.exp: Add prescott.
* gas/i386/prescott.d: New file.
* gas/i386/prescott.s: Likewise.
include/opcode/
2003-06-23 H.J. Lu <hongjiu.lu@intel.com>
* i386.h (i386_optab): Support Intel Precott New Instructions.
opcodes/
2003-06-23 H.J. Lu <hongjiu.lu@intel.com>
* i386-dis.c (PNI_Fixup): New. Fix up "mwait" and "monitor" in
Intel Precott New Instructions.
(PREGRP27): New. Added for "addsubpd" and "addsubps".
(PREGRP28): New. Added for "haddpd" and "haddps".
(PREGRP29): New. Added for "hsubpd" and "hsubps".
(PREGRP30): New. Added for "movsldup" and "movddup".
(PREGRP31): New. Added for "movshdup" and "movhpd".
(PREGRP32): New. Added for "lddqu".
(dis386_twobyte): Use PREGRP30 to replace the "movlpX" entry.
Use PREGRP31 to replace the "movhpX" entry. Use PREGRP28 for
entry 0x7c. Use PREGRP29 for entry 0x7d. Use PREGRP27 for
entry 0xd0. Use PREGRP32 for entry 0xf0.
(twobyte_has_modrm): Updated.
(twobyte_uses_SSE_prefix): Likewise.
(grps): Use PNI_Fixup in the "sidtQ" entry.
(prefix_user_table): Add PREGRP27, PREGRP28, PREGRP29, PREGRP30,
PREGRP31 and PREGRP32.
(float_mem): Use "fisttp{l||l|}" in entry 1 in opcode 0xdb.
Use "fisttpll" in entry 1 in opcode 0xdd.
Use "fisttp" in entry 1 in opcode 0xdf.
* NEWS: Updated for the new -n option for the i386 assembler.
* config/tc-i386.c (optimize_align_code): New.
(md_shortopts): Add 'n'.
(md_parse_option): Handle 'n'.
(md_show_usage): Add '-n'.
* config/tc-i386.h (optimize_align_code): Declared.
(md_do_align): Optimize code alignment only if optimize_align_code
is not 0.
* doc/as.texinfo: Add the new -n option.
* doc/c-i386.texi: Document the new -n option.
* reloc.c (BFD_RELOC_386_TLS_TPOFF, BFD_RELOC_386_TLS_IE,
BFD_RELOC_386_TLS_GOTIE): Add.
* bfd-in2.h, libbfd.h: Rebuilt.
* elf32-i386.c (elf_howto_table): Add R_386_TLS_TPOFF, R_386_TLS_IE
and R_386_TLS_GOTIE.
(elf_i386_reloc_type_lookup): Handle it.
(struct elf_i386_link_hash_entry): Change tls_type type to unsigned
char instead of enum, change GOT_* into defines.
(GOT_TLS_IE_POS, GOT_TLS_IE_NEG, GOT_TLS_IE_BOTH): Define.
(elf_i386_tls_transition): Handle R_386_TLS_IE and R_386_TLS_GOTIE.
(elf_i386_check_relocs): Likewise. Avoid crash if local symbol is
accessed both as normal and TLS symbol. Move R_386_TLS_LDM and
R_386_PLT32 cases so that R_386_TLS_IE can fall through.
Handle R_386_TLS_LE_32 and R_386_TLS_LE in shared libs.
(elf_i386_gc_sweep_hook): Handle R_386_TLS_IE and R_386_TLS_GOTIE.
Handle R_386_TLS_LE_32 and R_386_TLS_LE in shared libs.
(allocate_dynrelocs): Allocate 2 .got and 2 .rel.got entries if
tls_type is GOT_TLS_IE_BOTH.
(elf_i386_size_dynamic_sections): Likewise.
(elf_i386_relocate_section): Handle R_386_TLS_IE and R_386_TLS_GOTIE.
Handle R_386_TLS_LE_32 and R_386_TLS_LE in shared libs.
(elf_i386_finish_dynamic_symbol): Use tls_type & GOT_TLS_IE to catch
all 4 GOT_TLS_* TLS types.
gas/
* config/tc-i386.c (tc_i386_fix_adjustable): Handle
BFD_RELOC_386_TLS_IE and BFD_RELOC_386_TLS_GOTIE.
(BFD_RELOC_386_TLS_IE, BFD_RELOC_386_TLS_GOTIE): Define to 0
if not defined.
(lex_got): Handle @GOTNTPOFF and @INDNTPOFF.
(md_apply_fix3, tc_gen_reloc): Handle BFD_RELOC_386_TLS_IE and
BFD_RELOC_386_TLS_GOTIE.
gas/testsuite/
* gas/i386/tlspic.s: Add tests.
* gas/i386/tlspic.d: Regenerated.
* gas/i386/tlsnopic.s: Add tests.
* gas/i386/tlsnopic.d: Regenerated.
include/
* elf/i386.h (R_386_TLS_TPOFF, R_386_TLS_IE, R_386_TLS_GOTIE):
Define.
ld/testsuite/
* ld-i386/i386.exp: New.
* ld-i386/tlsbin.dd: New test.
* ld-i386/tlsbinpic.s: New test.
* ld-i386/tlsbin.rd: New test.
* ld-i386/tlsbin.s: New test.
* ld-i386/tlsbin.sd: New test.
* ld-i386/tlsbin.td: New test.
* ld-i386/tlslib.s: New test.
* ld-i386/tlsnopic1.s: New test.
* ld-i386/tlsnopic2.s: New test.
* ld-i386/tlsnopic.dd: New test.
* ld-i386/tlsnopic.rd: New test.
* ld-i386/tlsnopic.sd: New test.
* ld-i386/tlspic1.s: New test.
* ld-i386/tlspic2.s: New test.
* ld-i386/tlspic.dd: New test.
* ld-i386/tlspic.rd: New test.
* ld-i386/tlspic.sd: New test.
* ld-i386/tlspic.td: New test.
* elf32-i386.c: Don't defined ELF_ARCH etc. if this file is included
by a target variant implementation.
* elf64-alpha.c: Likewise.
* elf32-i386-fbsd.c: New file.
* elf64-alpha-fbsd.c: New file.
* targets.c: Support bfd_elf32_i386_freebsd_vec and
bfd_elf64_alpha_freebsd_vec.
* configure.in: Accept the vectors bfd_elf32_i386_freebsd_vec,
bfd_elf64_alpha_freebsd_vec.
* Makefile.am (BFD32_BACKENDS): Add elf32-i386-fbsd.lo.
(BFD32_BACKENDS_CFILES): Add elf32-i386-fbsd.c.
(BFD64_BACKENDS): Add elf64-alpha-fbsd.lo.
(BFD64_BACKENDS_CFILES): Add elf64-alpha-fbsd.c.
(elf32-i386-fbsd.lo, elf64-alpha-fbsd.lo): Add dependencies.
* config.bfd: For FreeBSD targets, set targ_defvec to a FreeBSD
specific targets. Define OLD_FREEBSD_ABI_LABEL if appropriate.
* config/tc-i386.h (ELF_TARGET_FORMAT): New macro.
(TARGET_FORMAT): Use ELF_TARGET_FORMAT instead of "elf32-i386".
* config/tc-i386.c (i386_target_format): Likewise.
* config/tc-alpha.h (ELF_TARGET_FORMAT): New macro.
(TARGET_FORMAT): Use ELF_TARGET_FORMAT instead of "elf64-alpha".
* emulparams/elf_i386_fbsd.sh: Set OUTPUT_FORMAT to
elf32-i386-freebsd.
* emulparams/elf64alpha_fbsd.sh: Set OUTPUT_FORMAT to
elf64-alpha-freebsd.
Approved by: Alan Modra <amodra@bigpond.net.au>
Message-ID: <20020715021113.GJ30362@bubble.sa.bigpond.net.au>
for ELF, and don't bother checking ELF relocs when non-ELF.
(i386_immediate): Allow absolute_section expressions for aout.
(i386_displacement): Likewise. Also test bfd_is_com_section.
(md_estimate_size_before_relax): Test OUTPUT_FLAVOR for ELF.
(md_apply_fix3): Hack for bfd_install_relocation when fx_pcrel,
not when fx_addsy. Remove dead code.
at start of insn, pass it to output_disp and output_imm.
(output_disp): Added arguments. If _GLOBAL_OFFSET_TABLE_ is seen
in displacement for R_386_32 reloc, use R_386_GOTPC and compute
properly addend.
(output_imm): Added arguments. Compute properly addend for
R_386_GOTPC.
(md_apply_fix3): Remove R_386_GOTPC handling.
* testsuite/gas/i386/gotpc.s: New.
* testsuite/gas/i386/gotpc.d: New.
* testsuite/gas/i386/i386.exp: Add gotpc test.
(md_estimate_size_before_relax): Don't set fx_pcrel_adjust any
more.
(md_apply_fix3): Remember addend value for rela relocations.
(tc_gen_reloc): Correctly compute pc-relative relocation addend.
field for pc-relative fixups.
(output_disp): Likewise.
(md_estimate_size_before_relax): Likewise.
(tc_gen_reloc): Subtract fx_pcrel_adjust instead of fx_size for
pc-relative fixups in 64bit mode.
relocs except when BFD64.
* write.c (number_to_chars_bigendian): Don't abort when N is
larger than sizeof (VAL).
(number_to_chars_littleendian): Likewise.
and rearrange for efficiency. For "PIC code" subtraction, use
"rightseg" rather than recalculating. For "symbol OP symbol"
subtract, set "retval" to absolute_section if symbols in same
section.
* symbols.c (resolve_symbol_value): Resolve "sym +/- expr" to an
O_symbol. Simplify a +/- b code. Allow equality and non-equality
comparisons on symbols from any section. Allow other comparison
operators as for subtraction.
(symbol_equated_reloc_p): New predicate function.
* symbols.h (symbol_equated_reloc_p): Declare.
* write.c (adjust_reloc_syms): Use symbol_equated_reloc_p.
(write_relocs): Likewise.
(write_object_file): Likewise.
(relax_segment <rs_machine_dependent>): Ensure segment for
expression syms is set correctly.
* config/tc-mips.c (md_estimate_size_before_relax): Likewise.
* config/tc-i386.c (md_assemble <Output jumps>): Don't lose part
of a complex expression when setting up frag_var.
(md_apply_fix): Use it here. Replace printf with equivalent
as_bad_where.
(tc_gen_reloc): Use as_bad_where instead of as_bad.
(md_apply_fix): Here too.
* config/tc-i386.c (tc_gen_reloc): Use as_bad_where instead of as_bad.
* config/tc-m68k.c (tc_gen_reloc): Likewise.
(md_convert_frag_1): Likewise.
(md_assemble [smallest displacement]): Use correct field of i.op[] union.
(md_assemble [JumpInterSegment output]): Use correct i.disp_reloc[].
(md_assemble [immediate output]): Likewise.
* config/tc-i386.c (tc_gen_reloc): Remove ugly hack which is not needed
anymore since we use bfd_elf_generic_reloc now.
(md_apply_fix3): Only apply hack for partial_inplace if not using RELA.
instruction sequence consisting of a conditional jump of the
opposite sense around an unconditional jump to the target.
Add jumps/nojumps .arch modifier.
* tc-i386.c (md_assemble): Return after the error message;
move testing for 64bit operands to proper place.
* i386.exp: Add tests for presence of 32bit versus 64bit output
format; run both 64bit and 32bit tests when format is available;
add x86_64 test.
* x86_64.s: New file.
* x86_64.d: New file.
(QWORD_MNEM_SUFFIX): New macro.
(CpuK6,CpuAthlon,CpuSledgehammer, Cpu64, CpuNo64, CpuUnknownFlags):
New macros
(CpuMMX,CpuSSE,Cpu3dnow, CpuUnknown): Renumber.
(IgnoreSize, DefaultSize, No_?Suf, FWait, IsString, regKludge, IsPrefix,
ImmExt): Renumber.
(Size64, No_qSuf, NoRex64, Rex64): New macros.
(Reg64, Imm32S, Imm64, Disp32S, Disp64): New macros.
(Imm8, Imm8S, Imm16, Imm32, Imm1, BaseIndex, Disp8, Disp16, Disp32,
InOutPortReg,ShiftCount, Control, Debug, Test, FloatReg, FloatAcc,
SReg2, SReg3, Acc, JumpAbsolute, RegMMX, RegXMM, EsSeg, InvMem): Renumber.
(Reg, WordReg): Add Reg64.
(Imm): Add Imm32S and Imm64.
(EncImm): New.
(Disp): Add Disp64 and Disp32S.
(AnyMem): Add Disp32S.
(RegRex, RegRex64): New macros.
(rex_byte): New type.
* tc-i386.c (set_16bit_code_flag): Kill.
(fits_in_unsigned_long, fits_in_signed_long): New functions.
(reloc): New parameter "signed"; support x86_64.
(set_code_flag): New.
(DEFAULT_ARCH): New macro; default to "i386".
(default_arch): New static variable.
(struct _i386_insn): New fields Operand_PCrel; rex.
(flag_16bit_code): Kill; All tests replaced to "flag_code == CODE_64BIT";
(flag_code): New enum and static variable.
(use_rela_relocations): New static variable.
(flag_code_names): New static variable.
(cpu_arch_flags): Default to CpuUnknownFlags|CpuNo64.
(cpu_arch): Add "sledgehammer"; Add CPUAthlon to Athlon and CpuK6 to
K6 and Athlon.
(i386_align_code): Return plain "nop" for x86_64.
(mode_from_disp_size): Support Disp32S.
(smallest_imm_type): Support Imm32S and Imm64.
(offset_in_range): Support size of 8.
(set_cpu_arch): Do not clobber to Cpu64/CpuNo64.
(md_pseudo_table): Add "code64"; use set_code_flat.
(md_begin): Emit sane error message on hash failure.
(tc_i386_fix_adjustable): Support x86_64 relocations.
(md_assemble): Support QWORD_MNEM_SUFFIX, REX registers,
instructions supported on particular arch just partially,
output of 64bit immediates, handling of Imm32S and Disp32S type.
(i386_immedaite): Support x86_64 relocations; support 64bit constants.
(i386_displacement): Likewise.
(i386_index_check): Cleanup; support 64bit addresses.
(md_apply_fix3): Support x86_64 relocation and rela.
(md_longopts): Add "32" and "64".
(md_parse_option): Add OPTION_32 and OPTION_64.
(i386_target_format): Call even for ELFs; choose between
elf64-x86-64 and elf32-i386.
(i386_validate_fix): Refuse GOTOFF in 64bit mode.
(tc_gen_reloc): Support rela relocations and x86_64.
(intel_e09_1): Support QWORD.
* i386.h (i386_optab): Replace "Imm" with "EncImm".
(i386_regtab): Add flags field.
* config/tc-i386.c (intel_e09_1): Only flag as a memory operand if
it's not an offset expression.
(intel_e10_1): Ditto. Also, if the operand is an offset expression,
keep the braces '[' and ']' in the output string.
(intel_e11): Ditto. Also remove comparison intel_parser.op_modifier
!= FLAT. There is no such op_modifier.
* tc-i386.c (md_assemble): Swap i.disp_relocs when using intel
syntax.
2000-11-30 Diego Novillo <dnovillo@redhat.com>
* intel.s, intel.d: New test for @GOT references.
* tc-i386.c (i386_operand_modifier): Remove.
(build_displacement_string): Remove.
(i386_parse_seg): Remove.
(i386_intel_memory_operand): Remove.
(i386_intel_operand): Re-write using recursive descent parser based
on MASM documentation.
(struct intel_parser_s): New structure.
(intel_parser): New static variable.
(struct intel_token): New structure.
(cur_token, prev_token): New static variables.
(T_NIL): Define.
(T_CONST): Define.
(T_REG): Define.
(T_BYTE): Define.
(T_WORD): Define.
(T_DWORD): Define.
(T_QWORD): Define.
(T_XWORD): Define.
(T_SHORT): Define.
(T_OFFSET): Define.
(T_PTR): Define.
(T_ID): Define.
(intel_match_token): New function.
(intel_get_token): New function.
(intel_putback_token): New function.
(intel_expr): New function.
(intel_e05): New function.
(intel_e05_1): New function.
(intel_e06): New function.
(intel_e06_1): New function.
(intel_e09): New function.
(intel_e09_1): New function.
(intel_e10): New function.
(intel_e10_1): New function.
(intel_e11): New function.
2000-10-24 Diego Novillo <dnovillo@cygnus.com>
* intel.s, intel.d: Add new tests for intel syntax.
2000-10-15 Diego Novillo <dnovillo@cygnus.com>
* config/tc-i386.c (i386_operand_modifier): Only match
modifiers SHORT and FLAT if they are followed by a space.
(parse_register): When `allow_naked_reg' is set, do not confuse
identifiers that start with a register name with a register.
gas/testsuite:
2000-10-15 Diego Novillo <dnovillo@cygnus.com>
* intel.s, intel.d: Add new tests for naked registers using intel
syntax.
the errors exposed by this addition. These were intel mode
"fi... word ptr", "fi... dword ptr", "jmp Imm seg, Imm offset", "out dx,al".
The failure with intel "out dx,al" was also present in att "out al,dx".
Extend testsuite to catch this case too.
assembler. ie. You will be able to do "as --em=i386aout" on an x86
linux-elf assembler to generate aout format object files, rather than
using a separate assembler. The aout emulation is enabled by giving
"--enable-targets=i386-linuxaout" to configure.
Oh yeah, there's a couple of fixes too. Error messages shouldn't be
passed to printf in the format arg just in case someone puts a `%' in
the message.
* config/tc-i386.c (md_shortopts): Check OBJ_MAYBE_ELF as well as
OBJ_ELF. If ELF, add "sq".
(md_parse_option): If ELF, ignore -s and -q.
(md_show_usage): Mention ELF options.
* config/atof-ieee.c (atof_ieee): Change what_kind to int.
* config/atof-vax.c (flonum_gen2vax): Change format_letter to
int.
(md_atof): Return NULL rather than 0.
* config/tc-i386.c (md_atof): Change type to int.
next_set_end even if the end symbol is being discarded.
* gasp.c: Add ATTRIBUTE_UNUSED as needed for non-BFD_ASSEMBLER.
* output-file.c, symbols.c, config/tc-i386.c: Likewise.
* config/obj-coff.c: Likewise.
(seg_info_type): Remove.
(seg_info_off_by_4): Change to array of segT.
(s_get_segment): Adjust accordingly.
(obj_pseudo_table): Fully initialize sentinel entry.
as appropriate. Fill in structure initializations. Add variable
initializations. Add casts.
* dwarf2dbg.c (print_stats): Change i to size_t.
* listing.c (listing_listing): Change list_line to unsigned int.
Move bitfield overflow checks to after the md_apply_fix call in
fixup_segment so that md_apply_fix has a chance to modify value.
Handle 8 and 16-bit pcrel relocs for i386.
Prototypes and other minor code cleanups.
