* config/tc-s390.c (md_begin): Only add to hash table if cpu and
mode mask fit.
2010-10-28 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
* s390-opc.txt: cfxr, cfdr and cfer z900 -> g5.
2010-10-25 H.J. Lu <hongjiu.lu@intel.com>
PR gas/12049
* gas/i386/i386.exp: Run relax-1 and relax-2 for all 32bit
targets. Run x86-64-relax-1.
* gas/i386/x86-64-relax-1.d: New.
* gas/i386/x86-64-relax-1.s: Likewise.
defined/declared (as appropriate) at the end of assembly, based
on the presence or not of the "forward" symbol.
* gas/mips/ld-forward.d: New test.
* gas/mips/mips1@ld-forward.d: Likewise. MIPS I version.
* gas/mips/r3000@ld-forward.d: Likewise, R3000 version.
* gas/mips/ecoff@ld-forward.d: Likewise, ECOFF version.
* gas/mips/r3900@ecoff@ld-forward.d: Likewise, R3900/ECOFF
version.
* gas/mips/mips2@ecoff@ld-forward.d: Likewise, MIPS II/ECOFF
version.
* gas/mips/mips32@ecoff@ld-forward.d: Likewise, MIPS32/ECOFF
version.
* gas/mips/mips32r2@ecoff@ld-forward.d: Likewise, MIPS32r2/ECOFF
version.
* gas/mips/ld-n32-forward.d: New test.
* gas/mips/ld-n64-forward.d: Likewise.
* gas/mips/mips.exp: Run the new tests.
* gas/mips/ld.d: Remove "-march=r4000" and "-mmips:4000" from
gas/objdump options.
* gas/mips/ld-ilocks.d: Add "-32" to gas options.
* gas/mips/mips.exp: Run the two cases with run_dump_test_arches.
* config/obj-elf.c (elf_adjust_symtab): New. Move group section
processing here from elf_frob_file. Ensure that group signature
symbols have the name of the group.
(elf_frob_file): Move group section processing to
elf_adjust_symtab.
* config/obj-elf.h (elf_adjust_symtab): Declare.
(obj_adjust_symtab): Define.
* config/tc-arm.c (arm_adjust_symtab): Call elf_adjust_symtab.
2010-10-23 Mark Mitchell <mark@codesourcery.com>
* gas/elf/elf.exp: Add group0c test.
* gas/elf/group0c.d: New.
* gas/elf/group0a.d: Expect ".group" for the name of group
sections.
* gas/elf/group0b.d: Likewise.
* gas/elf/group1a.d: Likewise.
* gas/elf/group1b.d: Likewise.
* gas/elf/groupautoa.d: Likewise.
* gas/elf/groupautob.d: Likewise.
* gas/elf/section4.d: Likewise.
* gas/ia64/group-1.d: Likewise. Adjust hard-coded constants.
2010-10-22 Mark Mitchell <mark@codesourcery.com>
* binutils-all/group-5.d: Expect ".group" for the name of group
sections.
* binutils-all/strip-2.d: Likewise.
2010-10-23 Mark Mitchell <mark@codesourcery.com>
* ld-elf/group10.d: Expect ".group" for the name of group
sections.
* ld-elf/group2.d: Likewise.
* ld-elf/group7.d: Likewise.
* emulparams/elf32_sparc_sol2.sh (OUTPUT_FORMAT): Set to
elf32-sparc-sol2.
* emulparams/elf64_sparc_sol2.sh (OUTPUT_FORMAT): Set to
elf64-sparc-sol2.
gas:
* config/tc-sparc.h [TE_SOLARIS] (ELF_TARGET_FORMAT): Define as
elf32-sparc-sol2.
(ELF64_TARGET_FORMAT): Define as elf64-sparc-sol2.
bfd:
* elfxx-sparc.c (tpoff): Define bed, static_tls_size.
Consider static_tls_alignment.
* elf32-sparc.c (TARGET_BIG_SYM): Redefine to
bfd_elf32_sparc_sol2_vec.
(TARGET_BIG_NAME): Redefine to elf32-sparc-sol2.
(elf32_bed): Redefine to elf32_sparc_sol2_bed.
(elf_backend_static_tls_alignment): Redefine to 8.
Include elf32-target.h.
(elf_backend_static_tls_alignment): Undef again for VxWorks.
* elf64-sparc.c (TARGET_BIG_SYM): Redefine to
bfd_elf64_sparc_sol2_vec.
(TARGET_BIG_NAME): Redefine to elf64-sparc-sol2.
(ELF_OSABI): Undef.
(elf64_bed): Redefine to elf64_sparc_sol2_bed.
(elf_backend_static_tls_alignment): Redefine to 16.
Include elf64-target.h.
* config.bfd (sparc-*-solaris2.[0-6]): Split from sparc-*-elf*.
Set targ_defvec to bfd_elf32_sparc_sol2_vec.
[BFD64] (sparc-*-solaris2*): Set targ_defvec to
bfd_elf32_sparc_sol2_vec.
Replace bfd_elf64_sparc_vec by bfd_elf64_sparc_sol2_vec in
targ_selvecs.
* configure.in: Handle bfd_elf32_sparc_sol2_vec,
bfd_elf64_sparc_sol2_vec.
* configure: Regenerate.
* targets.c (bfd_elf32_sparc_sol2_vec): Declare.
(bfd_elf64_sparc_sol2_vec): Declare.
(_bfd_target_vector): Add bfd_elf32_sparc_sol2_vec,
bfd_elf64_sparc_sol2_vec.
* gas/arm/msr-reg-thumb.d: Skip for non-ELF based targets.
* gas/arm/vldr.d: Likewise.
* gas/arm/thumb2_ldmstm.d: Allow for extra NOPs at the end of the disassembly.
* gas/cfi/cfi.exp (cfi-arm-1): Only run for ELF based ARM targets.
* frags.h (struct frag): Add "region" field.
* write.c (relax_frag): Don't add "stretch" to forward reference
target if there is an intervening org or align.
(relax_segment): Set region.
explicitly. Clean up some regexps.
* gas/mips/ld-ilocks.d: Likewise. Add missing "$" prefixes to
the names of FP registers.
* gas/mips/ld-ilocks-addr32.d: Likewise.
* gas/mips/ld.s: Align sections to 4k, adjust padding.
* mips-opc.c (mips_builtin_opcodes): Move M_LD_OB and M_SD_OB
macros before their corresponding MIPS III hardware instructions.
gas/
* config/tc-mips.c (macro)[M_LD_OB, M_SD_OB]: Handle 64-bit ABIs.
gas/testsuite/
* gas/mips/lineno.s: Convert to o32.
* gas/mips/lineno.d: Adjust patterns accordingly. Force the o32
ABI.
Make sure all illegal insns get assembled & decoded correctly.
Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
The BYTEOP2M parser incorrectly calls BYTEOP2P to generate the opcode.
Once we've fixed that, it's easy to see that the disassembler also likes
to decode this insn incorrectly. So fix that and then add some tests.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
The exact symbol addresses are not important to these tests. We only
care about the opcodes and the disassembly output. This makes adding
more insns to these tests easier.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
gas/
2010-10-14 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (_i386_insn): Add disp32_encoding.
(md_assemble): Don't call optimize_disp if disp32_encoding is
set.
(parse_insn): Support .d32 to force 32bit displacement.
(output_branch): Use BIG if disp32_encoding is set.
* doc/c-i386.texi: Document .d32 encoding suffix.
gas/testsuite/
2010-10-14 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/disp32.d: New.
* gas/i386/disp32.s: Likewise.
* gas/i386/x86-64-disp32.d: Likewise.
* gas/i386/x86-64-disp32.s: Likewise.
* gas/i386/i386.exp: Run disp32 and x86-64-disp32.
* s390-opc.c: Make the instruction masks for the load/store on
condition instructions to cover the condition code mask as well.
* s390-opc.txt: lgoc -> locg and stgoc -> stocg.
2010-10-11 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
* gas/s390/zarch-z196.d: Adjust the load/store on condition
instructions.
* gas/s390/zarch-z196.s: Likewise.
