Commit graph

86048 commits

Author SHA1 Message Date
GDB Administrator
67dd2c2073 Automatic date update in version.in 2015-12-13 00:00:08 +00:00
Alan Modra
dafa877d36 Fix SH gas testsuite invalid assembly exposed by ec9ab52c
* gas/sh/tlsd.s: Use .tdata not .tbss.
	* gas/sh/tlsnopic.s: Likewise.
2015-12-12 21:36:39 +10:30
Alan Modra
b817670b52 Enable 2 operand form of powerpc mfcr with -many
This is a workaround for a gcc bug.

	PR 19359
	* ppc-opc.c (insert_fxm): Remove "ignored" from error message.
	(powerpc_opcodes): Remove single-operand mfcr.
2015-12-12 21:34:34 +10:30
GDB Administrator
1f157432d9 Automatic date update in version.in 2015-12-12 00:00:08 +00:00
Andrew Burgess
4fdd372d50 gdb: Extend help text for 'list' command.
Reference the 'listsize' setting in the help text for the 'list' command
to help users find this setting.

gdb/ChangeLog:

	* cli/cli-cmds.c (_initialize_cli_cmds): Extend help text for
	'list' command.
2015-12-11 23:07:00 +00:00
Andrew Burgess
3b2464a8d3 gdb: Add an error when 'list -' reaches the start of a file.
When a a user uses 'list +' to list forward through a source file they
eventually reach the end of the source file.  Subsequent uses of 'list
+' result in an error message like this, that let the user know they are
at the end of the source file:

  Line number XXX out of range; FILENAME has YYY lines.

Compare this to the current behaviour of 'list -' which lists backwards
through a source file.  When the user reaches the beginning of the
source file, subsequent uses of 'list -' result in the command silently
returning.  This can be confusing if the previous uses of 'list -' have
scrolled off the users display, the user receives no reminder that the
have already seen the start of the file.

After this commit a use of 'list -' when the user has already seen the
start of a file will receive the following error:

   Already at the start of FILENAME.

gdb/ChangeLog:

	* cli/cli-cmds.c (list_command): Add an error when trying to use
	'-' to scan read off the start of the source file.

gdb/testsuite/ChangeLog:

	* gdb.base/list.exp (test_list_forward): Add end of file error
	test.
	(test_repeat_list_command): Add end of file error test.
	(test_list_backwards): Add beginning of file error test.
2015-12-11 23:06:14 +00:00
Andrew Burgess
a0def019aa gdb: 'list' command, tweak handling of +/- arguments.
There is an inconsistency with the handling of the special +/- arguments
to the list command.

For the very first time that list is used (after the inferior has
changed locations) then only the first character of the argument string
is checked, so 'list +BLAH' will operate as 'list +' and 'list -----FOO'
will operate as 'list -'.  This compares to each subsequent use of list,
where the whole argument string is checked, so 'list +BLAH' will try to
list lines of code around the function '+BLAH'.

This commit unifies the behaviour so that the whole argument string is
checked, in order to list the next 10, or previous 10 lines from a file
only 'list +' and 'list -' are now valid.

gdb/ChangeLog:

	* cli/cli-cmds.c (list_command): Check that the argument string is
	a single character, either '+' or '-'.

gdb/testsuite/ChangeLog:

	* gdb.base/list.exp (test_list_invalid_args): New function,
	defined, and called.
2015-12-11 23:05:35 +00:00
Andrew Burgess
5c000dff26 gdb: Make test names unique in list.exp.
gdb/testsuite/ChangeLog:

	* gdb.base/list.exp (test_list): Make test names unique.
2015-12-11 23:04:51 +00:00
Andrew Burgess
1a48ce7677 gdb: Small code restructure for list_command.
Move handling of special +/- arguments to the list_command function
inside a single if block, this helps group all related functionality
together.  There should be no user visible changes after this commit.

gdb/ChangeLog:

	* cli/cli-cmds.c (list_command): Move all handling of +/-
	arguments into a single if block.
2015-12-11 23:04:25 +00:00
Andrew Burgess
8c05462adb gdb: Use NULL instead of 0 for pointer comparison.
Small code cleanup, use NULL instead of 0 when checking pointers.  There
should be no user visible changes after this commit.

gdb/ChangeLog:

	* cli/cli-cmds.c (list_command): Use NULL instead of 0 when
	checking pointers.
2015-12-11 23:04:02 +00:00
Andrew Burgess
f43f85715a gdb: Make lines_to_list variable static.
Small clean up, make variable static.

gdb/ChangeLog:

	* source.c (lines_to_list): Make static.
2015-12-11 23:03:05 +00:00
Cary Coutant
6e0813d359 Pass relocations to Target::do_calls_non_split.
gold/
	* target.h (Target::calls_non_split): Add prelocs, reloc_count
	parameters.
	(Target::do_calls_non_split): Likewise.
	* target.cc (Target::do_calls_non_split): Likewise.
	* reloc.cc (Sized_relobj_file::split_stack_adjust_reltype): Adjust
	call to Target::calls_non_split.

	* i386.cc (Target_i386::do_calls_non_split): Add prelocs, reloc_count
	parameters.
	* powerpc.cc (Target_powerpc::do_calls_non_split): Likewise.
	* x86_64.cc (Target_x86_64::do_calls_non_split): Likewise.
2015-12-11 14:23:59 -08:00
Cary Coutant
6b2353a53a Make output views accessible to Target during do_relocate().
gold/
	* object.cc (Sized_relobj_file::Sized_relobj_file): Initialize
	output_views_.
	* object.h (Object::get_output_view): New function.
	(Object::do_get_output_view): New function.
	(Sized_relobj_file::do_get_output_view): New function.
	(Sized_relobj_file::output_views_): New data member.
	* reloc.cc: (Sized_relobj_file::do_relocate): Store pointer to
	output views in class object.
	(Sized_relobj_file::do_get_output_view): New function.
2015-12-11 14:23:58 -08:00
Yao Qi
f1637ebed1 Remove gdb.base/coremaker2.c
I happen to find that coremaker2.c isn't used in the testsuite (if I
don't miss anything).  I don't believe it until I see this ChangeLog
entry,

1999-11-18  Fred Fish  <fnf@cygnus.com>

        * gdb.base/coremaker2.c: Add sample program for generating
        cores that is more self contained than coremaker.c.  Eventually
        I'll add more code to this and tie it into the testsuite.

looks Fred didn't "tie it into testsuite" later.

gdb/testsuite:

2015-12-11  Yao Qi  <yao.qi@linaro.org>

	* gdb.base/coremaker2.c: Remove.
2015-12-11 16:21:09 +00:00
Yao Qi
db91f50261 Understand arm breakpoints in aarch64_breakpoint_at
AArch64 GDBserver can debug ARM program, and it should recognize
various arm breakpoint instructions.  This patch should be included
in 17b1509a.

gdb/gdbserver:

2015-12-11  Yao Qi  <yao.qi@linaro.org>

	* linux-aarch64-low.c (aarch64_breakpoint_at): Call
	arm_breakpoint_at if the process is 32-bit.
2015-12-11 11:19:52 +00:00
Yao Qi
b37a6290be Use arm_eabi_breakpoint on aarch32
Nowdays, GDBserver chooses arm breakpoint instructions by checking
macro __ARM_EABI__.  When aarch64 GDBserver debugs arm program,
arm_eabi_breakpoint is still needed, but __ARM_EABI__ isn't defined
in aarch64 compiler.  This causes GDBserver chooses the wrong
breakpoint instruction for arm program.  This patch fixes it.

gdb/gdbserver:

2015-12-11  Yao Qi  <yao.qi@linaro.org>

	* linux-aarch32-low.c [__aarch64__]: Use arm_abi_breakpoint
	arm breakpoint.
2015-12-11 11:19:52 +00:00
Matthew Wahab
1e6f4800fc [AArch64][Patch 5/5] Add instruction PSB CSYNC
The Statistical Profile Extension adds the instruction PSB CSYNC as an
alias for the HINT  instruction. This patch adds the instruction to
binutils as a HINT alias that takes an operand.

A new operand type, AARCH64_OPND_BARRIER_PSB, is added to represent the
operand to PSB. A parser for the operand type is added to the assembler
and a printer to the disassembler. The operand name "csync" is added to
the list of HINT options with HINT number . Encoding and decoding of
the operand is handled by the ins_hint/ext_hint functions added in the
preceding patches.

gas/
2015-12-11  Matthew Wahab  <matthew.wahab@arm.com>

	* config/tc-aarch64.c (aarch64_hint_opt_hsh): New.
	(parse_barrier_psb): New.
	(parse_operands): Add case for AARCH64_OPND_BARRIER_PSB.
	(md_begin): Set up aarch64_hint_opt_hsh.

gas/testsuite/
2015-12-11  Matthew Wahab  <matthew.wahab@arm.com>

	* gas/aarch64/system-2.d: Enable the statistical profiling
	extension.  Update the expected output.
	* gas/aarch64/system-2.s: Add tests for PSB CSYNC.
	* gas/aarch64/system.d: Update the expected output.

include/opcode/
2015-12-11  Matthew Wahab  <matthew.wahab@arm.com>

	* aarch64.h (aarch64_opnd): Add AARCH64_OPND_BARRIER_PSB.
	* aarch64-asm-2.c: Regenerate.
	* aarch64-dis-2.c: Regenerate.
	* aarch64-opc-2.c: Regenerate.
	* aarch64-opc.c (aarch64_hint_options): Add "csync".
	(aarch64_print_operands): Handle AARCH64_OPND_BARRIER_PSB.
	* aarch64-tbl.h (aarch64_feature_stat_profile): New.
	(STAT_PROFILE): New.
	(aarch64_opcode_table): Add "psb".
	(AARCH64_OPERANDS): Add "BARRIER_PSB".

Change-Id: I5ffb672d26a8b15b48785478d359350a9b70ca09
2015-12-11 10:22:40 +00:00
Matthew Wahab
9ed608f98b [AArch64][Patch 4/5] Support HINT aliases taking operands.
The Statistical Profile Extension adds the instruction PSB CSYNC as an
alias for the HINT  instruction. This patch adds support for aliases
of HINT which take an operand, adding a table to store operand names and
their matching hint number as well as encoding and decoding functions
for such operands. Parsing and printing the operands are deferred to any
support added for aliases with such operands.

include/opcode/
2015-12-11  Matthew Wahab  <matthew.wahab@arm.com>

	* aarch64.h (aarch64_hint_options): Declare.
	(aarch64_opnd_info): Add field hint_option.

opcodes/
2015-12-11  Matthew Wahab  <matthew.wahab@arm.com>

	* aarch64-asm.c (aarch64_ins_hint): New.
	* aarch64-asm.h (aarch64_ins_hint): Declare.
	* aarch64-dis.c (aarch64_ext_hint): New.
	* aarch64-dis.h (aarch64_ext_hint): Declare.
	* aarch64-opc-2.c: Regenerate.
	* aarch64-opc.c (aarch64_hint_options): New.
	* aarch64-tbl.h (AARCH64_OPERANDS): Fix typos.

Change-Id: I2205038fc1c47d3025d1f0bc2fbf405b5575b287
2015-12-11 10:12:34 +00:00
Matthew Wahab
a0f7013add [AArch64][Patch 3/5] Adjust maximum number of instruction aliases.
The Statistical Profile Extension adds the instruction PSB CSYNC as an
alias for the HINT  instruction. The HINT instruction currently has 8
aliases, which is the maximum number allowed. This patch raises to 16
the limit on the number of aliases an instruction can have.

opcodes/
2015-12-11  Matthew Wahab  <matthew.wahab@arm.com>

	* aarch64-gen.c (find_alias_opcode): Set max_num_aliases to 16.

Change-Id: I131044bf6e0fe0940a9e7478d9bf52137748907d
2015-12-11 10:12:08 +00:00
Matthew Wahab
55c144e691 [AArch64][Patch 2/5] Add Statistical Profiling Extension system registers.
The Statistical Profile extension included in the ARMv8.2 architecture
adds a number of system registers. This patch adds the registers to
binutils, making them available when the architecture extension
"+profile" is enabled.

opcodes/
2015-12-11  Matthew Wahab  <matthew.wahab@arm.com>

	* aarch64-opc.c (aarch64_sys_reg): Add pbmlimitr_el1, pmbptr_el1,
	pmbsr_el1, pmbidr_el1, pmscr_el1, pmsicr_el1, pmsirr_el1,
	pmsfcr_el1, pmsevfr_el1, pmslatfr_el1, pmsidr_el1, pmscr_el2 and
	pmscr_el2.
	(aarch64_sys_reg_supported_p): Add architecture feature tests for
	the new registers.

gas/testsuite/
2015-12-11  Matthew Wahab  <matthew.wahab@arm.com>

	* gas/aarch64/sysreg-2.s: Add tests for the statistical profiling
	system registers.
	* gas/aarch64/sysreg-2.d: Enable the statistical profiling
	extension and update the expected output.

Change-Id: Ibf23ad34db7c33f0fcd30010b796748b38be6efb
2015-12-11 09:52:11 +00:00
Matthew Wahab
73af8ed6b1 [AArch64][Patch 1/5] Support the ARMv8.2 Statistical Profiling Extension.
The Statistical Profile extension included in the ARMv8.2 architecture
adds a number of system registers and a new instruction. This patch set
adds support for the extension to binutils, enabled when
-march=armv8.2-a+profile is given.

The patches in this series:
- Add the new command line option and feature flags.
- Add the new system registers.
- Adjust the maximum number of aliases permitted for an instruction.
- Add support for HINT aliases which take operands.
- Add the new instruction, an alias of the HINT instruction.

This patch adds the option "profile" to the permitted architecture
extensions, disabling it by default.

gas/
2015-12-11  Matthew Wahab  <matthew.wahab@arm.com>

	* config/tc-aarch64.c (aarch64_features): Add "profile".
	* doc/c-aarch64.texi (AArch64 Extensions): Add "profile".

include/opcode/
2015-12-11  Matthew Wahab  <matthew.wahab@arm.com>

	* aarch64.h (AARCH64_FEATURE_PROFILE): New.

Change-Id: If9bb4a9b69a264180f96f8ffaf10b15ced273699
2015-12-11 09:30:26 +00:00
GDB Administrator
9343aa2bf0 Automatic date update in version.in 2015-12-11 00:00:13 +00:00
H.J. Lu
c5847ba726 ld -r doesn't need plugin for slim lto object
Plugin isn't required on slim lto object for relocatable link.

bfd/

	PR ld/19317
	* linker.c (_bfd_generic_link_add_one_symbol): Don't complain
	plugin needed to handle slim lto object for relocatable link.

ld/testsuite/

	PR ld/19317
	* ld-plugin/lto.exp (lto_no_fat): New.
	(lto_link_tests): Add a test for PR ld/19317.
	(lto_run_tests): Likewise.
	(run_ld_link_tests): Likewise.
2015-12-10 12:35:50 -08:00
Antoine Tremblay
60269a4a36 Fix regression revealed by corethreads.exp
This patch fixes a regression introduced by:
https://sourceware.org/ml/gdb-patches/2015-12/msg00192.html

We can't use thread_from_lwp with core files.  As mentioned in a comment,
td_ta_map_lwp2thr uses ps_get_thread_area, but we can't use that
currently on core targets, as it uses ptrace directly.

Use directly record_thread instead.

This fixes :
PASS -> FAIL: gdb.threads/corethreads.exp: thread0 found
PASS -> FAIL: gdb.threads/corethreads.exp: thread1 found

gdb/ChangeLog:

	* linux-thread-db.c (find_new_threads_callback): Use record_thread.
2015-12-10 14:43:48 -05:00
H.J. Lu
bebf4942b0 ld -r doesn't need plugin for slim lto object
Plugin isn't required on slim lto object for relocatable link.

	PR ld/19317
	* symtab.cc (Symbol_table::add_from_relobj): Don't complain
	plugin needed to handle slim lto object for relocatable link.
2015-12-10 11:29:03 -08:00
Pedro Alves
f4f4330e51 [gdb/doc] Explain that there's always a thread
This warning is a few years out of date -- there's always a thread
nowadays.

gdb/doc/ChangeLog:

	* gdb.texinfo (Threads): Replace warning with explanation
	about single-threaded programs.
2015-12-10 17:47:57 +00:00
Matthew Wahab
22a5455c6c [Aarch64] Support ARMv8.2 AT instructions
ARMv8.2 adds new instructions AT S1E1RP and AT S1E1WP to Aarch64. This
patch adds support for the instructions, making them available when
-march=armv8.2-a is selected.

gas/testsuite/
2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>

	* gas/aarch64/sysreg-2.d: Update for new tests for AT S1E1RP and
	AT S1E1WP.
	* gas/aarch64/sysreg-2.s: Add tests for AT S1E1RP and AT S1E1WP.

opcodes/
2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>

	* aarch64-opc.c (aarch64_sys_regs_at): Add "s1e1rp" and "s1e1wp".
	(aarch64_sys_ins_reg_supported_p): Add ARMv8.2 system register
	feature test for "s1e1rp" and "s1e1wp".

Change-Id: I09e1044b629ab0a34b03c423e8d4e71ff92daad4
2015-12-10 17:00:27 +00:00
Pedro Alves
b1236ac35a [gdb/doc] Remove references to no-longer-supported systems
HP-UX and SGI/IRIX are no longer supported.  Remove references
throughout.

AFAICS from the sources, "catch fork" seems to be supported in
multiple Unix systems -- just remove the "only works on xxx" remarks.

Update the list of supported shared library types.

gdb/doc/ChangeLog:

	* gdb.texinfo (Threads): Remove mention of SGI.
	(Forks): Remove mention of HP-UX.
	(Breakpoints): Remove mention of HP-UX.
	(Set Watchpoints) <hardware watchpoints>: Don't mention HP-UX.
	Reword in terms of architectures.
	(Set Catchpoints) <catch exec, catch fork, catch vfork>: Don't
	mention supported systems.
	(Convenience Vars): Don't mention HP-UX.
	(Jumping): Remove mention of HP-UX in comment.
	(Files) <shared libraries>: Update supported shared library types
	list.  Remove mention of HP-UX.
	(Native): Remove HP-UX subsection.
	(SVR4 Process Information): Remove mention of HP-UX.
2015-12-10 16:51:01 +00:00
Pedro Alves
36d6fc0a3c Remove "spaces" references from gdb.multi/base.exp
I think these references to "spaces" came from the original multi-exec
submission that exposed "symbol spaces" to the user and had a
different UI, and then survived a global find/replace.

gdb/testsuite/ChangeLog:
2015-12-10  Pedro Alves  <palves@redhat.com>

	* gdb.multi/base.exp: Remove stale "spaces" references.
2015-12-10 16:49:32 +00:00
Matthew Wahab
d6bf7ce6c2 [AArch64][PATCH 2/2] Support ARMv8.2 DC CVAP instruction.
ARMv8.2 adds the new system instruction DC CVAP. This patch adds support
for the instruction to binutils, enabled when -march=armv8.2-a is
selected.

gas/
2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>

	* config/tc-aarch64.c (parse_sys_ins_reg): Add check of
	architectural support for system register.

gas/testsuite/
2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>

	* gas/aarch64/sysreg-2.d: Add tests for dc instruction.
	* gas/aarch64/sysreg-2.s: Add uses of dc instruction.

include/opcode/
2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>

	* aarch64.h (aarch64_sys_ins_reg_supported_p): Declare.

opcodes/
2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>

	* aarch64-opc.c (aarch64_sys_regs_dc): Add "cvap".
	(aarch64_sys_ins_reg_supported_p): New.

Change-Id: I3158b97d9bbee9644c2d0e2986db807412ef1053
2015-12-10 16:40:45 +00:00
Matthew Wahab
ea2deeec92 [AArch64][PATCH 1/2] Add support for ARMv8.2 DC CVAP instruction.
ARMv8.2 adds the new system instruction DC CVAP. This patch series adds
support for this instruction to binutils, enabled when -march=armv8.2-a
is selected.

The AArch64 binutils record of some system registers uses a boolean
value to hold the single flag currently supported for them. To allow
these registers to be limited to specific architectures, the first patch
in this series replaces the boolean flag with a bitset and feature test.

include/opcode/
2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>

	* aarch64.h (aarch64_sys_ins_reg): Replace has_xt with flags.
	(aarch64_sys_ins_reg_has_xt): Declare.

opcodes/
2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>

	* aarch64-dis.c (aarch64_ext_regrt_sysins): Replace use of has_xt
	with aarch64_sys_ins_reg_has_xt.
	(aarch64_ext_sysins_op): Likewise.
	* aarch64-opc.c (operand_general_constraint_met_p): Likewise.
	(F_HASXT): New.
	(aarch64_sys_regs_ic): Update for changes to aarch64_sys_ins_reg.
	(aarch64_sys_regs_dc): Likewise.
	(aarch64_sys_regs_at): Likewise.
	(aarch64_sys_regs_tlbi): Likewise.
	(aarch64_sys_ins_reg_has_xt): New.

Change-Id: I363637a6c3f54d7ffff953b3a0734e8139cae819
2015-12-10 16:40:44 +00:00
Pedro Alves
762f774785 Stop using nowarnings in gdb/testsuite/gdb.multi/
Several of the gdb.multi tests use the "nowarnings" option to suppress
warnings.  The warnings in question all come from missing headers,
like e.g.:

 src/gdb/testsuite/gdb.multi/multi-arch-exec.c:28:3: warning: incompatible implicit declaration of built-in function 'exit' [enabled by default]
    exit (1);
    ^

There's no point in trying to avoid to include standard headers.  In
gdb.base/hangout.c's case, it's even dangerous, as that file calls
printf.  In order to compile a call to a variatic function correctly,
a declaration must be visible.

gdb/testsuite/ChangeLog:
2015-12-10  Pedro Alves  <palves@redhat.com>

	* gdb.multi/base.exp: Don't use nowarnings.
	* gdb.multi/bkpt-multi-exec.exp: Don't use nowarnings.
	* gdb.multi/hangout.c: Include stdio.h.
	* gdb.multi/hello.c: Include stdlib.h.
	* gdb.multi/multi-arch-exec.c: Include stdlib.h.
	* gdb.multi/multi-arch-exec.exp: Don't use nowarnings.
	* gdb.multi/multi-arch.exp: Don't use nowarnings.
2015-12-10 16:21:06 +00:00
Kwok Cheung Yeung
4a07dc8135 ld: Fix LTO for MinGW targets
When creating a dummy BFD for an IR file, the output BFD is used as
a template for the new BFD, when it needs to be the input BFD passed
into the function when not dealing with a BFD plugin.

On most targets this is not an issue as the input and output formats
are the same anyway, but on MinGW targets, there are two variant
formats used (pe-i386/pe-x86-64 and pei-i386/pei-x86-64) which are
similar but not interchangeable here.

	PR ld/18199
	* plugin.c (plugin_get_ir_dummy_bfd): Use srctemplate as the
	template when calling bfd_create if it does not use the BFD
	plugin target vector.
2015-12-10 16:12:33 +00:00
Matthew Wahab
6479e48ef9 [AArch64][binutils] Add support for ARMv8.2 PSTATE.UAO.
ARMv8.2 adds a new control bit PSTATE.UAO. This patch adds support for
this bit to binutils, following the same basic pattern as for
PSTATE.PAN. The new control bit is only available when -march=armv8.2-a
is specified.

gas/testsuite/
2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>

	* gas/aarch64/uao-directive.d: New.
	* gas/aarch64/uao.d: New.
	* gas/aarch64/uao.s: New.

opcodes/
2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>

	* aarch64-opc.c (aarch64_sys_regs): Add "uao".
	(aarch64_sys_reg_supported_p): Add comment.  Add checks for "uao".
	(aarch64_pstatefields): Add "uao".
	(aarch64_pstatefield_supported_p): Add checks for "uao".

Change-Id: Id571628ac5227b78aaf1876e85d15d7b6c0a2896
2015-12-10 16:03:56 +00:00
Jose E. Marchesi
7039122d13 gas: documentation for the SPARC %dN and %qN fp registers notation
gas/ChangeLog:

2015-12-10  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* doc/c-sparc.texi (Sparc-Regs): Document the %dN and %qN notation
	for floating-point registers.
2015-12-10 11:03:17 -05:00
Antoine Tremblay
c2c2a31fdb Remove support for thread events without PTRACE_EVENT_CLONE in GDB
Before, on systems that did not support PTRACE_EVENT_CLONE, both GDB and
GDBServer coordinated with libthread_db.so to insert breakpoints at magic
locations in libpthread.so, in order to break at thread creation and
thread death.

Support for thread events was removed from GDBServer as patch:
https://sourceware.org/ml/gdb-patches/2015-11/msg00466.html

This patch removes support for thread events in GDB.

No regressions found on Ubuntu 14.04 x86_64.

gdb/ChangeLog:

	* breakpoint.c (remove_thread_event_breakpoints): Remove.
	* breakpoint.h (remove_thread_event_breakpoints): Remove
	declaration.
	* linux-nat.c (in_pid_list_p): Remove.
	(lin_lwp_attach_lwp): Remove.
	* linux-nat.h (lin_lwp_attach_lwp): Remove declaration.
	* linux-thread-db.c (thread_db_use_events): Remove.
	(struct thread_db_info) <td_create_bp_addr>: Remove.
	<td_death_bp_addr>: Likewise.
	<td_ta_event_addr_p>: Likewise.
	<td_ta_set_event_p>: Likewise.
	<td_ta_clear_event_p>: Likewise.
	<td_ta_event_getmsg_p>: Likewise.
	<td_thr_event_enable_p>: Likewise.
	(attach_thread): Likewise.
	(detach_thread): Likewise.
	(have_threads_callback): Likewise.
	(have_threads): Likewise.
	(enable_thread_event): Likewise.
	(enable_thread_event_reporting): Likewise.
	(try_thread_db_load_1): Remove td_ta_event_addr, td_ta_set_event,
	td_ta_clear_event, td_ta_event_getmsg, td_thr_event_enable
	initializations.
	(try_thread_db_load_1): Remove enable_thread_event_reporting call.
	(disable_thread_event_reporting): Remove.
	(record_thread): Adapt to thread_db_use_event removal.
	(detach_thread): Remove.
	(thread_db_detach): Adapt to thread_db_use_event removal.
	(check_event): Remove.
	(thread_db_wait): Adapt to thread events support removal.
	(thread_db_mourn_inferior): Likewise.
	(find_new_threads_callback): Likewise.
	(find_new_threads_once): Likewise.
	(thread_db_update_thread_list): Likewise.
2015-12-10 10:46:29 -05:00
Matthew Wahab
47f8114261 [AArch64][PATCH 2/2] Add RAS system registers.
The ARMv8.2 RAS extension adds a number of new registers. This patch
adds the registers and makes them available whenever the RAS extension
is enabled, as it is when -march=armv8.2-a is selected.

The new registers are:
    erridr_el1, errselr_el1, erxfr_el1, erxctlr, erxaddr_el1,
    erxmisc0_el1, erxmisc1_el1, vsesr_el2, disr_el1 and
    vdisr_el2.

gas/testsuite/
2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>

	* gas/aarch64/sysreg-2.d: Add tests for new registers.
	* gas/aarch64/sysreg-2.s: Likewise.  Also replace some spaces with
	tabs.

opcodes/
2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>

	* aarch64-opc.c (aarch64_sys_regs): Add "vsesr_el2", "erridr_el1",
	"errselr_el1", "erxfr_el1", "erxctlr", "erxaddr_el1",
	"erxmisc0_el1", "erxmisc1_el1", "disr_el1" and "vdisr_el2".
	(aarch64_sys_reg_supported_p): Add architecture feature tests for
	new registers.

Change-Id: I8a01a0f0ee7987f89eead32650f6afcc749b3c74
2015-12-10 14:10:24 +00:00
Matthew Wahab
c8a6db6fa0 [AArch64][PATCH 1/2] Add support for RAS instruction ESB.
The ARMv8.2 RAS extension adds a new barrier instruction ESB as an alias
and the preferred form of HINT 16.

This patch adds an architectural feature flag for the RAS extension and
includes it in the features selected enabled by -march=armv8.2-a. It
also adds the ESB instruction, making it available whenever the RAS
feature is enabled.

Because ESB is the preferred form and because the target architecture
isn't available to the disassembler, HINT 16 will be disassembled as ESB
even when the target has no support for the RAS extension.

gas/testsuite/
2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>

	* gas/aarch64/system-2.d: New.
	* gas/aarch64/system-2.s: New.
	* gas/aarch64/system.d: Adjust expected output for HINT 16.

include/opcode/
2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>

	* aarch64.h (AARCH64_FEATURE_RAS): New.
	(AARCH64_ARCH_V8_2): Add AARCH64_FEATURE_RAS.

opcodes/
2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>

	* aarch64-asm-2.c: Regenerate.
	* aarch64-dis-2.c: Regenerate.
	* aarch64-tbl.h (aarch64_feature_ras): New.
	(RAS): New.
	(aarch64_opcode_table): Add "esb".

Change-Id: Id4713917da15cca3b977284f43febd1c9b3d9faf
2015-12-10 14:10:15 +00:00
Matthew Wahab
af117b3cf1 [AArch64] Fix ARMv8.1 and ARMv8.2 feature settings.
ARMv8.1 includes CRC as a required extension but this isn't reflected in
the features enabled by -march=armv8.1-a. The FP16 feature modifier also
clashes with AARCH64_FEATURE_V8_1 and the list of features for ARMv8.2
is missing ARMv8.1 features.

This patch enables +crc for -march values of armv8.1-a and later. It
also fixes the values for AARCH64_FEATURE_F16 and makes
AARCH64_ARCH_V8_2 and superset of AARCH64_ARCH_V8_2.

gas/
2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>

	* doc/c-aarch64.texi (AArch64 Extensions): Update entry for crc.

include/opcode
2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>

	* aarch64.h (AARCH64_FEATURE_F16): Fix clash with
	AARCH64_FEATURE_V8_1.
	(AARCH64_ARCH_V8_1): Add AARCH64_FEATURE_CRC.
	(AARCH64_ARCH_V8_2): Add AARCH64_FEATURE_CRC and
	AARCH64_FEATURE_V8_1.

Change-Id: I8af5369f6df2430b28f6cec92870d2a4d14a7431
2015-12-10 14:10:06 +00:00
Pedro Alves
0f59c28f61 [gdb/doc] Stack, Examining the Stack: Reorder menu
Commit fc58fa65d4 (gdb/doc: Restructure frame command documentation)
reordered the sections in the 'Examining the Stack' chapter, but
missed updating the menu:

src/gdb/doc/gdb.texinfo:6968: warning: node next `Backtrace' in menu `Frame Filter Management' and in sectioning `Selection' differ
src/gdb/doc/gdb.texinfo:7167: warning: node prev `Selection' in menu `Frame Filter Management' and in sectioning `Backtrace' differ
src/gdb/doc/gdb.texinfo:7252: warning: node `Frame Filter Management' is next for `Frame Info' in sectioning but not in menu
src/gdb/doc/gdb.texinfo:7317: warning: node `Selection' is next for `Frame Filter Management' in menu but not in sectioning
src/gdb/doc/gdb.texinfo:7317: warning: node prev `Frame Filter Management' in menu `Backtrace' and in sectioning `Frame Info' differ

gdb/doc/ChangeLog:
2015-12-10  Pedro Alves  <palves@redhat.com>

	* gdb.texinfo (Stack): Reorder menu.
2015-12-10 11:39:58 +00:00
Andrew Burgess
28d2bfb9c3 gdb: Handle multiple base address in debug_ranges data.
It is possible to use multiple base addresses within a single address
range series, within the .debug_ranges section.  The following is a
simplified example for 32-bit addresses:

  .section ".debug_ranges"
  .4byte	0xffffffff
  .4byte	BASE_1
  .4byte	START_OFFSET_1
  .4byte	END_OFFSET_1
  .4byte	START_OFFSET_2
  .4byte	END_OFFSET_2
  .4byte	0xffffffff
  .4byte	BASE_2
  .4byte	START_OFFSET_3
  .4byte	END_OFFSET_3
  .4byte	0
  .4byte	0

In this example START/END 1 and 2 are relative to BASE_1, while
START/END 3 are relative to BASE_2.

Currently gdb does not correctly parse this DWARF, resulting in
corrupted address range information.  This commit fixes this issue, and
adds a new test to cover this case.

In order to support testing of this feature extensions were made to the
testsuite dwarf assembler, additional functionality was added to the
.debug_line generation function, and a new function for generating the
.debug_ranges section was added.

gdb/ChangeLog:

	* dwarf2read.c (dwarf2_ranges_read): Unify and fix base address
	reading code.

gdb/testsuite/ChangeLog:

	* gdb.dwarf2/dw2-ranges-base.c: New file.
	* gdb.dwarf2/dw2-ranges-base.exp: New file.
	* lib/dwarf.exp (namespace eval Dwarf): Add new variables to
	support additional line table, and debug ranges generation.
	(Dwarf::ranges): New function, generate .debug_ranges.
	(Dwarf::lines): Support generating simple line table programs.
	(Dwarf::assemble): Initialise new namespace variables.
2015-12-10 09:53:46 +00:00
Andrew Burgess
c740885937 arc/gas: Accept, but ignore, dummy arguments.
There's a set of legacy command line arguments that the arc assembler
still accepts, however, these arguments not longer have any effect on
the assembler.

Currently we return false from md_parse_option for all of these
arguments, with the result that the assembler terminates with an error
message.

We should return true indicating that the argument has been accepted,
even though we ignore it.

gas/ChangeLog:

	* config/tc-arc.c (md_parse_option): Return 1 in order to accept
	dummy arguments.
2015-12-10 09:23:19 +00:00
Sandra Loosemore
33d4099fc8 Fix GOT address computations in initial PLT entries for nios2.
2015-12-09  Sandra Loosemore  <sandra@codesourcery.com>

	bfd/
	* elf32-nios2.c (nios2_elf32_finish_dynamic_sections): Correct
	%hiadj/%lo computations for _GLOBAL_OFFSET_TABLE_ in initial
	PLT entries.  Assert alignment requirements.
2015-12-09 16:13:58 -08:00
GDB Administrator
a0fad44f98 Automatic date update in version.in 2015-12-10 00:00:12 +00:00
Kevin Buettner
f56331b468 dwarf2loc.c: Perform a pointer to address conversion for DWARF_VALUE_MEMORY.
This patch fixes the following failures for rl78-elf:

FAIL: gdb.base/vla-datatypes.exp: print int_vla
FAIL: gdb.base/vla-datatypes.exp: print unsigned_int_vla
FAIL: gdb.base/vla-datatypes.exp: print double_vla
FAIL: gdb.base/vla-datatypes.exp: print float_vla
FAIL: gdb.base/vla-datatypes.exp: print long_vla
FAIL: gdb.base/vla-datatypes.exp: print unsigned_long_vla
FAIL: gdb.base/vla-datatypes.exp: print char_vla
FAIL: gdb.base/vla-datatypes.exp: print short_vla
FAIL: gdb.base/vla-datatypes.exp: print unsigned_short_vla
FAIL: gdb.base/vla-datatypes.exp: print unsigned_char_vla
FAIL: gdb.base/vla-datatypes.exp: print foo_vla
FAIL: gdb.base/vla-datatypes.exp: print bar_vla
FAIL: gdb.base/vla-datatypes.exp: print vla_struct_object
FAIL: gdb.base/vla-datatypes.exp: print vla_union_object
FAIL: gdb.base/vla-ptr.exp: print td_vla
FAIL: gdb.mi/mi-vla-c99.exp: evaluate complete vla

The first failure in this bunch occurs due to printing an incorrect
result for a variable length array:

    print int_vla
    $1 = {-1, -1, -1, -1, -1}

The result should actually be this:

    $1 = {0, 2, 4, 6, 8}

When I started examining this bug, I found that printing an
individual array element worked correctly.  E.g. "print int_vla[2]"
resulted in 4 being printed.  I have not looked closely to see why
this is the case.

I found that evaluation of the location expression for int_vla was
causing problems.  This is the relevant DWARF entry for int_vla:

<2><15a>: Abbrev Number: 10 (DW_TAG_variable)
    <15b>   DW_AT_name        : (indirect string, offset: 0xbf): int_vla
    <15f>   DW_AT_decl_file   : 1
    <160>   DW_AT_decl_line   : 35
    <161>   DW_AT_type        : <0x393>
    <165>   DW_AT_location    : 4 byte block: 86 7a 94 2  (DW_OP_breg22 (r22): -6; DW_OP_deref_size: 2)

I found that DW_OP_breg22 was providing a correct result.
DW_OP_deref_size was fetching the correct value from memory.  However,
the value being fetched should be considered a pointer.
DW_OP_deref_size zero extends the fetched value prior to pushing
it onto the evaluation stack.  (The DWARF-4 document specifies this
action; so GDB is faithfully implementing the DWARF-4 specification.)

However, zero extending the pointer is not sufficient for converting
that value to an address for rl78 and (perhaps) other architectures
which define a `pointer_to_address' method.  (I suspect that m32c
would have the same problem.)

Ideally, we would perform the pointer to address conversion in
DW_OP_deref_size.  We don't, however, know the type of the object
that the address refers to in DW_OP_deref_size.  I can't think
of a way to infer the type at that point in the code.

Before proceeding, I should note that there are two other DWARF
operations that could be used in place of DW_OP_deref_size.  One of
these is DW_OP_GNU_deref_type.  Current GDB implements this operation,
but as is obvious from the name, it is non-standard DWARF.  The other
operation is DW_OP_xderef_size.  Even though it's part of DWARF-2
through DWARF-4 specifications, it's not presently implemented in GDB.
Present day GCC does not output dwarf expressions containing this
operation either.  [Of the two, I like DW_OP_GNU_deref_type better.
Using it avoids the need to specify an "address space identifier".
(GCC, GDB, and other non-free tools all need to agree on the meanings
of these identifiers.)]

Back to the bug analysis...

The closest consumer of the DW_OP_deref_size result is the
DWARF_VALUE_MEMORY case in dwarf2_evaluate_loc_desc_full.  At that
location, we do know the object type to which the address is intended
to refer.  I added code to perform a pointer to address conversion at
this location.  (See the patch.)

I do have some misgivings regarding this patch.  As noted earlier, it
would really be better to perform the pointer to address conversion in
DW_OP_deref_size.  I can't, however, think of a way to make this work.
Changing GCC to output one of the other aforementioned operations might
be preferable but, as noted earlier, these solutions have problems as
well.  Long term, I think it'd be good to have something like
DW_OP_GNU_deref_type become part of the standard.  If that can't or
won't happen, we'll need to implement DW_OP_xderef_size.

But until that happens, this patch will work for expressions in which
DW_OP_deref_size occurs last.  It should even work for dereferences
followed by adding an offset.  I don't think it'll work for more than
one dereference in the same expression.

gdb/ChangeLog:

	* dwarf2loc.c (dwarf2_evaluate_loc_desc_full): Perform a pointer
	to address conversion for DWARF_VALUE_MEMORY.
2015-12-09 09:33:21 -07:00
Kevin Buettner
5fc2beac27 gdb.base/async.exp: Handle "asynchronous execution not supported"
This change eliminates some failures on simulator targets and makes
the test run a bit quicker too - without this change, we have to wait
for timeouts.

gdb/testsuite/ChangeLog:

	* gdb.base/async.exp (proc test_background): Add case
	for asynchronous execution not supported.
2015-12-09 09:23:57 -07:00
H.J. Lu
8eab413676 Implement Intel OSPKE instructions
This patch implements Intel OSPKE instructions documented in Intel64
and IA-32 Architectures Software Developer’s Manual Volume 2, September
2015.

gas/testsuite/

	* gas/i386/i386.exp: Run ospke and x86-64-ospke.
	* gas/i386/ospke.d: New file.
	* gas/i386/ospke.s: Likewise.
	* gas/i386/x86-64-ospke.d: Likewise.

opcodes/

	* i386-dis.c (MOD_0F01_REG_5): New.
	(RM_0F01_REG_5): Likewise.
	(reg_table): Use MOD_0F01_REG_5.
	(mod_table): Add MOD_0F01_REG_5.
	(rm_table): Add RM_0F01_REG_5.
	* i386-gen.c (cpu_flag_init): Add CPU_OSPKE_FLAGS.
	(cpu_flags): Add CpuOSPKE.
	* i386-opc.h (CpuOSPKE): New.
	(i386_cpu_flags): Add cpuospke.
	* i386-opc.tbl: Add rdpkru and wrpkru instructions.
	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.
2015-12-09 08:01:57 -08:00
Jan Beulich
fa7cc15f24 gas/ELF: slightly relax elf/file*.d expectations
Despite the re-ordering done for the file symbols, some targets manage
to put section symbols ahead of it.
2015-12-09 14:35:07 +01:00
Luis Machado
1c35a88f1d varobj zero-padded hexadecimal format
This set of patches add support for the zero-padded hexadecimal format for
varobj's, defined as "zero-hexadecimal".  We currently only support regular
non-zero-padded hexadecimal.

Talking with IDE developers, they would like to have this option that is
already available to GDB's print/x commands, in the CLI, as 'z'.

gdb/ChangeLog:

2015-12-09  Luis Machado  <lgustavo@codesourcery.com>

	* gdb/mi/mi-cmd-var.c (mi_parse_format): Handle new "zero-hexadecimal"
	format.
	* gdb/varobj.c (varobj_format_string): Add "zero-hexadecimal" entry.
	(format_code): Add 'z' entry.
	(varobj_set_display_format): Handle FORMAT_ZHEXADECIMAL.
	* gdb/varobj.h (varobj_display_formats) <FORMAT_ZHEXADECIMAL>: New enum
	field.
	* NEWS: Add new note to MI changes citing the new zero-hexadecimal
	format for -var-set-format.

gdb/doc/ChangeLog:

2015-12-09  Luis Machado  <lgustavo@codesourcery.com>

	* gdb.texinfo (GDB/MI Variable Objects): Update text to mention
	-var-set-format's new zero-hexadecimal format.

gdb/testsuite/ChangeLog:

2015-12-09  Luis Machado  <lgustavo@codesourcery.com>

	* gdb.mi/mi-var-display.exp: Add new checks for the zero-hexadecimal
	  format and change test names to make them unique.
2015-12-09 11:00:47 -02:00
Jose E. Marchesi
ec892a0718 sparc: support %dN and %qN syntax for FP registers.
The SPARC Refence Manual documents the %dN and %qN syntax to
refer to double and quad-precision floating-point registers,
respectively.  See OSA2015 Appendix C, Assembly Language Syntax,
C1.1 Register Names.

This patch adds support for these names to GAS.  This eases the
porting of software from Solaris to GNU/Linux, as these register
names have been supported by the Solaris linker for a long time
and many assembler require that support.

gas/ChangeLog:

2015-12-09  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* config/tc-sparc.c (sparc_ip): Support %dN and %qN notation for
	double and quad-precision floating-point registers.
2015-12-09 07:34:32 -05:00