[AArch64][PATCH 1/2] Add support for ARMv8.2 DC CVAP instruction.
ARMv8.2 adds the new system instruction DC CVAP. This patch series adds support for this instruction to binutils, enabled when -march=armv8.2-a is selected. The AArch64 binutils record of some system registers uses a boolean value to hold the single flag currently supported for them. To allow these registers to be limited to specific architectures, the first patch in this series replaces the boolean flag with a bitset and feature test. include/opcode/ 2015-12-10 Matthew Wahab <matthew.wahab@arm.com> * aarch64.h (aarch64_sys_ins_reg): Replace has_xt with flags. (aarch64_sys_ins_reg_has_xt): Declare. opcodes/ 2015-12-10 Matthew Wahab <matthew.wahab@arm.com> * aarch64-dis.c (aarch64_ext_regrt_sysins): Replace use of has_xt with aarch64_sys_ins_reg_has_xt. (aarch64_ext_sysins_op): Likewise. * aarch64-opc.c (operand_general_constraint_met_p): Likewise. (F_HASXT): New. (aarch64_sys_regs_ic): Update for changes to aarch64_sys_ins_reg. (aarch64_sys_regs_dc): Likewise. (aarch64_sys_regs_at): Likewise. (aarch64_sys_regs_tlbi): Likewise. (aarch64_sys_ins_reg_has_xt): New. Change-Id: I363637a6c3f54d7ffff953b3a0734e8139cae819
This commit is contained in:
Matthew Wahab
parent
762f774785
commit
ea2deeec92
5 changed files with 82 additions and 48 deletions
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@ -1,3 +1,8 @@
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2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
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* aarch64.h (aarch64_sys_ins_reg): Replace has_xt with flags.
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(aarch64_sys_ins_reg_has_xt): Declare.
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2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
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* aarch64.h (AARCH64_FEATURE_RAS): New.
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@ -672,9 +672,11 @@ typedef struct
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{
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const char *name;
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uint32_t value;
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int has_xt;
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uint32_t flags ;
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} aarch64_sys_ins_reg;
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extern bfd_boolean aarch64_sys_ins_reg_has_xt (const aarch64_sys_ins_reg *);
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extern const aarch64_sys_ins_reg aarch64_sys_regs_ic [];
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extern const aarch64_sys_ins_reg aarch64_sys_regs_dc [];
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extern const aarch64_sys_ins_reg aarch64_sys_regs_at [];
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@ -1,3 +1,16 @@
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2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
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* aarch64-dis.c (aarch64_ext_regrt_sysins): Replace use of has_xt
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with aarch64_sys_ins_reg_has_xt.
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(aarch64_ext_sysins_op): Likewise.
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* aarch64-opc.c (operand_general_constraint_met_p): Likewise.
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(F_HASXT): New.
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(aarch64_sys_regs_ic): Update for changes to aarch64_sys_ins_reg.
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(aarch64_sys_regs_dc): Likewise.
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(aarch64_sys_regs_at): Likewise.
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(aarch64_sys_regs_tlbi): Likewise.
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(aarch64_sys_ins_reg_has_xt): New.
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2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
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* aarch64-opc.c (aarch64_sys_regs): Add "uao".
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@ -248,7 +248,7 @@ aarch64_ext_regrt_sysins (const aarch64_operand *self, aarch64_opnd_info *info,
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/* This will make the constraint checking happy and more importantly will
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help the disassembler determine whether this operand is optional or
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not. */
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info->present = inst->operands[0].sysins_op->has_xt;
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info->present = aarch64_sys_ins_reg_has_xt (inst->operands[0].sysins_op);
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return 1;
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}
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@ -1034,7 +1034,7 @@ aarch64_ext_sysins_op (const aarch64_operand *self ATTRIBUTE_UNUSED,
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DEBUG_TRACE ("%s found value: %x, has_xt: %d, i: %d.",
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info->sysins_op->name,
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(unsigned)info->sysins_op->value,
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info->sysins_op->has_xt, i);
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aarch64_sys_ins_reg_has_xt (info->sysins_op), i);
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return 1;
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}
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@ -1279,12 +1279,14 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
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{
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assert (idx == 1 && (aarch64_get_operand_class (opnds[0].type)
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== AARCH64_OPND_CLASS_SYSTEM));
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if (opnds[1].present && !opnds[0].sysins_op->has_xt)
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if (opnds[1].present
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&& !aarch64_sys_ins_reg_has_xt (opnds[0].sysins_op))
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{
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set_other_error (mismatch_detail, idx, _("extraneous register"));
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return 0;
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}
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if (!opnds[1].present && opnds[0].sysins_op->has_xt)
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if (!opnds[1].present
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&& aarch64_sys_ins_reg_has_xt (opnds[0].sysins_op))
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{
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set_other_error (mismatch_detail, idx, _("missing register"));
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return 0;
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@ -2756,6 +2758,12 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
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#endif
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#define F_ARCHEXT 0x2 /* Architecture dependent system register. */
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#ifdef F_HASXT
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#undef F_HASXT
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#endif
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#define F_HASXT 0x4 /* System instruction register <Xt>
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operand. */
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/* TODO there are two more issues need to be resolved
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1. handle read-only and write-only system registers
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@ -3244,77 +3252,83 @@ const aarch64_sys_ins_reg aarch64_sys_regs_ic[] =
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{
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{ "ialluis", CPENS(0,C7,C1,0), 0 },
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{ "iallu", CPENS(0,C7,C5,0), 0 },
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{ "ivau", CPENS(3,C7,C5,1), 1 },
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{ "ivau", CPENS (3, C7, C5, 1), F_HASXT },
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{ 0, CPENS(0,0,0,0), 0 }
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};
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const aarch64_sys_ins_reg aarch64_sys_regs_dc[] =
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{
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{ "zva", CPENS(3,C7,C4,1), 1 },
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{ "ivac", CPENS(0,C7,C6,1), 1 },
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{ "isw", CPENS(0,C7,C6,2), 1 },
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{ "cvac", CPENS(3,C7,C10,1), 1 },
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{ "csw", CPENS(0,C7,C10,2), 1 },
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{ "cvau", CPENS(3,C7,C11,1), 1 },
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{ "civac", CPENS(3,C7,C14,1), 1 },
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{ "cisw", CPENS(0,C7,C14,2), 1 },
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{ "zva", CPENS (3, C7, C4, 1), F_HASXT },
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{ "ivac", CPENS (0, C7, C6, 1), F_HASXT },
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{ "isw", CPENS (0, C7, C6, 2), F_HASXT },
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{ "cvac", CPENS (3, C7, C10, 1), F_HASXT },
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{ "csw", CPENS (0, C7, C10, 2), F_HASXT },
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{ "cvau", CPENS (3, C7, C11, 1), F_HASXT },
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{ "civac", CPENS (3, C7, C14, 1), F_HASXT },
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{ "cisw", CPENS (0, C7, C14, 2), F_HASXT },
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{ 0, CPENS(0,0,0,0), 0 }
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};
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const aarch64_sys_ins_reg aarch64_sys_regs_at[] =
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{
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{ "s1e1r", CPENS(0,C7,C8,0), 1 },
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{ "s1e1w", CPENS(0,C7,C8,1), 1 },
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{ "s1e0r", CPENS(0,C7,C8,2), 1 },
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{ "s1e0w", CPENS(0,C7,C8,3), 1 },
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{ "s12e1r", CPENS(4,C7,C8,4), 1 },
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{ "s12e1w", CPENS(4,C7,C8,5), 1 },
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{ "s12e0r", CPENS(4,C7,C8,6), 1 },
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{ "s12e0w", CPENS(4,C7,C8,7), 1 },
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{ "s1e2r", CPENS(4,C7,C8,0), 1 },
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{ "s1e2w", CPENS(4,C7,C8,1), 1 },
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{ "s1e3r", CPENS(6,C7,C8,0), 1 },
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{ "s1e3w", CPENS(6,C7,C8,1), 1 },
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{ "s1e1r", CPENS (0, C7, C8, 0), F_HASXT },
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{ "s1e1w", CPENS (0, C7, C8, 1), F_HASXT },
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{ "s1e0r", CPENS (0, C7, C8, 2), F_HASXT },
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{ "s1e0w", CPENS (0, C7, C8, 3), F_HASXT },
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{ "s12e1r", CPENS (4, C7, C8, 4), F_HASXT },
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{ "s12e1w", CPENS (4, C7, C8, 5), F_HASXT },
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{ "s12e0r", CPENS (4, C7, C8, 6), F_HASXT },
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{ "s12e0w", CPENS (4, C7, C8, 7), F_HASXT },
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{ "s1e2r", CPENS (4, C7, C8, 0), F_HASXT },
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{ "s1e2w", CPENS (4, C7, C8, 1), F_HASXT },
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{ "s1e3r", CPENS (6, C7, C8, 0), F_HASXT },
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{ "s1e3w", CPENS (6, C7, C8, 1), F_HASXT },
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{ 0, CPENS(0,0,0,0), 0 }
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};
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const aarch64_sys_ins_reg aarch64_sys_regs_tlbi[] =
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{
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{ "vmalle1", CPENS(0,C8,C7,0), 0 },
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{ "vae1", CPENS(0,C8,C7,1), 1 },
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{ "aside1", CPENS(0,C8,C7,2), 1 },
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{ "vaae1", CPENS(0,C8,C7,3), 1 },
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{ "vae1", CPENS (0, C8, C7, 1), F_HASXT },
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{ "aside1", CPENS (0, C8, C7, 2), F_HASXT },
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{ "vaae1", CPENS (0, C8, C7, 3), F_HASXT },
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{ "vmalle1is", CPENS(0,C8,C3,0), 0 },
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{ "vae1is", CPENS(0,C8,C3,1), 1 },
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{ "aside1is", CPENS(0,C8,C3,2), 1 },
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{ "vaae1is", CPENS(0,C8,C3,3), 1 },
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{ "ipas2e1is", CPENS(4,C8,C0,1), 1 },
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{ "ipas2le1is",CPENS(4,C8,C0,5), 1 },
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{ "ipas2e1", CPENS(4,C8,C4,1), 1 },
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{ "ipas2le1", CPENS(4,C8,C4,5), 1 },
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{ "vae2", CPENS(4,C8,C7,1), 1 },
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{ "vae2is", CPENS(4,C8,C3,1), 1 },
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{ "vae1is", CPENS (0, C8, C3, 1), F_HASXT },
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{ "aside1is", CPENS (0, C8, C3, 2), F_HASXT },
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{ "vaae1is", CPENS (0, C8, C3, 3), F_HASXT },
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{ "ipas2e1is", CPENS (4, C8, C0, 1), F_HASXT },
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{ "ipas2le1is",CPENS (4, C8, C0, 5), F_HASXT },
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{ "ipas2e1", CPENS (4, C8, C4, 1), F_HASXT },
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{ "ipas2le1", CPENS (4, C8, C4, 5), F_HASXT },
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{ "vae2", CPENS (4, C8, C7, 1), F_HASXT },
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{ "vae2is", CPENS (4, C8, C3, 1), F_HASXT },
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{ "vmalls12e1",CPENS(4,C8,C7,6), 0 },
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{ "vmalls12e1is",CPENS(4,C8,C3,6), 0 },
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{ "vae3", CPENS(6,C8,C7,1), 1 },
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{ "vae3is", CPENS(6,C8,C3,1), 1 },
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{ "vae3", CPENS (6, C8, C7, 1), F_HASXT },
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{ "vae3is", CPENS (6, C8, C3, 1), F_HASXT },
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{ "alle2", CPENS(4,C8,C7,0), 0 },
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{ "alle2is", CPENS(4,C8,C3,0), 0 },
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{ "alle1", CPENS(4,C8,C7,4), 0 },
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{ "alle1is", CPENS(4,C8,C3,4), 0 },
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{ "alle3", CPENS(6,C8,C7,0), 0 },
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{ "alle3is", CPENS(6,C8,C3,0), 0 },
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{ "vale1is", CPENS(0,C8,C3,5), 1 },
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{ "vale2is", CPENS(4,C8,C3,5), 1 },
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{ "vale3is", CPENS(6,C8,C3,5), 1 },
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{ "vaale1is", CPENS(0,C8,C3,7), 1 },
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{ "vale1", CPENS(0,C8,C7,5), 1 },
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{ "vale2", CPENS(4,C8,C7,5), 1 },
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{ "vale3", CPENS(6,C8,C7,5), 1 },
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{ "vaale1", CPENS(0,C8,C7,7), 1 },
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{ "vale1is", CPENS (0, C8, C3, 5), F_HASXT },
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{ "vale2is", CPENS (4, C8, C3, 5), F_HASXT },
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{ "vale3is", CPENS (6, C8, C3, 5), F_HASXT },
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{ "vaale1is", CPENS (0, C8, C3, 7), F_HASXT },
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{ "vale1", CPENS (0, C8, C7, 5), F_HASXT },
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{ "vale2", CPENS (4, C8, C7, 5), F_HASXT },
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{ "vale3", CPENS (6, C8, C7, 5), F_HASXT },
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{ "vaale1", CPENS (0, C8, C7, 7), F_HASXT },
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{ 0, CPENS(0,0,0,0), 0 }
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};
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bfd_boolean
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aarch64_sys_ins_reg_has_xt (const aarch64_sys_ins_reg *sys_ins_reg)
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{
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return (sys_ins_reg->flags & F_HASXT) != 0;
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}
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#undef C0
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#undef C1
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#undef C2
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