* ld-mips-elf/reloc-merge-lo16.d: Correct symbol
table size for __start.
2005-02-22 Eric Christopher <echristo@redhat.com>
* config/tc-mips.c (struct proc): Change isym to
func_sym. New member func_end_sym.
(s_mips_ent): Update.
(s_mips_end): Ditto. Add code to compute function size.
* config/tc-mips.c (append_insn): Call dwarf2_emit_insn() before
emitting insn.
gas/testsuite/:
* gas/mips/mips16-dwarf2.d: New test to check DWARF2 line
information for MIPS16.
* gas/mips/mips16-dwarf2.s: Source for the new test.
* gas/mips/mips.exp: Run the new test.
2005-02-17 Jan Beulich <jbeulich@novell.com>
* config/tc-ia64.c (ia64_parse_name): Don't advance 'name' when
parsing inN, locN, outN. Set 'idx' to offset register number starts
at. Don't handle numbers with leading zeroes or beyond 95. Remove
pointless cast.
gas/testsuite/
2005-02-17 Jan Beulich <jbeulich@novell.com>
* gas/ia64/nostkreg.[ds]: New.
* gas/ia64/ia64.exp: Run new test.
(macro): Don't use AT if .set noat is in effect. Fix formatting.
Catch macros which are unexpandable without AT. Remove duplicate
zeroing of used_at.
(macro2): Remove duplicate zeroing of used_at.
2005-02-15 Nigel Stephens <nigel@mips.com>
Maciej W. Rozycki <macro@mips.com>
* elf32-mips.c (elf_mips16_howto_table_rel): New array for MIPS16
reloc howtos. Add R_MIPS16_HI16 and R_MIPS16_LO16 relocs and
R_MIPS16_GOT16 and R_MIPS16_CALL16 placeholders.
(elf_mips16_jump_howto): Move into elf_mips16_howto_table_rel.
(elf_mips16_gprel_howto): Likewise. Redefine src_mask and
dst_mask.
(mips16_gprel_reloc): Remove bit shuffling; call
_bfd_mips16_elf_reloc_unshuffle(), _bfd_mips_elf_gprel16_with_gp()
and _bfd_mips16_elf_reloc_shuffle() instead.
(mips16_reloc_map): New reloc map for MIPS16 relocs.
(bfd_elf32_bfd_reloc_type_lookup): Use mips16_reloc_map for MIPS16
relocs.
(mips_elf32_rtype_to_howto): Fetch MIPS16 howtos from
elf_mips16_howto_table_rel.
* elf64-mips.c (mips16_elf64_howto_table_rel): New array for
MIPS16 REL reloc howtos. Add R_MIPS16_HI16 and R_MIPS16_LO16
relocs and R_MIPS16_GOT16 and R_MIPS16_CALL16 placeholders.
(elf_mips16_jump_howto): Move into mips16_elf64_howto_table_rel.
(elf_mips16_gprel_howto): Likewise. Redefine src_mask and
dst_mask.
(mips16_elf64_howto_table_rela): New array for MIPS16 RELA
reloc howtos. Add R_MIPS16_26, R_MIPS16_GPREL, R_MIPS16_HI16 and
R_MIPS16_LO16 relocs and R_MIPS16_GOT16 and R_MIPS16_CALL16
placeholders.
(mips16_gprel_reloc): Remove bit shuffling; call
_bfd_mips16_elf_reloc_unshuffle(), _bfd_mips_elf_gprel16_with_gp()
and _bfd_mips16_elf_reloc_shuffle() instead.
(mips16_reloc_map): New reloc map for MIPS16 relocs.
(bfd_elf64_bfd_reloc_type_lookup): Use mips16_reloc_map for MIPS16
relocs.
(mips_elf64_rtype_to_howto): Fetch MIPS16 howtos from
mips16_elf64_howto_table_rela or mips16_elf64_howto_table_rel.
* elfn32-mips.c (elf_mips16_howto_table_rel): New array for MIPS16
REL reloc howtos. Add R_MIPS16_HI16 and R_MIPS16_LO16 relocs and
R_MIPS16_GOT16 and R_MIPS16_CALL16 placeholders.
(elf_mips16_jump_howto): Move into elf_mips16_howto_table_rel.
(elf_mips16_gprel_howto): Likewise. Redefine src_mask and
dst_mask.
(mips16_gprel_reloc): Remove bit shuffling; call
_bfd_mips16_elf_reloc_unshuffle(), _bfd_mips_elf_gprel16_with_gp()
and _bfd_mips16_elf_reloc_shuffle() instead.
(mips16_reloc_map): New reloc map for MIPS16 relocs.
(bfd_elf32_bfd_reloc_type_lookup): Use mips16_reloc_map for MIPS16
relocs.
(mips_elf_n32_rtype_to_howto): Fetch MIPS16 howtos from
elf_mips16_howto_table_rela or elf_mips16_howto_table_rel.
* elfxx-mips.c (_bfd_mips16_elf_reloc_unshuffle): New function to
handle bit shuffling for MIPS16 relocs.
(_bfd_mips16_elf_reloc_shuffle): Likewise.
(_bfd_mips_elf_lo16_reloc): Use _bfd_mips16_elf_reloc_unshuffle()
and _bfd_mips16_elf_reloc_shuffle().
(_bfd_mips_elf_generic_reloc): Likewise.
(mips_elf_calculate_relocation): Likewise. Handle R_MIPS16_HI16
and R_MIPS16_LO16.
(mips_elf_obtain_contents): Remove bit shuffling.
(mips_elf_perform_relocation): Likewise; call
_bfd_mips16_elf_reloc_unshuffle() and _bfd_mips16_elf_reloc_shuffle()
instead.
(_bfd_mips_elf_relocate_section): Likewise. Handle R_MIPS16_HI16
and R_MIPS16_LO16.
* elfxx-mips.h (_bfd_mips16_elf_reloc_unshuffle): Declare.
(_bfd_mips16_elf_reloc_shuffle): Likewise.
* reloc.c (BFD_RELOC_MIPS16_HI16): New reloc.
(BFD_RELOC_MIPS16_HI16_S): Likewise.
(BFD_RELOC_MIPS16_LO16): Likewise.
* bfd-in2.h: Regenerate.
* libbfd.h: Regenerate.
gas/:
2005-02-15 Nigel Stephens <nigel@mips.com>
Maciej W. Rozycki <macro@mips.com>
* config/tc-mips.c (reloc_needs_lo_p): Handle
BFD_RELOC_MIPS16_HI16_S.
(fixup_has_matching_lo_p): Handle BFD_RELOC_MIPS16_LO16.
(append_insn): Add BFD_RELOC_MIPS16_GPREL, BFD_RELOC_MIPS16_HI16_S
and BFD_RELOC_MIPS16_LO16 to relocs to suppress overflow
complaints on.
(mips16_ip): Resolve BFD_RELOC_MIPS16_HI16_S,
BFD_RELOC_MIPS16_HI16 and BFD_RELOC_MIPS16_LO16 for constants.
Call my_getSmallExpression() to parse percent operators.
(percent_op_match, mips_percent_op): Separate definitions.
(mips16_percent_op): Define percent operators for the MIPS16 mode.
(parse_relocation): Handle the MIPS16 mode using
mips16_percent_op.
(md_apply_fix3): Handle BFD_RELOC_MIPS16_HI16,
BFD_RELOC_MIPS16_HI16_S and BFD_RELOC_MIPS16_LO16.
gas/testsuite/:
2005-02-15 Nigel Stephens <nigel@mips.com>
Maciej W. Rozycki <macro@mips.com>
* gas/mips/mips16-hilo.d: New test for the R_MIPS16_HI16 and
R_MIPS16_LO16 relocs.
* gas/mips/mips16-hilo-n32.d: Likewise, for the n32 ABI.
* gas/mips/mips16-hilo.s: Source for the new tests.
* gas/mips/mips.exp: Run the new tests.
include/:
2005-02-15 Nigel Stephens <nigel@mips.com>
Maciej W. Rozycki <macro@mips.com>
* elf/mips.h (R_MIPS16_GOT16): New reloc code.
(R_MIPS16_CALL16): Likewise.
(R_MIPS16_HI16): Likewise.
(R_MIPS16_LO16): Likewise.
(R_MIPS16_min): New fake reloc code.
(R_MIPS16_max): Likewise.
ld/testsuite/:
2005-02-15 Nigel Stephens <nigel@mips.com>
Maciej W. Rozycki <macro@mips.com>
* ld-mips-elf/mips16-hilo.d: New test for the R_MIPS16_HI16 and
R_MIPS16_LO16 relocs.
* ld-mips-elf/mips16-hilo-n32.d: Likewise, for the n32 ABI.
* ld-mips-elf/mips16-hilo.s: Auxiliary source for the new tests.
* ld-mips-elf/mips-elf.exp: Run the new tests.
2005-02-15 Jan Beulich <jbeulich@novell.com>
* config/tc-ia64.c (md_apply_fix3): Call ia64_gen_real_reloc_type
instead of explicitly dealing with the translation; exclude
relocations that are already pcrel, however.
gas/testsuite/
2005-02-15 Jan Beulich <jbeulich@novell.com>
* gas/ia64/pcrel.[ds]: New.
* gas/ia64/ia64.exp: Run new test.
2005-02-15 Jan Beulich <jbeulich@novell.com>
* config/tc-ia64.c: Include limits.h (if available).
(gr_values[0]): Set path to INT_MAX.
(dot_reg_val): Don't allow changing value of r0. Limit range of
general registers at r127.
(specify_resource): Default resource index is -1. Don't set resource
index (in case IA64_RS_RSE) without setting the specific flag.
(note_register_values): Check operand is O_constant before tracking
input value of moves. Add tracking for dep.z with constant inputs.
(print_dependency): Resource index of specific resource may be zero.
(check_dependencies): Likewise.
gas/testsuite/
2005-02-15 Jan Beulich <jbeulich@novell.com>
* gas/ia64/dv-raw-err.l: Expect specific resource for RAW violation on b0.
* gas/ia64/regval.[ls]: New.
* gas/ia64/ia64.exp: Run new test.
2005-02-15 Jan Beulich <jbeulich@novell.com>
* config/tc-ia64.c (parse_operands): New local variables reg1, reg2,
reg_class. Check operands and emit diagnostics for illegal use of
registers.
gas/testsuite/
2005-02-15 Jan Beulich <jbeulich@novell.com>
* gas/ia64/dv-raw-err.s: Don't use r0 or f0 as output operand.
* gas/ia64/dv-waw-err.s: Likewise.
* gas/ia64/reg-err.[ls]: New.
* gas/ia64/ia64.exp: Run new test.
2005-02-15 Jan Beulich <jbeulich@novell.com>
* elfxx-ia64.c (ia64_howto_table): Correct strings for
R_IA64_DTPMOD64[LM]SB.
gas/
2005-02-15 Jan Beulich <jbeulich@novell.com>
* config/tc-ia64.c (ia64_gen_real_reloc_type): Define and initialize
new variables type, suffix, and width. Handle
BFD_RELOC_IA64_DIR(32|64)[LM]SB in FUNC_LT_FPTR_RELATIVE case.
Handle BFD_RELOC_IA64_DIR64[LM]SB in FUNC_TP_RELATIVE case. Add
FUNC_DTP_MODULE case. Handle BFD_RELOC_IA64_DIR32[LM]SB in
FUNC_DTP_RELATIVE case. Return incoming relocation type if
BFD_RELOC_IA64_IPLT[LM]SB in FUNC_IPLT_RELOC case. Generate warning
if unable to translate relocation type, using the new variables.
gas/testsuite/
2005-02-15 Jan Beulich <jbeulich@novell.com>
* gas/ia64/reloc.[ds]: New.
* gas/ia64/reloc-bad.[ls]: New.
* gas/ia64/ia64.exp: Run new tests.
2005-02-15 Jan Beulich <jbeulich@novell.com>
* config/tc-ia64.c (ia64_parse_name): Only update next character if
input_line_pointer was advanced.
gas/testsuite/
2005-02-15 Jan Beulich <jbeulich@novell.com>
* gas/ia64/operand-or.d: Pass -xnone to assembler.
2005-02-13 Jan Beulich <jbeulich@novell.com>
* config/tc-ia64.c (dot_rot): Add comment that name strings should
be freed when wiping out previous state. Canonicalize names before
use. Free name string when detecting redefinition.
(dot_pred_rel): Call generic expression parser to process arguments.
Handle O_register case for individual predicates and O_subtract for
ranges.
(ia64_parse_name): Canonicalize name before looking it up in dynamic
register hash.
(ia64_canonicalize_symbol_name): Strip off all trailing # characters.
Warn if multiple found, issue error if resulting symbol name has zero
length.
(dot_alias): Canonicalize name before use.
gas/testsuite/
2005-02-13 Jan Beulich <jbeulich@novell.com>
* gas/ia64/pound.[ls]: New.
* gas/ia64/ia64.exp: Run new test.
* config/tc-ia64.c (unwind_diagnostic): Return -1 for warning
and 0 for error.
(in_procedure): Return -1 for warning.
(in_prologue): Likewise.
(in_body): Likewise.
(dot_xdata): Undo the last change. Section name is used by
set_section.
(dot_float_cons): Likewise.
(dot_xstringer): Likewise.
(dot_xdata_ua): Likewise.
(dot_float_cons_ua): Likewise.
2005-02-11 H.J. Lu <hongjiu.lu@intel.com>
* NEWS: Mention "-munwind-check=[warning|error]".
* config/tc-ia64.c (md): Add unwind_check.
(unwind_diagnostic): New.
(in_procedure): Call unwind_diagnostic when a directive isn't
in procedure.
(in_prologue): Call unwind_diagnostic when a directive isn't in
prologue.
(in_body): Call unwind_diagnostic when a directive isn't in
body region.
(dot_endp): Set md.unwind_check to error before calling
in_procedure and restore it after. When the name is missing or
couldn't be found, use the one from the last .proc if
md.unwind_check isn't error. Warn if md.unwind_check is
warning.
(md_parse_option): Handle "-munwind-check=[warning|error]".
(md_show_usage): Add "-munwind-check=[warning|error]".
(ia64_init): Set md.unwind_check to warning.
* doc/as.texinfo: Add "-munwind-check=[none|warning|error]".
* doc/c-ia64.texi: Likewise.
gas/testcase
2005-02-11 H.J. Lu <hongjiu.lu@intel.com>
* gas/ia64/ia64.exp: Pass -munwind-check=error for unwind-err
and proc.
2005-02-11 Jan Beulich <jbeulich@novell.com>
* config/tc-ia64.h (LEX_AT): Include LEX_BEGIN_NAME.
(LEX_QM): Likewise.
(ia64_parse_name): New third parameter.
(md_parse_name): Pass third argument.
* config/tc-ia64.c (pseudo_func): Placeholders use NULL as name.
(md_operand): Handling of '@'-prefixed symbols moved from here...
(ia64_parse_name): ...to here.
BFD_RELOC_UNUSED.
(do_t_push_pop): Likewise.
(md_assemble): Likewise.
(md_apply_fix3): Handle BFD_RELOC_NONE correctly, make BFD_RELOC_UNUSED
same as previous meaning of BFD_RELOC_NONE.
(create_unwind_entry): Output dependency on the required personality
routines.
testsuite/gas/arm/unwind.d: Alter expected output to include dependency
on __aeabi_unwind_cpp_pr[01].
2005-02-02 Jan Beulich <jbeulich@novell.com>
* config/tc-ia64.c (dot_pred_rel): Update comment. Handle @-prefixed
designators along with quoted ones. Free copy of quoted designator
when done.
gas/testsuite/
2005-02-02 Jan Beulich <jbeulich@novell.com>
* gas/ia64/pred-rel.s: New.
* gas/ia64/ia64.exp: Run new test.
2005-01-31 Jan Beulich <jbeulich@novell.com>
* config/tc-ia64.c (parse_operands): Parse all specified operands,
immediately discarding (but counting) those exceeding the maximum
possible amount. Track whether output and input operand counts ever
matched, and use this to better indicate which of the operands/
operand types was wrong; specifically don't default to pointing to
the first operand.
gas/testsuite/
2005-01-31 Jan Beulich <jbeulich@novell.com>
* gas/ia64/operands.[ls]: New.
* gas/ia64/ia64.exp: Run new test.
2005-01-31 Jan Beulich <jbeulich@novell.com>
* config/tc-ia64.c (unwind): Remove proc_end (now an automatic
variable in dot_endp). Add body and insn. Make prologue,
prologue_mask, body, and insn bitfields.
(fixup_unw_records): Remove spurious new-lines from end of diagnostic
messages.
(in_procedure, in_prologue, in_body): New.
(dot_fframe, dot_vframe, dot_vframesp, dot_vframepsp, dot_save,
dot_restore, dot_restorereg, dot_restorereg_p, dot_handlerdata,
dot_unwentry, dot_altrp, dot_savemem, dot_saveg, dot_savef, dot_saveb,
dot_savegf, dot_spill, dot_spillreg, dot_spillmem, dot_spillreg_p,
dot_spillmem_p, dot_label_state, dot_copy_state, dot_unwabi,
dot_personality): Use the appropriate one of the above.
(dot_proc): Clear unwind.proc_start; set to current location only if
none of the entry points were valid. Check for non-zero-length entry
point names. Check that entry points aren't defined, yet. Clear
unwind.prologue, unwind.body, and unwind.insn.
(dot_body): Call in_procedure. Check that first directive in procedure
had no insns emitted before. Set unwind.body.
(dot_prologue): Call in_procedure. Check that not already in prologue.
Check that first directive in procedure had no insns emitted before.
Clear unwind.body.
(dot_endp): Call in_procedure. Declare proc_end. Check for non-zero-
length entry point names. Check that entry points became defined.
(md_assemble): Set unwind.insn once unwind.proc_start is defined.
gas/testsuite/
2005-01-31 Jan Beulich <jbeulich@novell.com>
* gas/ia64/proc.[ls]: New.
* gas/ia64/unwind-err.[ls]: New.
* gas/ia64/ia64.exp: Run new tests.
2005-01-31 Jan Beulich <jbeulich@novell.com>
* config/tc-ia64.c (emit_one_bundle): Snapshot manual bundling state
before actually using it. Don't generate an error in manual bundling
mode when looking at an insn requiring slot 2 but not yet at slot 2.
Don't generate an error in manual bundling mode when looking at an
insn required to be last in its group but the required slot hasn't
been reached, yet. Allow conversion from MII to MI;I for bundle
consisting of only 2 insns with the stop between them. Suppress
various meaningless errors resulting from detecting earlier ones.
gas/testsuite/
2005-01-31 Jan Beulich <jbeulich@novell.com>
* gas/ia64/bundling.[ds]: New.
* gas/ia64/label.[ls]: New.
* gas/ia64/last.[ls]: New.
* gas/ia64/slot2.[ls]: New.
* gas/ia64/ia64.exp: Run new tests.
2005-01-31 Jan Beulich <jbeulich@novell.com>
* config/tc-ia64.c (parse_operands): Also handle alloc without first
input being ar.pfs.
gas/testsuite/
2005-01-31 Jan Beulich <jbeulich@novell.com>
* gas/ia64/pseudo.[ds]: New.
* gas/ia64/ia64.exp: Run new test.
opcodes/
2005-01-31 Jan Beulich <jbeulich@novell.com>
* ia64-gen.c (NELEMS): Define.
(shrink): Generate alias with missing second predicate register when
opcode has two outputs and these are both predicates.
* ia64-opc-i.c (FULL17): Define.
(ia64_opcodes_i): Add mov-to-pr alias without second input. Use FULL17
here to generate output template.
(TBITCM, TNATCM): Undefine after use.
* ia64-opc-m.c (ia64_opcodes_i): Add alloc alias without ar.pfs as
first input. Add ld16 aliases without ar.csd as second output. Add
st16 aliases without ar.csd as second input. Add cmpxchg aliases
without ar.ccv as third input. Add cmp8xchg16 aliases without ar.csd/
ar.ccv as third/fourth inputs. Consolidate through...
(CMPXCHG_acq, CMPXCHG_rel, CMPXCHG_1, CMPXCHG_2, CMPXCHG_4, CMPXCHG_8,
CMPXCHGn, CMP8XCHG16, CMPXCHG_ALL): Define.
* ia64-asmtab.c: Regenerate.
2005-01-28 Jan Beulich <jbeulich@novell.com>
* config/tc-ia64.c (ia64_estimate_size_before_relax): Allocate space
for personality routine pointer only if there is one.
(ia64_convert_frag): Likewise.
(generate_unwind_image): Likewise.
ld/testsuite/
2005-01-28 Jan Beulich <jbeulich@novell.com>
* ld/ia64/tlsbin.[rt]d: Widen expected offset/size ranges.
* ld/ia64/tlspic.[rt]d: Likewise.
(md_apply_fix3): Make relative branches out of range an error
instead of a warning. Display correct line number for out of
range branches/calls/memory accesses.
2005-01-27 Jan Beulich <jbeulich@novell.com>
* config/tc-ia64.c (emit_one_bundle): Change "?imbf??" to "?ibmfxx".
gas/testsuite/
2005-01-27 Jan Beulich <jbeulich@novell.com>
* gas/ia64/nop_x.[ds]: New.
* gas/ia64/ia64.exp: Run new test.
2005-01-25 Jan Beulich <jbeulich@novell.com>
* config/tc-ia64.c (emit_one_bundle): Add late resolution of move
to/from application registers dynamic insns.
(md_assemble): Defer resolution of move to/from application registers
dynamic insns when they can be issued on either the I- or M-units.
gas/testsuite/
2005-01-25 Jan Beulich <jbeulich@novell.com>
* gas/ia64/dv-waw-err.l: Don't expect ar112 move warning to refer to
M-unit.
* gas/ia64/mov-ar.[ds]: New.
* gas/ia64/ia64.exp: Run new test.
* config/tc-ia64.c (md): Add member "loc_directive_seen".
(dot_loc): New function.
(md_pseudo_table): Add entry to map .loc to dot_loc().
(emit_one_bundle): Only call dwarf2_gen_line_info() if we have
seen a .loc directive or we're generating DWARF2 debug info for
assembly source.
* v850.h (R_V850_LO16_SPLIT_OFFSET): New reloc.
bfd/
* reloc.c (BFD_RELOC_V850_LO16_SPLIT_OFFSET): New bfd_reloc_code_type.
* elf32-v850.c (v850_elf_howto_table): Add entry for
R_V850_LO16_SPLIT_OFFSET.
(v850_elf_reloc_map): Map it to BFD_RELOC_V850_LO16_SPLIT_OFFSET.
(v850_elf_perform_lo16_relocation): New function, extracted from...
(v850_elf_perform_relocation): ...here. Use it to handle
R_V850_LO16_SPLIT_OFFSET.
(v850_elf_check_relocs, v850_elf_final_link_relocate): Handle
R_V850_LO16_SPLIT_OFFSET.
* libbfd.h, bfd-in2.h: Regenerate.
gas/
* config/tc-v850.c (handle_lo16): New function.
(v850_reloc_prefix): Use it to check lo().
(md_assemble, md_apply_fix3): Handle BFD_RELOC_V850_LO16_SPLIT_OFFSET.
gas/testsuite/
* gas/v850/split-lo16.{s,d}: New test.
* gas/v850/v850.exp: Run it.
ld/testsuite/
* ld-v850: New directory.
2004-12-15 Jan Beulich <jbeulich@novell.com>
* config/obj-elf.c (obj_elf_change_section): Only set type and
attributes on new sections. Emit warning when type of re-declared
section doesn't match.
gas/testsuite/
2004-12-15 Jan Beulich <jbeulich@novell.com>
* gas/elf/section5.[els]: New.
* configure.in: Use it for arm*-*-linux-gnueabi*.
* config/tc-arm.c: Allow emulation file to set FPU_DEFAULT.
* config/te-armlinuxeabi.h: New file.
* Makefile.in: Regenerated.
* aclocal.m4: Likewise.
* configure: Likewise.
* doc/Makefile.in: Regenerated.
2004-11-25 Jan Beulich <jbeulich@novell.com>
* config/tc-i386.c (optimize_imm): Adjust immediates to only those
permissible for the selected instruction suffix.
(process_suffix): For DefaultSize instructions, suppressing the
guessing of a 'q' suffix if the instruction doesn't support it is
pointless, because only an 'l' suffix can be guessed in this place.
gas/testsuite/
2004-11-25 Jan Beulich <jbeulich@novell.com>
* gas/i386/x86-64-inval.[sl]: Remove sahf/lahf.
include/opcode/
2004-11-25 Jan Beulich <jbeulich@novell.com>
* i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
to/from test registers are illegal in 64-bit mode. Add missing
NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
(previously one had to explicitly encode a rex64 prefix). Re-enable
lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
They should be correct now.
* gas/mn10300/relax.s: Add further tests of the relaxing of branch instructions.
* gas/mn10300/relax.d: Add expected relocations.
2004-11-23 Jan Beulich <jbeulich@novell.com>
* config/tc-i386.h (CpuMMX2): Declare. Artificial classifier to
indicate the MMX extensions added by both SSE and 3DNow!A.
(Cpu3dnowA): Declare.
(CpuUnknownFlags): Update.
* config/tc-i386.c (cpu_sub_arch_name): Declare.
(cpu_arch): i586 and pentium do not imply MMX. i686 and pentiumpro do
neither imply SSE nor MMX. k6 implies MMX. k6_2 additionally implies
3DNow!. Athlon additionally implies 3DNow!A. Several new
entries (those starting with a dot are for sub-arch specification).
(set_cpu_arch): Handle sub-arch specifications.
(parse_insn): Distinguish between instructions not supported because
of insufficient CPU features and because of 64-bit mode.
* doc/c-i386.texi: Describe enhanced .arch directive.
include/opcode/
2004-11-23 Jan Beulich <jbeulich@novell.com>
* i386.h (i386_optab): paddq and psubq, even in their MMX form, are
available only with SSE2. Change the MMX additions introduced by SSE
and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
instructions by their now designated identifier (since combining i686
and 3DNow! does not really imply 3DNow!A).
include/ChangeLog
* xtensa-isa-internal.h (xtensa_interface_internal): Add class_id.
* xtensa-isa.h (xtensa_interface_class_id): New prototype.
bfd/ChangeLog
* xtensa-isa.c (xtensa_interface_class_id): New.
gas/ChangeLog
* config/tc-xtensa.c (finish_vinsn): Clear pending instruction if
there is a conflict.
(check_t1_t2_reads_and_writes): Check for both reads and writes to
interfaces that are related as determined by xtensa_interface_class_id.
* config/tc-xtensa.c (MAX_IMMED6): Change value to 65.
gas/testsuite/
* gas/xtensa/short_branch_offset.s: New.
* gas/xtensa/short_branch_offset.d: New.
* gas/xtensa/all.exp: Run new test.
* config/tc-crx.c: Rename argument types.
(processing_arg_number): Rename to 'cur_arg_num'.
(get_number_of_bits): Rename to 'set_operand_size'.
(get_operandtype): Rename to 'parse_operand', totally rewrite.
(set_cons_rparams): Rename to 'set_operand', totally rewrite.
(set_indexmode_parameters): Remove function, integrate its code into 'set_operand'.
(set_operand_size): Get rid of 'Operand Number' function parameter - use global variable 'cur_arg_num' instead.
Use a local 'argument' pointer to reference the current argument.
(parse_operand): Likewise.
(set_operand): Likewise.
(process_label_constant): Likewise.
DEFAULT_CRIS_ARCH. Handle crisv32-*-linux-gnu* like
cris-*-linux-gnu* and crisv32-*-* like cris-*-*.
* configure: Regenerate.
* config/tc-cris.c (enum cris_archs): New.
(cris_mach, cris_arch_from_string, s_cris_arch, get_sup_reg)
(cris_insn_ver_valid_for_arch): New functions.
(DEFAULT_CRIS_ARCH): New macro, default to cris_any_v0_v10.
(cris_arch): New variable.
(md_pseudo_table): New pseudo .arch.
(err_for_dangerous_mul_placement): Initialize according to
DEFAULT_CRIS_ARCH.
(STATE_COND_BRANCH): Renamed from STATE_CONDITIONAL_BRANCH.
All users changed.
(STATE_COND_BRANCH_V32, STATE_COND_BRANCH_COMMON)
(STATE_ABS_BRANCH_V32, STATE_LAPC, BRANCH_BF_V32, BRANCH_BB_V32)
(BRANCH_WF_V32, BRANCH_WB_V32): New.
(BRANCH_BF, BRANCH_BB, BRANCH_WF, BRANCH_WB): Don't undef after
use in md_cris_relax_table.
(md_cris_relax_table): Add entries for STATE_COND_BRANCH_V32,
STATE_COND_BRANCH_COMMON, STATE_ABS_BRANCH_V32, STATE_LAPC.
Update and improve head comment.
(OPTION_PIC): Define in terms of previous option, OPTION_US.
(OPTION_MULBUG_ABORT_ON, OPTION_MULBUG_ABORT_OFF): Similar.
(OPTION_ARCH): New.
(md_longopts): New option --march=...
(cris_any_v0_v10_long_jump_size, crisv32_long_jump_size): New
macros.
(md_long_jump_size): Initialize in terms of DEFAULT_CRIS_ARCH.
(HANDLE_RELAXABLE): New macro.
(md_estimate_size_before_relax): Use HANDLE_RELAXABLE for common
cases. Check for weak symbols and assume not relaxable. Handle
STATE_COND_BRANCH_V32, STATE_COND_BRANCH_COMMON,
STATE_ABS_BRANCH_V32, STATE_LAPC. Use new variable symbolP, not
fragP->fr_symbol.
(md_convert_frag): Handle STATE_COND_BRANCH_V32,
STATE_COND_BRANCH_COMMON, STATE_ABS_BRANCH_V32, STATE_LAPC.
(cris_create_short_jump): Adjust for CRISv32.
(md_create_long_jump): Ditto. Emit error for common_v10_v32.
(md_begin): Define symbols "..asm.arch.cris.v32",
"..asm.arch.cris.v10", "..asm.arch.cris.common_v10_v32" and
"..asm.arch.cris.any_v0_v10". Use cris_insn_ver_valid_for_arch
when entering opcode table entry points.
(md_assemble): Adjust branch handling for CRISv32. Handle LAPC
relaxation. In fix_new_exp call for main insn, pass 1 for pcrel
parameter for 8, 16 and 32-bit pc-relative insns and LAPC.
(cris_process_instruction): Initialize out_insnp->insn_type to
CRIS_INSN_NONE, not CRIS_INSN_NORMAL.
<case ']', '[', 'A', 'd', 'Q', 'N', 'n', 'Y', 'U', 'u', 'T'>: New
cases.
<case 'm'>: Check that modified_char == '.'.
<invalid operands>: Consume the rest of the line.
When operands don't match, skip over subsequent insns with
non-matching version specifier but same mnemonic.
<immediate constant, case SIZE_SPEC_REG>: Immediate operands for
special registers in CRISv32 are always 32 bit long.
<immediate constant, case SIZE_FIELD_SIGNED, SIZE_FIELD_UNSIGNED>:
New cases.
(get_gen_reg): Only recognize "PC" when followed by "+]" for v32
and compatible. Recognize "ACR" for v32, unless followed by "+".
(get_spec_reg): Consider cris_arch when looking up register.
(get_autoinc_prefix_or_indir_op): Don't recognize assignment for
v32 or compatible.
(get_3op_or_dip_prefix_op): Check for ']' after seeing '[rN+'.
(cris_get_expression): Restore input_line_pointer if failing "early".
(get_flags): Consider cris_arch and recognize flags accordingly.
(branch_disp): Adjust for CRISv32.
(gen_cond_branch_32): Similar. Emit error for common_v10_v32.
(cris_number_to_imm): Use as_bad_where, not as_bad. Remove
related FIXME. Don't insist on BFD_RELOC_32_PCREL fixup to be
resolved. Don't enter zeros in object file for
BFD_RELOC_32_PCREL.
<case BFD_RELOC_CRIS_LAPCQ_OFFSET, BFD_RELOC_CRIS_SIGNED_16>
<case BFD_RELOC_CRIS_SIGNED_8>: New case.
(md_parse_option): Break out "return 1".
<OPTION_ARCH> New case.
(tc_gen_reloc): <case BFD_RELOC_CRIS_LAPCQ_OFFSET>
<case BFD_RELOC_CRIS_SIGNED_16, BFD_RELOC_CRIS_SIGNED_8>
<case BFD_RELOC_CRIS_UNSIGNED_8, BFD_RELOC_CRIS_UNSIGNED_16>
<case BFD_RELOC_32_PCREL>: New cases.
Addends for non-zero fx_pcrel are too in fx_offset.
(md_show_usage): Show --march=<arch>.
(md_apply_fix3): Adjust val for BFD_RELOC_CRIS_LAPCQ_OFFSET.
(md_pcrel_from): BFD_RELOC_CRIS_LAPCQ_OFFSET is PC-relative too.
(s_syntax) <struct syntaxes>: Properly constify member operand.
* config/tc-cris.h (TARGET_MACH): Define.
(cris_mach): Declare.
* doc/as.texinfo (Overview) <CRIS>: Add --march=...
* doc/c-cris.texi (CRIS-Symbols): New node for built-in symbols.
(CRIS-Opts): Document --march=...
(CRIS-Pseudos): Document .arch.
2004-11-04 Jan Beulich <jbeulich@novell.com>
* config/tc-i386.c (set_intel_syntax): Allow % in symbol names when
intel syntax and no register prefix, allow $ in symbol names when
intel syntax.
(set_16bit_gcc_code_flag): Replace literal 'l' by LONG_MNEM_SUFFIX.
(intel_float_operand): Add fourth return value indicating math control
operations. Make classification more precise.
(md_assemble): Complain if memory operand of mov[sz]x has no size
specified.
(parse_insn): Translate word operands to floating point instructions
operating on integers as well as control instructions to short ones
as expected by AT&T syntax. Translate 'd' suffix to short one only for
floating point instructions operating on non-integer operands.
(match_template): Remove fldcw special case. Adjust q-suffix handling
to permit it on fild/fistp/fisttp in AT&T mode.
(process_suffix): Don't guess DefaultSize insns' suffix from
stackop_size for certain floating point control instructions. Guess
suffix for branch and [ls][gi]dt based on flag_code. Split error
messages for Intel and AT&T syntax, and make the condition more strict
for the former. Adjust suppressing of generation of operand size
overrides.
(intel parser): Allow the full set of MASM operators. Add FWORD, TBYTE,
OWORD, and XMMWORD operand size specifiers (TBYTE replaces XWORD). Add
more error checking.
* config/tc-i386.h (BYTE_PTR WORD_PTR DWORD_PTR QWORD_PTR XWORD_PTR
SHORT OFFSET_FLAT FLAT NONE_FOUND): Remove unused defines.
gas/testsuite/
2004-11-04 Jan Beulich <jbeulich@novell.com>
* gas/i386/i386.exp: Execute new tests intelbad and intelok.
* gas/i386/intelbad.[sl]: New test to check for various things not
permitted in Intel mode.
* gas/i386/intel.d, gas/i386/opcode.d, gas/i386/x86-64-opcode.d:
Adjust for change to segment register store.
* gas/i386/intelok.[sd]: New test to check various Intel mode specific
things get handled correctly.
* gas/i386/x86_64.[sd]: Remove unsupported constructs referring to
'high' and 'low' parts of an operand, which the parser previously
accepted while neither telling that it's not supported nor that it
ignored the remainder of the line following these supposed keywords.
include/opcode/
2004-11-04 Jan Beulich <jbeulich@novell.com>
* i386.h (sldx_Suf): Remove.
(FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
(q_FP): Define, implying no REX64.
(x_FP, sl_FP): Imply FloatMF.
(i386_optab): Split reg and mem forms of moving from segment registers
so that the memory forms can ignore the 16-/32-bit operand size
distinction. Adjust a few others for Intel mode. Remove *FP uses from
all non-floating-point instructions. Unite 32- and 64-bit forms of
movsx, movzx, and movd. Adjust floating point operations for the above
changes to the *FP macros. Add DefaultSize to floating point control
insns operating on larger memory ranges. Remove left over comments
hinting at certain insns being Intel-syntax ones where the ones
actually meant are already gone.
opcodes/
2004-11-04 Jan Beulich <jbeulich@novell.com>
* i386-dis.c (Eq, Edqw, indirEp, Gdq, I1): Define.
(indirEb): Remove.
(Mp): Use f_mode rather than none at all.
(t_mode, dq_mode, dqw_mode, f_mode, const_1_mode): Define. t_mode
replaces what previously was x_mode; x_mode now means 128-bit SSE
operands.
(dis386): Make far jumps and calls have an 'l' prefix only in AT&T
mode. movmskpX's, pextrw's, and pmovmskb's first operands are Gdq.
pinsrw's second operand is Edqw.
(grps): 1-bit shifts' and rotates' second operands are I1. cmpxchg8b's
operand is Eq. movntq's and movntdq's first operands are EM. s[gi]dt,
fldenv, frstor, fsave, fstenv all should also have suffixes in Intel
mode when an operand size override is present or always suffixing.
More instructions will need to be added to this group.
(putop): Handle new macro chars 'C' (short/long suffix selector),
'I' (Intel mode override for following macro char), and 'J' (for
adding the 'l' prefix to far branches in AT&T mode). When an
alternative was specified in the template, honor macro character when
specified for Intel mode.
(OP_E): Handle new *_mode values. Correct pointer specifications for
memory operands. Consolidate output of index register.
(OP_G): Handle new *_mode values.
(OP_I): Handle const_1_mode.
(OP_ESreg, OP_DSreg): Generate pointer specifications. Indicate
respective opcode prefix bits have been consumed.
(OP_EM, OP_EX): Provide some default handling for generating pointer
specifications.
