Commit graph

25 commits

Author SHA1 Message Date
Mike Frysinger
d320201dbe sim: mn10300: drop global callback handle
It's used in one place and can easily be replaced by using the sim state.
2015-11-22 00:53:23 -05:00
Mike Frysinger
61a0c964e6 sim: syscall: unify memory helpers
Almost every port implements these two callbacks in the same way, so
unify them in the common layer.
2015-06-17 13:19:51 -04:00
Mike Frysinger
926b1cd8cf sim: mn10300: delete unused memory code
Only one place used get_word/put_word, so inline the usage there.
All the rest is dead code so trim it.
2015-06-11 10:13:49 -04:00
Mike Frysinger
96eaf29ec4 sim: mn10300: delete unused exception/exited/debug state
The syscall path was the only code checking the custom exception state
after recent cleanups.  Once we change that to the common engine halt
function, we can delete that state entirely.

This also helps highlight some other dead code that we can cull.
2015-06-11 07:29:16 -04:00
Mike Frysinger
b0e4c8a581 sim: mn10300: use common size types
No point in open coding this logic here when we have common size types
already that give the right answer.
2015-06-11 07:20:57 -04:00
Mike Frysinger
5d19c36612 sim: m68hc11/mn10300/v850: delete redundant INLINE defines
The sim-inline.h header already takes care of this for us, so punt
the local definitions.
2015-06-11 07:17:12 -04:00
Alexandre Oliva
c76b4bab30 2000-08-07 Graham Stott <grahams@cygnus.co.uk>
* am33-2.igen (fmadd, fmsub, fmnadd, fmnsub): Correct typo.
2000-05-29  Alexandre Oliva  <aoliva@cygnus.com>
* interp.c (fpu_disabled_exception, fpu_unimp_exception,
fpu_check_signal_exception): Take additional state arguments.
Print exception type and call program_interrupt.  Adjust callers.
(fpu_rsqrt, fpu_cmp, fpu_add, fpu_sub, fpu_mul, fpu_div,
fpu_fmadd, fpu_fmsub, fpu_fnmadd, fpu_fnmsub): Take additional
arguments.
* mn10300_sim.h (fpu_disabled_exception, fpu_unimp_exception,
fpu_check_signal_exception): Adjust prototypes.
(fpu_rsqrt, fpu_cmp, fpu_add, fpu_sub, fpu_mul, fpu_div,
fpu_fmadd, fpu_fmsub, fpu_fnmadd, fpu_fnmsub): Likewise.
* am33-2.igen: Adjust calls.
2000-05-19  Alexandre Oliva  <aoliva@cygnus.com>
* op_utils.c (cmp2fcc): Moved...
* interp.c: ... here.
2000-05-18  Alexandre Oliva  <aoliva@cygnus.com>
* am33-2.igen: Use `unsigned32', `signed32', `unsigned64' or
`signed64' where type width is relevant.
2000-05-15  Alexandre Oliva  <aoliva@cygnus.com>
* mn10300_sim.h: Include sim-fpu.h.
(FD2FPU, FPU2FD): Enclose the FD argument in parentheses.
(fpu_check_signal_exception): Declare.
(struct fp_prec_t, fp_single_prec, fp_double_prec): Likewise.
(FP_SINGLE, FP_DOUBLE): Shorthands for fp_*_prec.
(fpu_rsqrt, fpu_cmp, fpu_add, fpu_sub, fpu_mul, fpu_div,
fpu_fmadd, fpu_fmsub, fpu_fnmadd, fpu_fnmsub): Declare.
* interp.c (fpu_disabled_exception): Document.
(fpu_unimp_exception): Likewise.
(fpu_check_signal_exception): Define.
(reg2val_32, round_32, val2reg_32, fp_single_prec): Likewise.
(reg2val_64, round_64, val2reg_64, fp_double_prec): Likewise.
(REG2VAL, ROUND, VAL2REG): Define shorthands.
(fpu_status_ok): Define.
(fpu_rsqrt, fpu_cmp, fpu_add, fpu_sub, fpu_mul, fpu_div,
fpu_fmadd, fpu_fmsub, fpu_fnmadd, fpu_fnmsub): Define.
* am33-2.igen (frsqrt, fcmp, fadd, fsub, fmul, fdiv,
fmadd, fmsub, fnmadd, fnmsub): Use new functions.
2000-04-27  Alexandre Oliva  <aoliva@cygnus.com>
* interp.c (sim_create_inferior): Set PSW bit to enable FP insns
if architecture is AM33/2.0.
* am33.igen: Include am33-2.igen.
2000-04-23  Alexandre Oliva  <aoliva@cygnus.com>
* mn10300.igen (movm, call, ret, retf): Check for am33_2 too.
* am33.igen (movm): Likewise.
2000-04-19  Alexandre Oliva  <aoliva@cygnus.com>
* am33.igen: Added `*am33_2' to some instructions that were
missing it.
2000-04-07  Alexandre Oliva  <aoliva@cygnus.com>
* am33-2.igen: New file.  All insns implemented, but FP flags are
only set for fcmp, exceptional conditions are not handled yet.
* Makefile.in (IGEN_INSN): Added am33-2.igen.
(tmp-igen): Added -M am33_2.
* mn10300.igen, am33.igen: Added `*am33_2' to all insns.
* gencode.c: Support FMT_D3.
* mn10300_sim.h (dword): New type.
(struct _state): Added fpregs.
(REG_FPCR, FPCR): New define.  All assorted bitmaps.
(XS2FS, AS2FS, Xf2FD): New macros.
(FS2FPU, FD2FPU, FPU2FS, FPU2FD): Likewise.
(load_dword, store_dword): New functions or macros.
(u642dw, dw2u64): New functions.
(fpu_disabled_exception, fpu_unimp_exception): Declared.
* interp.c (fpu_disabled_exception): Defined; no actual
implementation.
(fpu_unimp_exception): Likewise.
* op_utils.c (cmp2fcc): New function.
2004-06-26 22:18:18 +00:00
Alexandre Oliva
489503ee33 * interp.c, mn10300_sim.h, op_utils.c: Convert function prototypes
and definitions to ISO C.
2004-06-26 21:53:47 +00:00
Alexandre Oliva
599e0b9e0d * configure.in: Use common simulator always. Don't subst sim_gen
nor mn10300_common.
* configure: Rebuilt.
* Makefile.in (WITHOUT_COMMON_OBJS, WITHOUT_COMMON_INTERP_DEP,
WITHOUT_COMMON_RUN_OBJS): Remove.
(WITH_COMMON_OBJS): Rename to MN10300_OBJS.
(WITH_COMMON_INTERP_DEP): Rename to MN10300_INTERP_DEP.
(WITH_COMMON_RUN_OBJS): Rename to SIM_RUN_OBJS.
(SIM_EXTRA_CFLAGS): Don't use @sim_gen@.
* interp.c: Remove non-common bits.
* mn10300_sim.h: Likewise.
2004-06-26 18:45:53 +00:00
Andrew Cagney
3c25f8c7b0 Move include/callback.h and include/remote-sim.h to include/gdb/.
Update accordingly.
2002-06-09 15:45:54 +00:00
Alexandre Oliva
24a39d88a2 * mn10300_sim.h (genericAdd, genericSub, genericCmp, genericOr,
genericXor, genericBtst): Use `unsigned32'.
* op_utils.c: Likewise.
* mn10300.igen, am33.igen: Use `unsigned32', `signed32',
`unsigned64' or `signed64' where type width is relevant.
2000-05-18 22:56:28 +00:00
Jason Molenda
c2d11a7da0 import gdb-1999-12-06 snapshot 1999-12-07 03:56:43 +00:00
Stan Shebs
c906108c21 Initial creation of sourceware repository 1999-04-16 01:35:26 +00:00
Stan Shebs
071ea11e85 Initial creation of sourceware repository 1999-04-16 01:34:07 +00:00
Jeff Law
a6cbaa652a * mn10300_sim.h: Include bfd.h
(struct state): Add more room for processor specific registers.
start-sanitize-am33
        (REG_E0): Define.
end-sanitize-am33
1998-06-30 17:28:54 +00:00
Andrew Cagney
e855e57637 Pacify GCC. 1998-03-25 00:08:52 +00:00
Joyce Janczyn
13e0e254dc New {load/store}_{byte/half/word} macros for simulator built with
common framework.
1998-03-24 20:11:44 +00:00
Jeff Law
8def922034 * mn10300_sim.h: Fix ordering of bits in the PSW. 1997-05-06 19:42:17 +00:00
Jeff Law
26e9f63c11 * mn10300_sim.h (struct _state): Add space for mdrq register.
(REG_MDRQ): Define.
        * simops.c: Don't abort for trap.  Add support for the extended
        instructions, "getx", "putx", "mulq", "mulqu", "sat16", "sat24",
        and "bsch".
1997-05-06 00:35:42 +00:00
Jeff Law
b774c0e4b1 * mn10300_sim.h (struct _state): Put all registers into a single
array to make gdb implementation easier.
        (REG_*): Add definitions for all registers in the state array.
        (SEXT32, SEXT40, SEXT44, SEXT60): Remove unused macros.
        * simops.c: Related changes.
1996-12-31 23:26:11 +00:00
Jeff Law
d252301029 * gencode.c (write_header): Add "insn" and "extension" arguments
to the OP_* declarations.
        (write_template): Similarly for function templates.
        * interp.c (insn, extension): Remove global variables.  Instead
        pass them as arguments to the OP_* functions.
        * mn10300_sim.h: Remove decls for "insn" and "extension".
        * simops.c (OP_*): Accept "insn" and "extension" as arguments
        instead of using globals.
Starting to clean things up.
1996-12-06 21:19:37 +00:00
Jeff Law
92284aaa35 * mn10300_sim.h (_state): Add another register (MDR).
(REG_MDR): Define.
        * simops.c: Implement "cmp", "calls", "rets", "jmp" and
        a few additional random insns.
We can now function calls.  We get out of crt0 into main now, then lose
when calls are nested (because don't handle movm yet).
1996-11-27 00:53:25 +00:00
Jeff Law
73e6529893 * mn10300_sim.h (PSW_*): Define for CC status tracking.
(REG_D0, REG_A0, REG_SP): Define.
        * simops.c: Implement "add", "addc" and a few other random
        instructions.
Starting to simulate instructions for the mn10300.  Executes some of
the crt0 code now!
1996-11-26 22:58:24 +00:00
Jeff Law
b5f831ac51 * gencode.c, interp.c: Snapshot current simulator code.
(crude) hashing works, along with dispatch to the OP_* functions.
1996-11-26 20:40:19 +00:00
Jeff Law
05ccbdfdd2 * Makefile.in, config.in, configure, configure.in: New files.
* gencode.c, interp.c, mn10300_sim.h, simops.c: New files.

Skeleton mn10300 simulator
1996-11-25 19:52:08 +00:00