Commit graph

3572 commits

Author SHA1 Message Date
Joel Brobecker
17d88f73c0 Switch erc32 simulator copyright headers to FSF.
Permission was granted by Jiri Gaisler, who has a copyright assignment
on file for GDB.

sim/erc32/ChangeLog:

        * configure.ac: Add copyright header.
        * erc32.c: Change copyright holder to FSF.  Reformat.
        * exec.c, float.c, func.c, interf.c, sis.c, sis.h: Likewise.
        * help.c, startsim: Add copyright header.
2015-05-08 07:23:15 -07:00
DJ Delorie
0952813b0b Make RL78 disassembler and simulator respect ISA for mul/div
[gas]
	* config/rl78-defs.h (rl78_isa_g10): New.
	(rl78_isa_g13): New.
	(rl78_isa_g14): New.
	* config/rl78-parse.y (ISA_G10): New.
	(ISA_G13): New.
	(ISA_G14): New.
	(MULHU, MULH, MULU, DIVHU, DIVWU, MACHU, MACH): Use them.
	* config/tc-rl78.c (rl78_isa_g10): New.
	(rl78_isa_g13): New.
	(rl78_isa_g14): New.

[gdb]
	* rl78-tdep.c (rl78_analyze_prologue): Pass RL78_ISA_DEFAULT to
	rl78_decode_opcode

[include]
	* dis-asm.h (print_insn_rl78_g10): New.
	(print_insn_rl78_g13): New.
	(print_insn_rl78_g14): New.
	(rl78_get_disassembler): New.
	* opcode/rl78.h (RL78_Dis_Isa): New.
	(rl78_decode_opcode): Add ISA parameter.

[opcodes]
	* disassemble.c (disassembler): Choose suitable disassembler based
	on E_ABI.
	* rl78-decode.opc (rl78_decode_opcode): Take ISA parameter.  Use
	it to decode mul/div insns.
	* rl78-decode.c: Regenerate.
	* rl78-dis.c (print_insn_rl78): Rename to...
	(print_insn_rl78_common): ...this, take ISA parameter.
	(print_insn_rl78): New.
	(print_insn_rl78_g10): New.
	(print_insn_rl78_g13): New.
	(print_insn_rl78_g14): New.
	(rl78_get_disassembler): New.

[sim]
	* rl78/cpu.c (g14_multiply): New.
	* rl78/cpu.h (g14_multiply): New.
	* rl78/load.c (rl78_load): Decode ISA completely.
	* rl78/main.c (main): Expand -M to include other ISAs.
	* rl78/rl78.c (decode_opcode): Decode based on ISA.
	* rl78/trace.c (rl78_disasm_fn): New.
	(sim_disasm_init): Reset it.
	(sim_disasm_one): Get correct disassembler for ISA.
2015-04-30 15:25:49 -04:00
Nick Clifton
0a13382c8e Fix problems in the sim sources discovered by running the cppcheck static analysis tool.
erc32	PR 18273
	* sis.c (main): Remove unreachable code.

m68hc11	* gencode.c (gen_fetch_operands): Remove unreachable code.

ppc	* hw_htab.c (htab_map_binary): Fix overlap check.

common	* sim-fpu.c (INLINE_SIM_FPU): Fix static analysis warning by
	increasing parenthesis around casts to signed values.
2015-04-29 16:02:02 +01:00
Senthil Kumar Selvaraj
180d40b903 sim: avr: Fix 'multiple definition of sim_{read,write}'
This patch does whatever was done in
https://sourceware.org/ml/gdb-patches/2015-04/msg00437.html to fix
broken gdb build for the AVR target.
2015-04-27 09:54:37 -04:00
Nick Clifton
de7669bfa5 Fix typos in sim sources exposed by static analysis.
bfin	PR 18273
	* bfin-sim.c (decode_dsp32alu_0): Remove spurious check for
	s == 1.

erc32	PR 18273
	* exec.c (add32): Fix typo in check for overflow.

igen	PR 18273
	* misc.c (a2i): Fix typos checking for uppercase letters.
2015-04-24 15:43:21 +01:00
Nick Clifton
63c72d1ae4 Fix typo in check for valid register number in RX sim.
PR sim/18273
	* reg.c (put_reg): Fix check for valid register number.
2015-04-24 15:31:36 +01:00
Mike Frysinger
43236bb255 sim: mcore: clean up printf warnings
These printf statements are showing "word" objects which are typedefed
from long, so make sure to use l with %x when printing them to avoid
warnings from gcc.
2015-04-21 03:10:16 -04:00
Mike Frysinger
f63036b811 sim: mcore: convert to common memory/verbose functions
Re-use the existing memory core that handles reads/writes.

The verbose command is converted to the common --verbose flag
since only a few call sites use it now.
2015-04-21 03:10:16 -04:00
Mike Frysinger
e53e5aab53 sim: mcore: drop watchpoint/dumpmem/clearstats support
In preparation for converting to the common memory framework, the custom
commands get in our way.  But when we realize that gdb support has been
dropped for mcore, it makes things a bit easier: the main runner does not
let you run arbitrary commands once simulation starts.

So lets disable watchpoint support until it can be converted to the common
watchpoint logic.  There's already an ifdef to let us do that.

We straight up drop support for the dumpmem command (no other sim supports
this, and if it's a feature people want, we can add a common func) and the
clearstats command (not a big deal -- just restart your simulation).

We leave in place the verbose check points as a follow up commit will cut
that over to common logic.
2015-04-21 03:10:16 -04:00
Mike Frysinger
767e68f1b9 sim: mcore: switch to common syscall handling
Now that libgloss has a header tracking the syscalls for this arch, we
can update the database to include it for the symbolic constants/maps.
Then we can switch the mcore syscall callbacks over to the common ones.
2015-04-21 03:10:16 -04:00
Mike Frysinger
248d23e82b sim: gennltvals.sh: handle split out newlib source tree
Since newlib no longer shares the same repo as binutils/gdb, we have to go
searching further afield to locate the sources.  We still look at the top
level for newlib, but if that is not found, we also try up one dir outside
of this source tree.  It sucks, but better than the status quo (no workie).
2015-04-21 03:10:16 -04:00
Jiri Gaisler
d3e9b40afb sim/erc32: Switched emulated memory to host endian order.
Change data ordering in emulated memory from target order (big endian)
to host order. Improves performance and simplifies most memory
operations. Requires some byte twisting during stores on little
endian hosts (intel). Also removed support for little-endian binaries.
2015-04-19 02:29:44 -04:00
Mike Frysinger
3ebe2863f7 sim: clean up duplicate sim-engine hooks
Now that we've unified sim-cpu, we can delete the duplicate sim-engine
hooks -- these targets defined these only because they didn't fully
implement the sim-cpu callbacks.
2015-04-18 04:40:27 -04:00
Mike Frysinger
e8d3a34fee sim: trim old USING_SIM_BASE_H define
This doesn't appear to have been used since 1998, but wasn't cleaned
up since.  So much for being "quick" ;).
2015-04-18 04:32:56 -04:00
Mike Frysinger
20bca71d82 sim: unify SIM_CPU definition
Since every target typedefs this the same way, move it to the common code.

We have to leave Blackfin behind here for now because of inter-dependencies
on types and headers: sim-base.h includes sim-model.h which needs types in
machs.h which needs types in bfim-sim.h which needs SIM_CPU.
2015-04-18 04:31:36 -04:00
Mike Frysinger
7e83aa92f2 sim: unify sim_cia definition
Almost every target defines sim_cia the same way -- either using the
address_word type directly, or a type of equivalent size.  The only
odd one out is sh64 (who has 32bit address_word and 64bit cia), and
even that case doesn't seem to make sense.  We'll put off clean up
though of sh64 and at least set up a sensible default for everyone.
2015-04-18 04:14:38 -04:00
Mike Frysinger
c85fc61074 sim: microblaze: switch to common memory functions
Re-use the existing memory core that handles reads/writes.

This drops support for the dumpmem command, but gdb itself has
support for dumping memory regions.

The verbose command is converted to the common --verbose flag
since only two call sites use it now.

Support for the clearstats command is dropped entirely, but no
other sim really does this, and the same thing can be done by
reloading.  If it's important (clearing cycle stats) to someone,
we can add a common function for it.
2015-04-17 03:15:43 -04:00
Mike Frysinger
034685f9ce sim: replace CIA_{GET,SET} with CPU_PC_{GET,SET}
The CIA_{GET,SET} macros serve the same function as CPU_PC_{GET,SET}
except the latter adds a layer of indirection via the sim state.  This
lets models set up different functions at runtime and doesn't reach so
directly into the arch-specific cpu state.

It also doesn't make sense to have two sets of macros that do exactly
the same thing, so lets standardize on the one that gets us more.
2015-04-17 02:44:30 -04:00
Mike Frysinger
27b97b40bc sim: arm/cr16/d10v/h8300/microblaze/sh: fill out sim-cpu pc fetch/store helpers
This makes the common sim-cpu logic work.
2015-04-17 02:22:16 -04:00
Mike Frysinger
4c0cab1e21 sim: avr/mcore/moxie: fill out sim-cpu pc fetch/store helpers
This makes the common sim-cpu logic work.
2015-04-16 02:13:50 -04:00
Mike Frysinger
78e9aa70fe sim: unify sim-cpu usage
Now that all the targets are utilizing CPU_PC_{FETCH,STORE}, and the
cpu state is multicore, and the STATE_CPU defines match, we can move
it all to the common code.
2015-04-15 02:19:52 -04:00
Mike Frysinger
f95f4ed2c4 sim: cris/frv/h8300/iq2000/lm32/m32r/sh64: standardize cpu state
This sets up the sim_state structure and the cpu member to match what we
do in most other sims, and what the common code suggests.  This is a step
to unifying on the sim-cpu.o object.
2015-04-15 01:25:32 -04:00
Mike Frysinger
887bddbcad sim: ppc: fix up version script
The common sim code has switched to using gdb directly; update the
ppc copy too.
2015-04-13 23:17:53 -04:00
Mike Frysinger
bf12d44ee0 sim: fix the PKGVERSION define
This should be SIM, not GDB.
2015-04-13 02:41:10 -04:00
Mike Frysinger
a542beff94 sim: options: add --version support
The old run frontend had a --version option, but the new common
sim-options file does not.  Restore support for that so we can
get version info out of `run` when using the new frontend.
2015-04-13 02:35:26 -04:00
Mike Frysinger
8c32ba2233 sim: switch to gdb version script
Since the local create-version.sh already points directly into the gdb
source tree, we might as well use the gdb script directly too.
2015-04-13 02:32:58 -04:00
Mike Frysinger
64f14c9707 sim: mn10300: convert to sim-cpu
Make cpu allocation fully dynamic so we can leverage the common
sim-cpu and its APIs.
2015-04-13 02:13:48 -04:00
Mike Frysinger
14c9ad2edb sim: v850: convert to sim-cpu
Make cpu allocation fully dynamic so we can leverage the common
sim-cpu and its APIs.
2015-04-13 02:11:50 -04:00
Mike Frysinger
7bebb329bb sim: mips: convert to sim-cpu
Make cpu allocation fully dynamic so we can leverage the common
sim-cpu and its APIs.
2015-04-13 02:09:55 -04:00
Mike Frysinger
bea3f671c5 sim: m68hc11: convert to sim-cpu
Make cpu allocation fully dynamic so we can leverage the common
sim-cpu and its APIs.
2015-04-13 02:07:23 -04:00
Mike Frysinger
8ac57fbde4 sim: mips: fix prototype warnings
Convert a bunch of old style prototypes and tweak various casts
to match the function signatures.
2015-04-13 02:01:11 -04:00
Mike Frysinger
65f9096890 sim: ft32: fix ft32_pc_get logic 2015-04-13 01:54:33 -04:00
Hans-Peter Nilsson
a9d9677441 Do unset_currtarget_info ldscript for all simulator testsuites.
sim/testsuite:
	* sim-defs.exp (sim_init): Unset target ldscript here.

sim/testsuite/sim/mips:
	* basic.exp: Don't unset target ldscript here.
2015-04-13 01:56:04 +02:00
Mike Frysinger
e787f858a4 sim: arm/mips: fix sim_read/sim_write linkage errors
With sim-hrw.o being built & linked in the common list, some people are
getting linking errors now for these targets.  Move the main objects that
provide these functions before the common list to avoid that.
2015-04-12 05:47:39 -04:00
Mike Frysinger
29f1a5934a sim: ft32: delete sim_read/sim_write funcs
The common sim-hrw.o provides both of these, so simply use them.
2015-04-12 05:13:23 -04:00
Mike Frysinger
122bbfb52a sim: move sim-engine.o/sim-hrw.o to the common list
This makes these two objects available to all sims by default.
2015-04-06 23:56:47 -04:00
Mike Frysinger
20cc975360 sim: moxie: fix running after nrun conversion
The nrun conversion was slightly incorrect in how it stopped when an
exception occurred.  We still set cpu.asregs.exception, but nothing
was checking it anymore.  Convert all of that to sim_engine_halt.

To keep things from regressing again, add a basic testsuite too.
2015-04-05 04:37:44 -04:00
Mike Frysinger
024305f7f2 sim: mn10300: add a basic testsuite 2015-04-05 03:52:08 -04:00
Mike Frysinger
aad84fa6ae sim: m68hc11: add a basic testsuite 2015-04-05 03:17:44 -04:00
Mike Frysinger
eed64ce675 sim: iq2000: add a basic testsuite 2015-04-05 02:28:44 -04:00
Mike Frysinger
e56dbbb92f sim: lm32: add a basic testsuite 2015-04-05 01:58:00 -04:00
Mike Frysinger
b366059a5b sim: d10v: fix signal updates
Way back in aba6488e0b, a bunch of signal
defines were changed to TARGET_SIGNAL_xxx.  For d10v, the transition was
incomplete which lead to sim_stop_reason using the new set but sim_resume
still using the old set.  Which meant in some cases, the sim would never
actually stop.

Convert all the remaining SIGxxx defines in here to TARGET_SIGNAL_xxx.
This has the nice side effect of fixing the testsuite.
2015-04-02 20:40:11 -04:00
H.J. Lu
7fed4b0be6 Regenerate configure in sim
* arm/configure: Regenerated.
	* avr/configure: Likewise.
	* bfin/configure: Likewise.
	* common/configure: Likewise.
	* cr16/configure: Likewise.
	* cris/configure: Likewise.
	* d10v/configure: Likewise.
	* erc32/configure: Likewise.
	* frv/configure: Likewise.
	* ft32/configure: Likewise.
	* h8300/configure: Likewise.
	* igen/configure: Likewise.
	* iq2000/configure: Likewise.
	* lm32/configure: Likewise.
	* m32c/configure: Likewise.
	* m32r/configure: Likewise.
	* m68hc11/configure: Likewise.
	* mcore/configure: Likewise.
	* microblaze/configure: Likewise.
	* mips/configure: Likewise.
	* mn10300/configure: Likewise.
	* moxie/configure: Likewise.
	* msp430/configure: Likewise.
	* ppc/configure: Likewise.
	* rl78/configure: Likewise.
	* rx/configure: Likewise.
	* sh/configure: Likewise.
	* sh64/configure: Likewise.
	* v850/configure: Likewise.
2015-04-02 05:43:07 -07:00
Mike Frysinger
1a8faa2aa6 sim: clean up SIM_EXTRA_OBJS references
This variable was deleted in previous commits and is not used anymore.
Prune any stray references to it.
2015-04-02 00:51:40 -04:00
H.J. Lu
79730a3b26 Fix sim build
* common/Make-common.in (CSEARCH): Remove $(ZLIBINC).
	(BFD_LIB): Remove $(ZLIB).
	(CONFIG_LIBS): Add $(ZLIB).
	* ppc/Makefile.in (ZLIBINC): Removed.
	(INCLUDES): Remove $(ZLIBINC).
	(BFD_LIB): Remove $(ZLIB).
2015-04-01 10:27:43 -07:00
H.J. Lu
0ceaf1ec96 Regenerate configure in sim
* arm/configure: Regenerated.
	* avr/configure: Likewise.
	* bfin/configure: Likewise.
	* common/configure: Likewise.
	* cr16/configure: Likewise.
	* cris/configure: Likewise.
	* d10v/configure: Likewise.
	* erc32/configure: Likewise.
	* frv/configure: Likewise.
	* ft32/configure: Likewise.
	* h8300/configure: Likewise.
	* igen/configure: Likewise.
	* iq2000/configure: Likewise.
	* lm32/configure: Likewise.
	* m32c/configure: Likewise.
	* m32r/configure: Likewise.
	* m68hc11/configure: Likewise.
	* mcore/configure: Likewise.
	* microblaze/configure: Likewise.
	* mips/configure: Likewise.
	* mn10300/configure: Likewise.
	* moxie/configure: Likewise.
	* msp430/configure: Likewise.
	* ppc/configure: Likewise.
	* rl78/configure: Likewise.
	* rx/configure: Likewise.
	* sh/configure: Likewise.
	* sh64/configure: Likewise.
	* v850/configure: Likewise.
2015-04-01 10:15:13 -07:00
Mike Frysinger
269e9c185f sim: m32c: enable warnings & clean up a bunch
This doesn't clean up all the warnings, just most of them.
The ones that are left will require some care to unravel.
2015-04-01 02:22:58 -04:00
Mike Frysinger
0fe84f3fbe sim: run: punt!
Now that all targets have been converted to nrun, we can finally punt
this old inconsistent interface.

A few stray references to the old run were sprinkled about; clean them
up in the process.

We leave behind the run(1) man page mostly so that we get it updated for
the new nrun interface.
2015-04-01 01:22:44 -04:00
Mike Frysinger
aadc9410ba sim: update zlib handling
With zlib being mandatory, and the updated m4 configs, we need to regen
and use the new settings w/bfd to avoid linkage errors.
2015-04-01 01:07:57 -04:00
Mike Frysinger
b38f7f340b sim: cr16/d10v: restore generated headers dep
While cleaning up stale make rules, one too many were deleted.  The
build system autogenerates static rules, but not generated files.
2015-03-31 01:59:44 -04:00