sim: microblaze: switch to common memory functions
Re-use the existing memory core that handles reads/writes. This drops support for the dumpmem command, but gdb itself has support for dumping memory regions. The verbose command is converted to the common --verbose flag since only two call sites use it now. Support for the clearstats command is dropped entirely, but no other sim really does this, and the same thing can be done by reloading. If it's important (clearing cycle stats) to someone, we can add a common function for it.
This commit is contained in:
Mike Frysinger
parent
034685f9ce
commit
c85fc61074
4 changed files with 33 additions and 332 deletions
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@ -1,3 +1,23 @@
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2015-04-17 Mike Frysinger <vapier@gentoo.org>
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* interp.c (issue_messages, wbat, wlat, what, rbat, rlat, rhat,
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sim_memory_size, MEM_SIZE_FLOOR, sim_size, init_pointers, sim_write,
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sim_read, sim_do_command): Delete.
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(set_initial_gprs): Delete memsize and call to init_pointers.
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(sim_resume): Change rlat to MEM_RD_WORD. Change issue_messages to
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STATE_VERBOSE_P.
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(sim_store_register, sim_fetch_register): Drop call to init_pointers.
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(sim_open): Drop issue_messages setup. Delete osize and call to
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sim_size. Call sim_do_commandf to set the memory size.
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* microblaze.h (MEM): Delete.
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(MEM_RD_BYTE): Change rbat to sim_core_read_1.
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(MEM_RD_HALF): Change rhat to sim_core_read_2.
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(MEM_RD_WORD): Change rlat to sim_core_read_4.
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(MEM_WR_BYTE): Change wbat to sim_core_write_1.
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(MEM_WR_HALF): Change what to sim_core_write_2.
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(MEM_WR_WORD): Change wlat to sim_core_write_4.
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* sim-main.h (microblaze_regset): Delete msize and memory.
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2015-04-17 Mike Frysinger <vapier@gentoo.org>
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* sim-main.h (CIA_GET, CIA_SET): Delete.
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@ -89,240 +89,16 @@ microblaze_store_unsigned_integer (unsigned char *addr, int len,
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}
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}
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/* TODO: Convert to common tracing framework. */
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static int issue_messages = 0;
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static void /* INLINE */
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wbat (SIM_CPU *cpu, word x, word v)
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{
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if (((uword)x) >= CPU.msize)
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{
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if (issue_messages)
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fprintf (stderr, "byte write to 0x%x outside memory range\n", x);
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CPU.exception = SIGSEGV;
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}
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else
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{
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unsigned char *p = CPU.memory + x;
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p[0] = v;
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}
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}
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static void /* INLINE */
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wlat (SIM_CPU *cpu, word x, word v)
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{
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if (((uword)x) >= CPU.msize)
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{
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if (issue_messages)
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fprintf (stderr, "word write to 0x%x outside memory range\n", x);
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CPU.exception = SIGSEGV;
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}
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else
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{
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if ((x & 3) != 0)
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{
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if (issue_messages)
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fprintf (stderr, "word write to unaligned memory address: 0x%x\n", x);
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CPU.exception = SIGBUS;
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}
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else if (!target_big_endian)
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{
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unsigned char *p = CPU.memory + x;
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p[3] = v >> 24;
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p[2] = v >> 16;
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p[1] = v >> 8;
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p[0] = v;
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}
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else
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{
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unsigned char *p = CPU.memory + x;
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p[0] = v >> 24;
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p[1] = v >> 16;
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p[2] = v >> 8;
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p[3] = v;
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}
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}
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}
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static void /* INLINE */
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what (SIM_CPU *cpu, word x, word v)
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{
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if (((uword)x) >= CPU.msize)
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{
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if (issue_messages)
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fprintf (stderr, "short write to 0x%x outside memory range\n", x);
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CPU.exception = SIGSEGV;
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}
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else
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{
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if ((x & 1) != 0)
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{
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if (issue_messages)
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fprintf (stderr, "short write to unaligned memory address: 0x%x\n",
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x);
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CPU.exception = SIGBUS;
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}
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else if (!target_big_endian)
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{
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unsigned char *p = CPU.memory + x;
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p[1] = v >> 8;
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p[0] = v;
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}
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else
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{
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unsigned char *p = CPU.memory + x;
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p[0] = v >> 8;
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p[1] = v;
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}
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}
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}
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/* Read functions. */
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static int /* INLINE */
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rbat (SIM_CPU *cpu, word x)
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{
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if (((uword)x) >= CPU.msize)
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{
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if (issue_messages)
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fprintf (stderr, "byte read from 0x%x outside memory range\n", x);
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CPU.exception = SIGSEGV;
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return 0;
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}
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else
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{
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unsigned char *p = CPU.memory + x;
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return p[0];
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}
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}
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static int /* INLINE */
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rlat (SIM_CPU *cpu, word x)
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{
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if (((uword) x) >= CPU.msize)
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{
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if (issue_messages)
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fprintf (stderr, "word read from 0x%x outside memory range\n", x);
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CPU.exception = SIGSEGV;
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return 0;
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}
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else
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{
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if ((x & 3) != 0)
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{
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if (issue_messages)
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fprintf (stderr, "word read from unaligned address: 0x%x\n", x);
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CPU.exception = SIGBUS;
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return 0;
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}
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else if (! target_big_endian)
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{
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unsigned char *p = CPU.memory + x;
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return (p[3] << 24) | (p[2] << 16) | (p[1] << 8) | p[0];
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}
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else
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{
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unsigned char *p = CPU.memory + x;
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return (p[0] << 24) | (p[1] << 16) | (p[2] << 8) | p[3];
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}
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}
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}
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static int /* INLINE */
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rhat (SIM_CPU *cpu, word x)
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{
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if (((uword)x) >= CPU.msize)
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{
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if (issue_messages)
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fprintf (stderr, "short read from 0x%x outside memory range\n", x);
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CPU.exception = SIGSEGV;
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return 0;
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}
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else
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{
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if ((x & 1) != 0)
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{
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if (issue_messages)
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fprintf (stderr, "short read from unaligned address: 0x%x\n", x);
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CPU.exception = SIGBUS;
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return 0;
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}
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else if (!target_big_endian)
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{
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unsigned char *p = CPU.memory + x;
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return (p[1] << 8) | p[0];
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}
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else
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{
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unsigned char *p = CPU.memory + x;
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return (p[0] << 8) | p[1];
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}
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}
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}
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/* TODO: Delete all sim_size and use common memory functions. */
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/* Default to a 8 Mbyte (== 2^23) memory space. */
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static int sim_memory_size = 1 << 23;
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#define MEM_SIZE_FLOOR 64
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static void
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sim_size (SIM_CPU *cpu, int size)
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{
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sim_memory_size = size;
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CPU.msize = sim_memory_size;
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if (CPU.memory)
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free (CPU.memory);
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CPU.memory = (unsigned char *) calloc (1, CPU.msize);
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if (!CPU.memory)
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{
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if (issue_messages)
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fprintf (stderr,
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"Not enough VM for simulation of %ld bytes of RAM\n",
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CPU.msize);
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CPU.msize = 1;
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CPU.memory = (unsigned char *) calloc (1, 1);
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}
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}
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static void
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init_pointers (SIM_CPU *cpu)
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{
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if (CPU.msize != (sim_memory_size))
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sim_size (cpu, sim_memory_size);
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}
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static void
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set_initial_gprs (SIM_CPU *cpu)
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{
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int i;
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long space;
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unsigned long memsize;
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init_pointers (cpu);
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/* Set up machine just out of reset. */
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PC = 0;
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MSR = 0;
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memsize = CPU.msize / (1024 * 1024);
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if (issue_messages > 1)
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fprintf (stderr, "Simulated memory of %ld Mbytes (0x0 .. 0x%08lx)\n",
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memsize, CPU.msize - 1);
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/* Clean out the GPRs */
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for (i = 0; i < 32; i++)
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CPU.regs[i] = 0;
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@ -365,7 +141,7 @@ sim_resume (SIM_DESC sd, int step, int siggnal)
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do
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{
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/* Fetch the initial instructions that we'll decode. */
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inst = rlat (cpu, PC & 0xFFFFFFFC);
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inst = MEM_RD_WORD (PC & 0xFFFFFFFC);
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op = get_insn_microblaze (inst, &imm_unsigned, &insn_type,
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&num_delay_slot);
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@ -439,7 +215,7 @@ sim_resume (SIM_DESC sd, int step, int siggnal)
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{
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newpc = PC;
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PC = oldpc + INST_SIZE;
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inst = rlat (cpu, PC & 0xFFFFFFFC);
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inst = MEM_RD_WORD (PC & 0xFFFFFFFC);
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op = get_insn_microblaze (inst, &imm_unsigned, &insn_type,
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&num_delay_slot);
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if (op == invalid_inst)
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@ -452,14 +228,14 @@ sim_resume (SIM_DESC sd, int step, int siggnal)
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/* immword = IMM_W; */
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if (op == microblaze_brk)
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{
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if (issue_messages)
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if (STATE_VERBOSE_P (sd))
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fprintf (stderr, "Breakpoint set in delay slot "
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"(at address 0x%x) will not be honored\n", PC);
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/* ignore the breakpoint */
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}
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else if (insn_type == branch_inst || insn_type == return_inst)
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{
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if (issue_messages)
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if (STATE_VERBOSE_P (sd))
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fprintf (stderr, "Cannot have branch or return instructions "
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"in delay slot (at address 0x%x)\n", PC);
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CPU.exception = SIGILL;
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@ -522,41 +298,11 @@ sim_resume (SIM_DESC sd, int step, int siggnal)
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CPU.cycles += memops; /* and memop cycle delays */
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}
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int
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sim_write (SIM_DESC sd, SIM_ADDR addr, const unsigned char *buffer, int size)
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{
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SIM_CPU *cpu = STATE_CPU (sd, 0);
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int i;
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init_pointers (cpu);
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memcpy (&CPU.memory[addr], buffer, size);
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return size;
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}
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int
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sim_read (SIM_DESC sd, SIM_ADDR addr, unsigned char *buffer, int size)
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{
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SIM_CPU *cpu = STATE_CPU (sd, 0);
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int i;
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init_pointers (cpu);
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memcpy (buffer, &CPU.memory[addr], size);
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return size;
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}
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int
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sim_store_register (SIM_DESC sd, int rn, unsigned char *memory, int length)
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{
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SIM_CPU *cpu = STATE_CPU (sd, 0);
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init_pointers (cpu);
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if (rn < NUM_REGS + NUM_SPECIAL && rn >= 0)
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{
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if (length == 4)
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@ -582,8 +328,6 @@ sim_fetch_register (SIM_DESC sd, int rn, unsigned char *memory, int length)
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SIM_CPU *cpu = STATE_CPU (sd, 0);
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long ival;
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init_pointers (cpu);
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if (rn < NUM_REGS + NUM_SPECIAL && rn >= 0)
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{
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if (length == 4)
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@ -709,25 +453,20 @@ sim_open (SIM_OPEN_KIND kind, host_callback *cb, struct bfd *abfd, char **argv)
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return 0;
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}
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if (kind == SIM_OPEN_STANDALONE)
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issue_messages = 1;
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/* CPU specific initialization. */
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for (i = 0; i < MAX_NR_PROCESSORS; ++i)
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{
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SIM_CPU *cpu = STATE_CPU (sd, i);
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int osize = sim_memory_size;
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CPU_PC_FETCH (cpu) = microblaze_pc_get;
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CPU_PC_STORE (cpu) = microblaze_pc_set;
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set_initial_gprs (cpu);
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/* Discard and reacquire memory -- start with a clean slate. */
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sim_size (cpu, 1); /* small */
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sim_size (cpu, osize); /* and back again */
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}
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/* Default to a 8 Mbyte (== 2^23) memory space. */
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sim_do_commandf (sd, "memory-size 0x800000");
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return sd;
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}
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@ -746,57 +485,3 @@ sim_create_inferior (SIM_DESC sd, struct bfd *prog_bfd, char **argv, char **env)
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return SIM_RC_OK;
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}
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void
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sim_do_command (SIM_DESC sd, const char *cmd)
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{
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SIM_CPU *cpu = STATE_CPU (sd, 0);
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/* Nothing there yet; it's all an error. */
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if (cmd != NULL)
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{
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char ** simargv = buildargv (cmd);
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if (strcmp (simargv[0], "dumpmem") == 0)
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{
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unsigned char * p;
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FILE * dumpfile;
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if (simargv[1] == NULL)
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fprintf (stderr, "Error: missing argument to dumpmem cmd.\n");
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fprintf (stderr, "Writing dumpfile %s...",simargv[1]);
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dumpfile = fopen (simargv[1], "w");
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p = CPU.memory;
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fwrite (p, CPU.msize-1, 1, dumpfile);
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fclose (dumpfile);
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fprintf (stderr, "done.\n");
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}
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else if (strcmp (simargv[0], "clearstats") == 0)
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{
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CPU.cycles = 0;
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CPU.insts = 0;
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}
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else if (strcmp (simargv[0], "verbose") == 0)
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{
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issue_messages = 2;
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}
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else
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{
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fprintf (stderr,"Error: \"%s\" is not a valid M.CORE simulator command.\n",
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cmd);
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}
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freeargv (simargv);
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}
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else
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{
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fprintf (stderr, "M.CORE sim commands: \n");
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fprintf (stderr, " dumpmem <filename>\n");
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fprintf (stderr, " clearstats\n");
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fprintf (stderr, " verbose\n");
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}
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}
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@ -52,18 +52,16 @@
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#define RETREG CPU.regs[3]
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#define MEM(X) memory[X]
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#define MEM_RD_BYTE(X) rbat(cpu, X)
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#define MEM_RD_HALF(X) rhat(cpu, X)
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#define MEM_RD_WORD(X) rlat(cpu, X)
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#define MEM_RD_BYTE(X) sim_core_read_1 (cpu, 0, read_map, X)
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#define MEM_RD_HALF(X) sim_core_read_2 (cpu, 0, read_map, X)
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#define MEM_RD_WORD(X) sim_core_read_4 (cpu, 0, read_map, X)
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#define MEM_RD_UBYTE(X) (ubyte) MEM_RD_BYTE(X)
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#define MEM_RD_UHALF(X) (uhalf) MEM_RD_HALF(X)
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#define MEM_RD_UWORD(X) (uword) MEM_RD_WORD(X)
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#define MEM_WR_BYTE(X, D) wbat(cpu, X, D)
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#define MEM_WR_HALF(X, D) what(cpu, X, D)
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#define MEM_WR_WORD(X, D) wlat(cpu, X, D)
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#define MEM_WR_BYTE(X, D) sim_core_write_1 (cpu, 0, write_map, X, D)
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#define MEM_WR_HALF(X, D) sim_core_write_2 (cpu, 0, write_map, X, D)
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#define MEM_WR_WORD(X, D) sim_core_write_4 (cpu, 0, write_map, X, D)
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#define MICROBLAZE_SEXT8(X) ((char) X)
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@ -45,8 +45,6 @@ typedef struct _sim_cpu SIM_CPU;
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int cycles;
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int insts;
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int exception;
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unsigned long msize;
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unsigned char *memory;
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ubyte imm_enable;
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half imm_high;
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};
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