as synonyms for "rN" registers.
(xr_registers): Add mcrh, mcrl, mcvf, mdrq and sp as synonyms
for "xrN" registers.
(md_assemble): Fix typo computing the size of relocations.
* config/tc-mn10300.c (r_registers): Add missing registers.
(xr_registers): New set of registers.
(xr_register_name): New function.
(md_assemble): Handle XRREG and PLUS operands. Tweak handling of
RREG operand insertion. Handle new D6 and D7 instruction formats.
end-sanitize-am33
* config/tc-mn10300.c (mn10300_insert_operand): Do not hardcode the
shift amount for a repeated operand. The shift amount for the
repeated copy comes from the size of the operand.
other than their native tongues.
Wed Jun 17 14:02:10 1998 Frank Ch. Eigler <fche@cygnus.com>
* gas/mips/delay.d: Add -mcpu=NNNN to gas flags to let test case
run on differently targeted assembler.
* gas/mips/{ld-ilocks-addr32,ld-svr4pic.d}: Ditto.
* gas/mips/{ld-xgot.d,lif-svr4pic.d,lif-xgot.d}: Same.
* gas/mips/{mips16.d,mips4.d,nodelay.d}: Again.
* gas/mips/{trunc.d,uld.d,ulh-xgot.d,usd.d}: And then some.
* gas/mips/ld-ilocks.d: Removed disassembler flags to let target
defaults go unmodified. Replaced $f4/$f5 with $fp[45], as the
original `ld.d' had. Find `ld.s'.
* gas/mips/mul-ilocks.d: Nearly ditto.
* app.c (do_scrub_begin): If tc_symbol_chars is defined, treat all
characters in it as LEX_IS_SYMBOL_COMPONENT.
* config/tc-i386.h (tc_symbol_chars): Define.
(extra_symbol_chars): Declare.
* config/tc-i386.c (extra_symbol_chars): Define.
(comment_chars): Don't use '/' as comment start if TE_LINUX.
(line_comment_chars): Set to '/' if TE_LINUX.
* doc/c-i386.texi (i386-prefixes): Update.
* doc/internals.texi (CPU backend): Document tc_symbol_chars.
* config/tc-i386.h: Change Data16 to Size16, Data32 to Size32,
IgnoreDataSize to IgnoreSize as they are used for address size as
well as data size.
* config/tc-i386.c: Likewise. Add code to reject addr32/data32 in
32-bit mode, similarly addr16/data16 and variants.
* config/tc-i386.c: REPNE renamed to REPNE_PREFIX_OPCODE, and
likewise for REPE.
* config/tc-i386.c (reloc): Add braces.
* config/tc-i386.c (struct _i386_insn): Rename bi to sib to be
consistent with Intel naming.
* config/tc-i386.h (base_index_byte): Rename to sib_byte. Don't
use bitfields in sib_byte.
(modrm_byte): Don't use bitfields here either.
* config/tc-i386.c (current_templates): Add const.
(parse_register): Add const to return, param, and char *s.
(i386_operand): Add const to reg_entry *r.
* config/tc-i386.h (templates): Add const to start, end.
Inspired by code for 16 bit gas support from Martynas Kunigelis
<martynas@nm3.ktu.lt>:
* config/tc-i386.c (md_assemble): Add full support for 16 bit
modrm, and Jump, JumpByte, JumpDword, JumpInterSegment insns.
(uses_mem_addrmode): Remove.
(md_estimate_size_before_relax): Add support here too.
(md_relax_table): Rewrite interface to md_relax for 16 bit
support.
(BYTE, WORD, DWORD, UNKNOWN_SIZE): Remove.
(opcode_suffix_to_type): Remove.
(CODE16, SMALL, SMALL16, BIG, BIG16): Define.
(SIZE_FROM_RELAX_STATE): Modify to suit above.
(md_convert_frag): Likewise.
(i386_operand): Add support for 16 bit base/index regs,
immediates, and displacements. Remove some unnecessary casts, and
localise end_of_operand_string, displacement_string_start,
displacement_string_end variables. Add GCC_ASM_O_HACK.
* config/tc-i386.h (NO_BASE_REGISTER_16): Define.
* config/tc-i386.c (prefix_hash): Remove.
(md_begin): Rewrite without obstacks. Remove prefix hash table
handling. Rewrite lexical table handling.
(i386_print_statistics): Don't print prefix statistics.
(md_assemble): Rewrite instruction parser so that line is not
converted to lower case. Don't do a hash_find for prefixes,
instead recognise them via opcode modifier.
(expecting_operand, paren_not_balanced): Localise variables.
* config/tc-i386.h (IsPrefix): Define.
(prefix_entry): Remove.
* config/tc-i386.h (PREFIX_SEPERATOR): Don't define.
* config/tc-i386.c (PREFIX_SEPARATOR): Define here instead, using
'\\' in case where comment_chars contains '/'.
* config/tc-i386.c (MATCH): Ensure given operand and template
match for JumpAbsolute. Makes e.g. `ljmp table(%ebx)' invalid;
you must write `ljmp *table(%ebx)'.
From H.J. Lu <hjl@gnu.org>:
* config/tc-i386.c (BFD_RELOC_16, BFD_RELOC_16_PCREL): Define
as 0 ifndef BFD_ASSEMBLER.
(md_assemble): Allow immediate operands without suffix or
other reg operand to default in size to the current code size.
* config/tc-i386.c (mode_from_disp_size): Disp16 is mode 2.
(i386_operand): Simplify checks for valid base/index combinations.
Disallow `in 4(%dx),%al'.
* config/tc-i386.c (struct _i386_insn): Make regs, base_reg, and
index_reg const.
(add_prefix): Change parameter from char to int.
* config/tc-i386.h (Ugh): Define opcode modifier.
* config/tc-i386.c (md_assemble): Print warnings for Ugh insns.
* config/tc-i386.c (md_assemble): Rewrite MATCH and
CONSISTENT_REGISTER_MATCH macros to check register types more
thoroughly. Check for illegal suffix/operand combinations
when matching insns with operands. Handle new `s' suffix, and
associated FloatMF opcode modifier for float insns with memory
operands.
* config/tc-i386.h (FloatMF): Define new opcode modifier.
(No_sSuf, No_bSuf, No_wSuf, No_lSuf): Likewise.
(SHORT_OPCODE_SUFFIX, LONG_OPCODE_SUFFIX): Define.
* config/tc-i386.c: Rename WORD_PREFIX_OPCODE to
DATA_PREFIX_OPCODE throughout.
* config/tc-i386.c (REGISTER_WARNINGS): Define.
(md_assemble): Rewrite suffix/register operand checking code to be
more thorough. Remove Abs8,16,32. Change occurrences of Mem to
AnyMem, the better to grep.
(pi): Remove Abs.
(i386_operand): Don't set Mem bits in i.types[this_operand] when
given a memory operand. Don't set Abs bits either.
(type_names): Remove Mem*, Abs*.
* config/tc-i386.h (Mem8, Mem16, Mem32, Abs8, Abs16, Abs32): Don't
define opcode_modifiers as these cases are handled by Disp8,
Disp16, Disp32 and suffix checks.
(COMES_IN_BOTH_DIRECTIONS): Remove.
(FloatR): Define. It's OK to share the bit with ReverseRegRegmem.
* config/tc-i386.c (md_assemble): Don't emit operand size prefix
if IgnoreDataSize modifier given. Remove ShortformW modifier
test. Add test for ShortForm in W base_opcode modification.
Merge Seg2ShortForm and Seg3ShortForm code.
* config/tc-i386.h (ShortFormW): Remove.
(IgnoreDataSize): Define.
* gas/m68k/operands.s: For all pc relative addresses change tstl
to pea since the former does not allow pcrel on m68000. Do not
make label foo global, so that references to it can be relaxed on
ELF targets.
* gas/m68k/operands.d, gas/m68k/op68000.d: Updated.
* config/tc-i386.c (END_STRING_AND_SAVE): Protect arguments of
macros and enclose in do while(0).
(RESTORE_END_STRING): Likewise.
(md_assemble): Add one to printed operand number so we start
from 1 not 0. Add some more gettext invocations.
(i386_operand): Fix `%%s' -> `%%%s'. Inc printed operand
number here too.
* config/tc-i386.h (WAIT_PREFIX, LOCKREP_PREFIX, ADDR_PREFIX,
DATA_PREFIX, SEG_PREFIX): Define.
* config/tc-i386.c (struct _i386_insn): Remove wait_prefix field.
(check_prefix): Remove function.
(add_prefix): New function. Add prefix to i.prefix as well as
doing checks.
(md_assemble): Changes for add_prefix. Remove hack for wait
prefix, instead always output prefixes in fixed order. Test
for jcxz/loop when selecting between word & dword operations,
and add address size prefix rather than operand size prefix.
Remove operand -> address size hack when emitting jcxz/loop.
(i386_operand): Remove O_Absent check as it's done in expr.
* config/tc-m68k.c (md_estimate_size_before_relax): Add more calls
to relaxable_symbol to prevent references to external symbol from
being relaxed.
Wed Jun 3 14:10:36 1998 Ian Lance Taylor <ian@cygnus.com>
* config/tc-m68k.c (relaxable_symbol): If TARGET_OS is "elf", all
symbols are relaxable.
* macro.c (macro_mri_mode): New function.
* macro.h (macro_mri_mode): Declare.
* read.c (s_mri): Call macro_mri_mode when switching in and out of
MRI mode.
* config/tc-vax.c (md_create_short_jump): Fix off by two bug in
offset calculation. Also, use VAX_BRW from vax-inst.h instead
of hardcoded magic number.
(md_create_long_jump): Use VAX_JMP and VAX_ABSOLUTE_MODE macros.
* gas/mips/mips.exp: The r5900 has ilocks and gpr_ilocks.
* gas/mips/div-ilocks.d: Handle both "break" instruction variants.
* gas/mips/{div.d, mul-ilocks.d, mul.d}: Likewise.
(VUOVERLAY_SECTION_PREFIX,VUOVERLAY_TABLE_SECTION_NAME): Delete.
* config/tc-dvp.c (vuoverlay_string_section): New static global.
(md_begin): Create overlay string section.
(create_vuoverlay_section): Put section name in overlay string section.
Put string's offset in overlay table entry.
* config/tc-vax.c (_): Delete this macro used for placeholder
values in vax_operand_width_size; it conflicts with the _() macro
used for internationalization.
* struc-symbol.h (struct broken_word): Add seg and subseg fields.
* read.c (emit_expr): Initialize seg and subseg fields of a new
broken word.
* write.c (write_object_file): Switch to the appropriate segment
and subsegment when processing a broken word.
(dvp_frob_file): Declare.
(tc_frob_file): Define.
(VUOVERLAY_SECTION_PREFIX,VUOVERLAY_TABLE_SECTION_NAME): New macros.
* config/tc-dvp.c (VUOVERLAY_START_PREFIX): New macro.
(vuoverlay_section_name,create_vuoverlay_section): New functions.
(vuoverlay_section,vuoverlay_table_section): New static globals.
(ovlysym_table): New static global.
(md_begin): Create .vuoverlay_table section.
(assemble_vif): Call create_vuoverlay_section for each mpg.
(dvp_frob_label): Record vu labels in ovlysym_table for later
movement from absolute section to their overlay section.
(dvp_frob_file): New function.
(md_apply_fix3): For 8/16/32/64 bit relocs, only process if fx_done.
Mon May 18 12:37:38 1998 Frank Ch. Eigler <fche@cygnus.com>
* config/tc-mips.c (macro): For R5900, use "B" operand format for
"break" instructions generated in macro (div etc.) instructions.
Mon May 18 13:11:45 1998 Frank Ch. Eigler <fche@cygnus.com>
* gas/mips/{div,ld,mul}.d: Add assembler -mcpu= flag to match
disassembler.
start-sanitize-r5900
* gas/mips/break5900.[sd]: Test that break instructions generated
in div/etc. macro instructions are of 20-bit variety for R5900.
end-sanitize-r5900
* Bonus test cases to confirm behavior.
[ChangeLog]
Thu May 7 12:50:33 1998 Frank Ch. Eigler <fche@cygnus.com>
* config/tc-mips.c (validate_mips_insn): Removed hack
for previously inaccessible bitfields in some INSN_TRAP
instructions.
[testsuite/ChangeLog]
Thu May 7 13:05:25 1998 Frank Ch. Eigler <fche@cygnus.com>
* gas/mips/break20.[sd]: New tests for 20-bit operand break and
sddbp instructions.
* gas/mips/trap20.[sd]: New tests for 20-bit operand trap
instructions.
* gas/mips/mips.exp: Run them.
* cgen.c: Include it.
(MAX_FIXUPS): Renamed to CGEN_MAX_FIXUPS.
(cgen_asm_finish_insn): Result is now void. New arg `result'.
All callers updated.
* config/tc-m32r.c: Include cgen.h.
(m23r_insn): New members num_fixups,fixups.
(assemble_parallel_insn): Initialize debug_sym_link for each insn.
(md_assemble): Simplify code to pack two insns in parallel.
When swapping two insns, update their fixups.
* config/tc-m68k.h (TC_RELOC_RTSYM_LOC_FIXUP): Changed to keep
relocations against globally visible symbols.
* config/tc-m68k.c (relaxable_symbol): New macro.
(m68k_ip, md_estimate_size_before_relax): Use it.
(tc_m68k_fix_adjustable): Also handle weak symbols.
references to externally visible symbols.
* config/tc-i386.c (md_apply_fix3): When OBJ_ELF, don't add the
values in twice for a PC relative reloc if the symbol is
externally defined.
don't adjust a PC relative reloc against an externally visible
symbol.
* config/tc-sparc.c (md_apply_fix3): When generating a.out PIC,
for a PC relative fixup against an externally visible defined
symbol, arrange to store object file and addend values as though
the symbol were not defined.
(tc_gen_reloc): Likewise.
[ChangeLog]
Tue Apr 28 11:35:56 1998 Frank Ch. Eigler <fche@cygnus.com>
* ecoff.c (ecoff_build_lineno): Do not use dummy first_lineno
for line numbers for assembly source.
[testsuite/ChangeLog]
Tue Apr 28 16:38:34 1998 Frank Ch. Eigler <fche@cygnus.com>
* gas/mips/lineno.[sd]: Assembly source line number test.
* gas/mips/mips.exp: Added lineno test.
* config/tc-m32r.c (assemble_parallel_insn): No need to try
non-relaxable variant any more. Simplify test for nop insn.
(md_assemble): Only scan operands if m32rx. Set orig_insn in case
scan of operands yields an insn different from original (e.g. a macro).
Fix call to can_make_parallel.
* read.c (s_set): Cast xmalloc return value to fragS *.
* config/tc-m68k.c (m68k_ip): Function made static to match
previous forward declaration.
(insert_reg, init_regtable, md_convert_frag_1): Likewise.
* config/tc-i386.c (check_prefix): New static function, split out
from md_assemble.
(struct _i386_insn): Add wait_prefix field.
(md_assemble): Remove wait_prefix local variable. Use
check_prefix when adding a prefix.
* config/tc-i386.c (current_templates): New static variable.
(md_assemble): Remove current_templates local variable.
(md_assemble, i386_operand): Improve error and warning messages in
many places. Add RESTORE_END_STRING in many places before error
return. Clarify some comments.
* config/tc-i386.c (struct _i386_insn): Change seg field to a two
element array.
(md_assemble): Parse string instruction operands, looking for
segment override prefixes. Check for invalid segment prefixes on
string instruction.
(i386_operand): i.seg[] and max mem_operand changes for string
insns.
* config/tc-i386.h (EsSeg): Define.
* config/tc-i386.h (regKludge): Define.
(iclrKludge, imulKludge): Don't define.
* config/tc-i386.c (md_assemble): Merge imulKludge and iclrKludge
code. Move ReverseRegRegmem fudges into Modrm case. Reorder
opcode_modifier checks to look for more common cases first. Add
default_seg for IsString case.
(compute_mpgloc): New function.
(eval_expr): New arg `cpu'. All callers updated.
(non_vu_insn_seen_p): New static global.
(RELAX_{MPG,DIRECT,VU,ENCODE,GROWTH,DONE_}): New macros.
(struct dvp_fixup): New member `cpu'.
(assemble_one_insn): New args init_fixup_count, fixup_offset.
All callers updated.
(md_assemble): Set non_vu_insn_seen_p as appropriate.
(assemble_vif): Set `cpu' field of fixup.
Clean up calls to frag_var. Recorded mpgloc is now in bytes.
(assemble_vu_insn): Delete, contents moved into ...
(assemble_vu): ... here. Don't record fixups until after parsing
both upper and lower insns. If branch insn inside mpg, properly
compute target address.
(dvp_frob_label): Create copies of vu labels inside mpg's.
(dvp_relax_frag): Clean up.
(md_convert_frag): Ditto.
(md_apply_fix3): Signal error if mpg embedded vu code has branch
to undefined label (not currently supported).
(eval_expr): New arg `cpu'. All callers updated.
(insert_operand_final): Convert mpgloc from bytes to dwords.
(s_endmpg): Use compute_mpgloc to update $.mpgloc.
(s_state): If switching to vu state, initialize $.mpgloc.
