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Author SHA1 Message Date
Nick Clifton
7ba29e2a41 Add support for Xilinx MicroBlaze processor. 
* bfd/Makefile.am: Add cpu-microblaze.{lo,c}, elf32-microblaze.{lo,c}.
        * bfd/Makefile.in: Same.
        * bfd/archures.c: Add bfd_arch_microblaze.
        * bfd/bfd-in2.h: Regenerate.
        * bfd/config.bfd: Add microblaze target.
        * bfd/configure: Add bfd_elf32_microblaze_vec target.
        * bfd/configure.in: Same.
        * bfd/cpu-microblaze.c: New.
        * bfd/elf32-microblaze.c: New.
        * bfd/libbfd-in.h: Add prototype _bfd_dwarf2_fixup_section_debug_loc().
        * bfd/libbfd.h: Regenerate.
        * bfd/reloc.c: Add MICROBLAZE relocations.
        * bfd/section.c: Add struct relax_table and relax_count to section.
        * bfd/targets.c: Add bfd_elf32_microblaze_vec.
        * binutils/MAINTAINERS: Add self as maintainer.
        * binutils/readelf.c: Include elf/microblaze.h, add EM_MICROBLAZE &
        EM_MICROBLAZE_OLD to guess_is_rela(), dump_relocations(),
        get_machine_name().
        * config.sub: Add microblaze target.
        * configure: Same.
        * configure.ac: Same.
        * gas/Makefile.am: add microblaze to CPU_TYPES, config/tc-microblaze.c to
        TARGET_CPU_CFILES, config/tc-microblaze.h to TARGET_CPU_HFILES, add
        DEP_microblaze_elf target.
        * gas/Makefile.in: Same.
        * gas/config/tc-microblaze.c: Add MicroBlaze assembler.
        * gas/config/tc-microblaze.h: Add header for tc-microblaze.c.
        * gas/configure: Add microblaze target.
        * gas/configure.in: Same.
        * gas/configure.tgt: Same.
        * gas/doc/Makefile.am: Add c-microblaze.texi to CPU_DOCS.
        * gas/doc/Makefile.in: Same.
        * gas/doc/all.texi: Set MICROBLAZE.
        * gas/doc/as.texinfo: Add MicroBlaze doc links.
        * gas/doc/c-microblaze.texi: New MicroBlaze docs.
        * include/dis-asm.h: Decl print_insn_microblaze().
        * include/elf/common.h: Define EM_MICROBLAZE & EM_MICROBLAZE_OLD.
        * include/elf/microblaze.h: New reloc definitions.
        * ld/Makefile.am: Add eelf32mb_linux.o, eelf32microblaze.o to
        ALL_EMULATIONS, targets.
        * ld/Makefile.in: Same.
        * ld/configure.tgt: Add microblaze*-linux*, microblaze* targets.
        * ld/emulparams/elf32mb_linux.sh: New.
        * ld/emulparams/elf32microblaze.sh. New.
        * ld/scripttempl/elfmicroblaze.sc: New.
        * opcodes/Makefile.am: Add microblaze-opc.h to HFILES, microblaze-dis.c to
        CFILES, microblaze-dis.lo to ALL_MACHINES, targets.
        * opcodes/Makefile.in: Same.
        * opcodes/configure: Add bfd_microblaze_arch target.
        * opcodes/configure.in: Same.
        * opcodes/disassemble.c: Define ARCH_microblaze, return
        print_insn_microblaze().
        * opcodes/microblaze-dis.c: New MicroBlaze disassembler.
        * opcodes/microblaze-opc.h: New MicroBlaze opcode definitions.
        * opcodes/microblaze-opcm.h: New MicroBlaze opcode types.
 2009-08-06 17:38:04 +00:00
H.J. Lu
8a9036a406 bfd/ 
2009-07-25  H.J. Lu  <hongjiu.lu@intel.com>

	* archures.c (bfd_architecture): Add bfd_arch_l1om.
	(bfd_l1om_arch): New.
	(bfd_archures_list): Add &bfd_l1om_arch.
	* bfd-in2.h: Regenerated.

	* config.bfd (targ64_selvecs): Add bfd_elf64_l1om_vec if
	bfd_elf64_x86_64_vec is supported.  Add bfd_elf64_l1om_freebsd_vec
	if bfd_elf64_x86_64_freebsd_vec is supported.
	(targ_selvecs): Likewise.

	* configure.in: Support bfd_elf64_l1om_vec and
	bfd_elf64_l1om_freebsd_vec.
	* configure: Regenerated.

	* cpu-l1om.c: New.

	* elf64-x86-64.c (elf64_l1om_elf_object_p): New.
	(bfd_elf64_l1om_vec): Likewise.
	(bfd_elf64_l1om_freebsd_vec): Likewise.

	* Makefile.am (ALL_MACHINES): Add cpu-l1om.lo.
	(ALL_MACHINES_CFILES): Add cpu-l1om.c.
	* Makefile.in: Regenerated.

	* targets.c (bfd_elf64_l1om_vec): New.
	(bfd_elf64_l1om_freebsd_vec): Likewise.
	(_bfd_target_vector): Add bfd_elf64_l1om_vec and
	bfd_elf64_l1om_freebsd_vec.

binutils/

2009-07-25  H.J. Lu  <hongjiu.lu@intel.com>

	* readelf.c (guess_is_rela): Handle EM_L1OM.
	(dump_relocations): Likewise.
	(get_machine_name): Likewise.
	(get_section_type_name): Likewise.
	(get_elf_section_flags): Likewise.
	(get_symbol_index_type): Likewise.
	(is_32bit_abs_reloc): Likewise.
	(is_32bit_pcrel_reloc): Likewise.
	(is_64bit_abs_reloc): Likewise.
	(is_64bit_pcrel_reloc): Likewise.
	(is_none_reloc): Likewise.

gas/

2009-07-25  H.J. Lu  <hongjiu.lu@intel.com>

	* config/tc-i386.c (cpu_arch): Add l1om.
	(check_cpu_arch_compatible): New.
	(set_cpu_arch): Use it.
	(i386_arch): New.
	(i386_mach): Return bfd_mach_l1om for Intel L1OM.
	(md_show_usage): Display l1om.
	(i386_target_format): Return ELF_TARGET_L1OM_FORMAT if
	cpu_arch_isa_flags.bitfield.cpul1om is set.

	* config/tc-i386.h (TARGET_ARCH): Use (i386_arch ()).
	(i386_arch): New.
	(ELF_TARGET_L1OM_FORMAT): Likewise.

	* doc/c-i386.texi: Document l1om.

gas/testsuite/

2009-07-25  H.J. Lu  <hongjiu.lu@intel.com>

	* gas/i386/l1om.d: New.
	* gas/i386/l1om-inval.l: Likewise.
	* gas/i386/l1om-inval.s: Likewise.

	* gas/i386/i386.exp: Run l1om-inval and l1om.

include/elf/

2009-07-25  H.J. Lu  <hongjiu.lu@intel.com>

	* common.h (EM_L1OM): New.

ld/

2009-07-25  H.J. Lu  <hongjiu.lu@intel.com>

	* configure.tgt (targ64_extra_emuls): Add elf_l1om if elf_x86_64
	is supported.  Add elf_l1om_fbsd if elf_x86_64_fbsd is supported.
	(targ_extra_emuls): Likewise.

	* Makefile.am (ALL_64_EMULATIONS): Add eelf_l1om.o and
	eelf_l1om_fbsd.o
	(eelf_l1om.c): New.
	(eelf_l1om_fbsd.c): Likewise.
	* Makefile.in: Regenerated.

	* emulparams/elf_l1om.sh: New.
	* emulparams/elf_l1om_fbsd.sh: Likewise.

ld/testsuite/

2009-07-25  H.J. Lu  <hongjiu.lu@intel.com>

	* ld-x86-64/abs-l1om.d: New.
	* ld-x86-64/protected2-l1om.d: Likewise.
	* ld-x86-64/protected3-l1om.d: Likewise.

	* ld-x86-64/x86-64.exp: Run abs-l1om, protected2-l1om and
	protected3-l1om.

opcodes/

2009-07-25  H.J. Lu  <hongjiu.lu@intel.com>

	* configure.in: Handle bfd_l1om_arch.
	* disassemble.c (disassembler): Likewise.

	* configure: Regenerated.

	* i386-dis.c (print_insn): Handle bfd_mach_l1om and
	bfd_mach_l1om_intel_syntax.  Use 8 bytes per line for Intel L1OM.

	* i386-gen.c (cpu_flag_init): Set CPU_UNKNOWN_FLAGS to ~CpuL1OM.
	Add CPU_L1OM_FLAGS.
	(cpu_flags): Add CpuL1OM.
	(set_bitfield): Take an argument to set the value field.
	(process_i386_cpu_flag): Support ~CpuXXX and ~(CpuXXX|CpuYYY).
	(process_i386_opcode_modifier): Updated.
	(process_i386_operand_type): Likewise.
	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.

	* i386-opc.h (CpuL1OM): New.
	(CpuXsave): Updated.
	(i386_cpu_flags): Add cpul1om.
 2009-07-25 14:58:58 +00:00
Jan Beulich
309d33736f gas/ 
2009-07-24  Jan Beulich  <jbeulich@novell.com>

	* tc-i386.c (cpu_arch): Add .8087, .287, .387, .no87, .nommx,
	.nosse, and .noavx.
	(cpu_flags_and_not): New.
	(set_cpu_arch): Check whether sub-architecture specified is a
	feature disable.
	(md_parse_option): Likewise.
	(parse_real_register): Don't return floating point register
	when x87 functionality is disabled.
	(md_show_usage): Add new sub-options.
	* doc/c-i386.texi: Update with new command line sub-options.

gas/testsuite/
2009-07-24  Jan Beulich  <jbeulich@novell.com>

	* gas/i386/8087.[ds]: New.
	* gas/i386/287.[ds]: New.
	* gas/i386/387.[ds]: New.
	* gas/i386/no87.[ls]: New.
	* gas/i386/no87-2.[ls]: New.
	* gas/i386/i386.exp: Run new tests.
	* gas/i386/att-regs.s: Also check FPU register access.
	* gas/i386/intel-regs.s: Likewise.
	* gas/i386/att-regs.d: Adjust expectations.
	* gas/i386/intel-regs.d: Likewise.

opcodes/
2009-07-24  Jan Beulich  <jbeulich@novell.com>

	* i386-dis.c (fgrps): Correct annotation for feni/fdisi. Add
	frstpm.
	* i386-gen.c (cpu_flag_init): Add FP enabling flags where needed.
	(cpu_flags): Add Cpu8087, Cpu287, Cpu387, Cpu687, and CpuFISTTP.
	(set_bitfield): Expand CpuFP to Cpu8087|Cpu287|Cpu387.
	* i386-opc.h (Cpu8087, Cpu287, Cpu387, Cpu687, CpuFISTTP):
	Define.
	(union i386_cpu_flags): Add cpu8087, cpu287, cpu387, cpu687,
	and cpufisttp.
	* i386-opc.tbl: Qualify floating point instructions by their
	respective CpuXXX flag. Fix fucom{,p,pp}, fprem1, fsin, fcos,
	and fsincos to be avilable only on 387. Fix fstsw ax to be
	available only on 287+. Add f{,n}eni, f{,n}disi, f{,n}setpm,
	and frstpm.
	* i386-init.h, i386-tbl.h: Regenerate.
 2009-07-24 15:41:20 +00:00
Nick Clifton
7769efb28e PR 10288 
* arm-dis.c (arm_opcodes): Catch non-zero bits 8-11 in register
        offset or indexed based addressing mode 3.
 2009-07-20 12:11:18 +00:00
Nick Clifton
74bdfecf08 PR 10288 
* arm-dis.c (arm_opcodes): Catch illegal Addressing Mode 1
        patterns.
        (arm_decode_shift): Catch illegal register based shifts.
        (print_insn_arm): Properly handle negative register r0
        post-indexed addressing.
 2009-07-14 14:16:34 +00:00
Doug Kwan
d1aaab3c71 2009-07-10 Doug Kwan <dougkwan@google.com> 
* arm-disc.c (print_insn_coprocessor, print_insn_arm):  Print only
	lower 32 bits of long types to make hexadecimal output consistent
	on both 32-bit and 64-bit hosts.
 2009-07-10 16:58:54 +00:00
Alan Modra
87337981d9 Regenerate. 2009-07-10 14:20:41 +00:00
Nick Clifton
1103f72c0f gas/ 
* config/tc-arm.c (insns): Fix encoding for torvsc.

gas/testsuite/
    * gas/arm/iwmmxt2.d: Fix insn pattern for torvsc,
    add patterns for waddsubhx.
    * gas/arm/iwmmxt2.s: Add tests for waddsubhx.

opcodes/
    * arm-dis.c (coprocessor_opcodes): Fix mask for waddbhus.
 2009-07-07 16:15:32 +00:00
Nick Clifton
78c66db84c PR 10288 
* arm-dis.c (arm_opcodes): Be more strict about decoding scaled
        addressing modes.
 2009-07-07 14:46:14 +00:00
DJ Delorie
22102fb0d9 [cgen] 
* cpu/mep-core.cpu (fsft, ssarb): Mark as VOLATILE.
	* cpu/mep-ivc2.cpu (many): Add VOLATILE to more insns that make
	unspecified accesses to control registers.

[sid/component/cgen-cpu/mep]

	* mep-cop1-16-decode.cxx: Regenerate.
	* mep-cop1-16-decode.h: Regenerate.
	* mep-cop1-16-defs.h: Regenerate.
	* mep-cop1-16-model.cxx: Regenerate.
	* mep-cop1-16-model.h: Regenerate.
	* mep-cop1-16-sem.cxx: Regenerate.
	* mep-cop1-32-decode.cxx: Regenerate.
	* mep-cop1-32-decode.h: Regenerate.
	* mep-cop1-32-defs.h: Regenerate.
	* mep-cop1-32-model.cxx: Regenerate.
	* mep-cop1-32-model.h: Regenerate.
	* mep-cop1-32-sem.cxx: Regenerate.
	* mep-cop1-48-decode.cxx: Regenerate.
	* mep-cop1-48-decode.h: Regenerate.
	* mep-cop1-48-defs.h: Regenerate.
	* mep-cop1-48-model.cxx: Regenerate.
	* mep-cop1-48-model.h: Regenerate.
	* mep-cop1-48-sem.cxx: Regenerate.
	* mep-cop1-64-decode.cxx: Regenerate.
	* mep-cop1-64-decode.h: Regenerate.
	* mep-cop1-64-defs.h: Regenerate.
	* mep-cop1-64-model.cxx: Regenerate.
	* mep-cop1-64-model.h: Regenerate.
	* mep-cop1-64-sem.cxx: Regenerate.
	* mep-core1-decode.cxx: Regenerate.
	* mep-core1-decode.h: Regenerate.
	* mep-core1-defs.h: Regenerate.
	* mep-core1-model.cxx: Regenerate.
	* mep-core1-model.h: Regenerate.
	* mep-core1-sem.cxx: Regenerate.
	* mep-cpu.h: Regenerate.
	* mep-decode.cxx: Regenerate.
	* mep-decode.h: Regenerate.
	* mep-defs.h: Regenerate.
	* mep-desc.h: Regenerate.
	* mep-model.cxx: Regenerate.
	* mep-model.h: Regenerate.
	* mep-sem.cxx: Regenerate.

[opcodes]

	* mep-desc.c: Regenerate.
	* mep-desc.h: Regenerate.
	* mep-opc.c: Regenerate.
	* mep-opc.h: Regenerate.
 2009-07-07 01:56:05 +00:00
Dwarakanath Rajagopal
922d8de8c1 <gas changes> 
2009-07-06  Dwarakanath Rajagopal  <dwarak.rajagopal@amd.com>

	* config/tc-i386.c (cpu_arch): Add .fma4 and CPU_FMA4_FLAGS.
	(build_modrm_byte): Add support to handle FMA4 instructions.
	(md_show_usage): Add fma4.

<gas/testsuite changes>
2009-07-06  Dwarakanath Rajagopal  <dwarak.rajagopal@amd.com>

	* gas/i386/i386.exp: Add FMA4 tests.
	* gas/i386/x86-64-fma4.d: Ditto.
	* gas/i386/fma4.d: Ditto.
	* gas/i386/x86-64-fma4.s: Ditto.
	* gas/i386/fma4.s: Ditto.

<opcodes changes>
2009-07-06  Dwarakanath Rajagopal  <dwarak.rajagopal@amd.com>

	* i386-opc.h (CpuFMA4): Add CpuFMA4.
	(i386_cpu_flags): New.
	* i386-gen.c: Add CPU_FMA4_FLAGS.
	* i386-opc.tbl: Add FMA4 instructions.
	* i386-tbl.h: Regenerate.
	* i386-init.h: Regenerate.
	* i386-dis.c (OP_VEX_FMA): New. Handle FMA4.
	(OP_XMM_VexW): Ditto.
	(OP_EX_VexW): Ditto.
	(VEXI4_Fixup): Ditto.
	(VexI4, VexFMA, Vex128FMA, EXVexW, EXdVexW, XMVexW): New Macros.
	(PREFIX_VEX_3A5C, PREFIX_VEX_3A5D, PREFIX_VEX_3A5E): New.
	(PREFIX_VEX_3A5F, PREFIX_VEX_3A60): New.
	(PREFIX_VEX_3A68, PREFIX_VEX_3A69, PREFIX_VEX_3A6A): New.
	(PREFIX_VEX_3A6B, PREFIX_VEX_3A6C, PREFIX_VEX_3A6D): New.
	(PREFIX_VEX_3A6E, PREFIX_VEX_3A6F, PREFIX_VEX_3A7A): New.
	(PREFIX_VEX_3A7B, PREFIX_VEX_3A7C, PREFIX_VEX_3A7D): New.
	(PREFIX_VEX_3A7E, PREFIX_VEX_3A7F): New.
	(VEX_LEN_3A6A_P_2,VEX_LEN_3A6B_P_2, VEX_LEN_3A6E_P_2): New.
	(VEX_LEN_3A6F_P_2,VEX_LEN_3A7A_P_2, VEX_LEN_3A7B_P_2): New.
	(VEX_LEN_3A7E_P_2,VEX_LEN_3A7F_P_2): New.
	(get_vex_imm8): New. handle FMA4.
	(OP_EX_VexReg): Ditto.
 2009-07-06 19:34:30 +00:00
Nick Clifton
fe56b6cece PR 10288 
* arm-dis.c (coprocessor): Print the LDC and STC versions of the
        LFM and SFM instructions as comments,.
        Improve consistency of formatting for instructions displayed as
        comments and decimal values displayed with their hexadecimal
        equivalents.
        Formatting tidy ups.

        Updated expected disassembler regexps.
 2009-06-30 11:57:05 +00:00
Nick Clifton
05413229fd PR 10288 
* arm-dis.c (enum opcode_sentinels): New:  Used to mark the
        boundary between variaant and generic coprocessor instuctions.
        (coprocessor): Use it.
        Fix architecture version of MCRR and MRRC instructions.
        (arm_opcdes): Fix patterns for STRB and STRH instructions.
        (print_insn_coprocessor): Check architecture and extension masks.
        Print a hexadecimal version of any decimal constant that is
        outside of the range of -16 to +32.
        (print_arm_address): Add a return value of the offset used in the
        adress, if it is worth printing a hexadecimal version of it.
        (print_insn_neon): Print a hexadecimal version of any decimal
        constant that is outside of the range of -16 to +32.
        (print_insn_arm): Likewise.
        (print_insn_thumb16): Likewise.
        (print_insn_thumb32): Likewise.

        PR 10297
        * arm-dis.c (UNDEFINED_INSTRUCTION): New macro for a description
        of an undefined instruction.
        (arm_opcodes): Use it.
        (thumb_opcod): Use it.
        (thumb32_opc): Use it.

        Update expected disassembly regrexps in GAS and LD testsuites.
 2009-06-29 08:08:15 +00:00
DJ Delorie
dab97f2471 [cgen] 
* intrinsics.scm: Updates to support IVC2.
	(belongs-to-group?): Check IVC2 slots.
	(-slots-attribute): New.
	(targets::attributes): Add SLOTS.
	(target:add-well-known-intrinsics): Add CPMOV.
	(md-insn): Add CPTYPE and CRET?.
	(add-md-insn): Likewise.
	(add-intrinsic-for-isa): Disable the duplicate tests, as IVC2 has
	duplicate insns with different bit patterns.
	(write-cgen-insn?): Add cret? support.
	(intrinsics.h): Add vector types.
	(runtime-op): Add vector support.
	(intrinsic-protos.h): Let GCC define its types.  Add cret? support.

	* cpu/mep-core.cpu: Add CPTYPE and CRET attributes.
	* cpu/mep-ivc2.cpu: Update all insns to include type information.
	(h-cr-ivc2): Default to typeless.
	(h-ccr-ivc2): Fix register width.
	(SLOTS): Fix values and default.
	(ivc2_*): Add control register names.
	(crop, crqp, crpp, croc, crqc, crpc): Default to typeless.

[opcodes]

	* mep-desc.c: Regenerate.
	* mep-desc.h: Regenerate.
	* mep-dis.c: Regenerate.
	* mep-ibld.c: Regenerate.
	* mep-opc.c: Regenerate.

[sid/component/cgen-cpu/mep]

	* ivc2-cop.cxx (ivc2_cphadd_w): Change to return value.
	(ivc2_cpsubaca0u_b): Remove debug line.
	* ivc2-cpu.h (ivc2_cpccadd_b): Change to return value.
	* mep-cop1-16-decode.cxx: Regenerate.
	* mep-cop1-16-sem.cxx: Regenerate.
	* mep-cop1-32-decode.cxx: Regenerate.
	* mep-cop1-32-sem.cxx: Regenerate.
	* mep-cop1-48-decode.cxx: Regenerate.
	* mep-cop1-48-sem.cxx: Regenerate.
	* mep-cop1-64-decode.cxx: Regenerate.
	* mep-cop1-64-sem.cxx: Regenerate.
	* mep-core1-decode.cxx: Regenerate.
	* mep-cpu.h: Regenerate.
	* mep-decode.cxx: Regenerate.
	* mep-desc.h: Regenerate.
 2009-06-24 03:06:42 +00:00
DJ Delorie
378a0c07ca [cgen] 
* cpu/mep.opc (mep_cgen_insn_supported_asm): New, skip the short
	version of BSR when assembling VLIW bundles.  Use it in mep-asm.c

[opcodes]

	* mep-asm.c: Regenerate.
	* mep-opc.c: Regenerate.
	* mep-opc.h: Regenerate.
 2009-06-24 01:44:53 +00:00
Nick Clifton
aece7d2e74 * po/fi.po: Updated Finish translation. 2009-06-22 11:32:21 +00:00
Alan Modra
1998a8e033 cpu/ 
* m32c.opc (parse_lab_5_3): Use correct enum.
opcodes/
	* m32c-asm.c: Regenerate.
 2009-06-22 00:53:25 +00:00
Alan Modra
b33bafa0d7 * score-dis.c (print_insn_score48, print_insn_score32): Move default 
case label to proper lexical block.
	* score7-dis.c (print_insn_score32): Likewise.
 2009-06-22 00:01:57 +00:00
Martin Schwidefsky
ce21feb4ba * s390-opc.c (INSTR_RR_0R_OPT, INSTR_RX_0RRD_OPT, MASK_RR_0R_OPT, 
MASK_RX_0RRD_OPT): New instruction formats with optional arguments.
        * s390-opc.txt (nopr, nop): Use new instruction format.
 2009-06-19 10:55:42 +00:00
Nick Clifton
0313a2b8d2 PR 10288 
* arm-dis.c (print_insn_coprocessor): Check that a user specified
        ARM architecture supports the matched instruction.
        (print_insn_arm): Likewise.
        (select_arm_features): New function.  Fills in the fields of an
        arm_feature_set structure based on a given arm machine number.
        (print_insn): Initialise an arm_feature_set structure.

        * objdump.c (disassemble_bytes): Set the
        USER_SPECIFIED_MACHINE_TYPE flag in the disassemble_info structure
        if the user has invoked the -m switch.
        * doc/binutils.texi: Document the additional behaviour of
        objdump's -m switch for ARM targets.

        * dis-asm.h (USER_SPECIFIED_MACHINE_TYPE): New value for the flags
        field of struct disassemble_info.

        * gas/arm/align.s: Add labels so that COFF based targets can
        correctly locate THUMB code.
        * gas/arm/copro.d: Do not pass --architecture switch to objdump.
 2009-06-18 10:31:21 +00:00
Maciej W. Rozycki
6db7e006e4 bfd/ 
* elf32-vax.c (elf_vax_plt_sym_val): New function.
(elf_backend_plt_sym_val): Define.

opcodes/
* vax-dis.c (is_function_entry): Return success for synthetic
symbols too.
(is_plt_tail): New function.
(print_insn_vax): Decode PLT entry offset longword.
 2009-06-16 02:23:09 +00:00
Nick Clifton
fe2ceba101 PR 10186 
* arm-dis.c (thumb32_opcodes): Fix binary value of SEV.W
        instruction.

        * gas/arm/thumb32.d: Fix expected binary value of SEV.W instruction.

        * config/tc-arm.c (T16_32_TAB): Fix binary value of SEV.W
        instruction.
 2009-06-15 15:42:36 +00:00
Nick Clifton
522fe56177 PR 10173 
* cr16-dis.c (print_arg): Avoid printing the 0x prefix twice.
 2009-06-15 15:24:52 +00:00
Nick Clifton
1316c8b37f PR 10263 
* arm-dis.c (print_insn): Ignore is_data if the user has requested
        the disassembly of data as well as instructions.

        * objdump.c (disassemble_bytes): Set the DISASSEMBLE_DATA bit in
        the flags field of the disassemble_info structure if the -D switch
        is in operation.

        * dis-asm.h (struct disassemble_info): New value for the flags
        field.
 2009-06-15 11:37:26 +00:00
Doug Evans
f6475b4872 * cgen.sh: Handle multiple simultaneous runs for parallel makes. 2009-06-14 16:36:56 +00:00
Anthony Green
f865a31d1e Add PC-relative branch instructions to moxie port. 2009-06-11 11:27:58 +00:00
Anthony Green
0e7c7f11f4 Print moxie addresses nicely. 2009-06-06 13:02:21 +00:00
Alan Modra
67a648f17a * dep-in.sed: Don't use \n in replacement part of s command. 
* Makefile.am (DEP1): LC_ALL for uniq.
	* Makefile.in: Regenerate.
 2009-06-04 06:57:56 +00:00
Nick Clifton
06c582ac9d * po/nl.po: Updated Dutch translation. 2009-06-02 16:31:59 +00:00
Tristan Gingold
3164099e4f 2009-05-29 Tristan Gingold <gingold@adacore.com> 
* ia64-gen.c (parse_resource_users, print_dependency_table,
	add_dis_table_ent, finish_distable, insert_bit_table_ent,
	add_dis_entry, compact_distree, gen_dis_table, completer_entries_eq,
	get_prefix_len, compute_completer_bits, insert_opcode_dependencies,
	insert_completer_entry, print_completer_entry, print_completer_table,
	opcodes_eq, add_opcode_entry, shrink): Use ISO C syntax for functions.
 2009-06-02 07:48:05 +00:00
DJ Delorie
d285268e48 [cgen] 
* cpu/mep.opc (parse_signed16_range): New.
	(parse_unsigned16_range): New.
	* cpu/mep-ivc2.cpu (imm16p0, simm16p0): Use them.
[opcodes]
	* mep-asm.c: Regenerate.
	* mep-desc.c: Regenerate.
 2009-05-28 22:53:08 +00:00
DJ Delorie
2f3565a392 [cgen/cpu] 
* cpu/mep-ivc2.cpu (h-ccr-ivc2): Enable for C3 slots, fix
	accumulator names.
	(f-ivc2-ccrn-c3hi): New.
	(f-ivc2-ccrn-c3lo): New.
	(f-ivc2-ccrn-c3): New.
	(ivc2c3ccrn): Use it.

[sid/component/cgen-cpu/mep]

	* mep-cop1-32-decode.cxx: Regenerate.
	* mep-cop1-32-decode.h: Regenerate.
	* mep-cop1-32-sem.cxx: Regenerate.
	* mep-cop1-48-sem.cxx: Regenerate.

[opcodes]

	* mep-asm.c: Regenerate.
	* mep-desc.c: Regenerate.
	* mep-desc.h: Regenerate.
	* mep-dis.c: Regenerate.
	* mep-ibld.c: Regenerate.
	* mep-opc.c: Regenerate.
	* mep-opc.h: Regenerate.
 2009-05-27 01:49:46 +00:00
Nick Clifton
f12e7348b2 Update Indonesian translations. 
Update translation templates.
 2009-05-26 16:49:41 +00:00
Alan Modra
9e097a72c9 * dep-in.sed: Don't modify .o to .lo here. Output one filename 
per line with all lines having continuation backslash.  Prefix
	first line with "A", following lines with "B".
	* Makefile.am (DEP): Don't use dep.sed here.
	(DEP1): Run $MKDEP on single files, modify .o to .lo here.  Use
	dep.sed here on dependencies, sort and uniq.
	* Makefile.in: Regenerate.
 2009-05-26 03:19:28 +00:00
Tristan Gingold
4f8318f890 2009-05-25 Tristan Gingold <gingold@adacore.com> 
* makefile.vms (OPT): New variable.
	(CFLAGS): Update compilation flags.
 2009-05-25 12:43:48 +00:00
DJ Delorie
1d74713bc6 [cgen] 
* cpu/mep.opc (mep_examine_ivc2_insns): Fix bug in ivc2 decoder.
	(mep_config_map): Regenerate.

	* cpu/mep-ivc2.cpu (h-ccr-ivc2): Add generic names as well as
	ivc2-specific names.
	(simm8p20): New.
	(cmovc): move to after field definitions, use ivc2-specific
	register names.
	(cpmovi_b_P0S_P1): New.

[utils/mep]

	* mepcfgtool.c (do_cgen_config_opc): Propagate endianness and VLIW
	size to default configuration.

[sid/component/cgen-cpu/mep]

	* mep-cop1-16-decode.cxx: Regenerate.
	* mep-cop1-16-decode.h: Regenerate.
	* mep-cop1-16-model.cxx: Regenerate.
	* mep-cop1-16-model.h: Regenerate.
	* mep-cop1-16-sem.cxx: Regenerate.
	* mep-cop1-64-decode.cxx: Regenerate.
	* mep-cop1-64-decode.h: Regenerate.
	* mep-cop1-64-model.cxx: Regenerate.
	* mep-cop1-64-model.h: Regenerate.
	* mep-cop1-64-sem.cxx: Regenerate.

[opcodes]

	* mep-asm.c: Regenerate.
	* mep-desc.c: Regenerate.
	* mep-desc.h: Regenerate.
	* mep-dis.c: Regenerate.
	* mep-ibld.c: Regenerate.
	* mep-opc.c: Regenerate.
	* mep-opc.h: Regenerate.
 2009-05-22 17:37:45 +00:00
Dwarakanath Rajagopal
c1e679ec0a <gas changes> 
2009-05-22  Dwarakanath Rajagopal  <dwarak.rajagopal@amd.com>

	* config/tc-i386.c (process_drex): Delete. Remove SSE5 support.
	(build_modrm_byte): Remove DREX handling support.
	(DREX_*): Delete.
	(drex_byte): Delete.
	(md_assemble): Remove DREX handling support.
	(process_operands): Remove DREX, SSE5 support.
	(i386_insn): Remove DREX.

<gas/testsuite changes>
2009-05-22  Dwarakanath Rajagopal  <dwarak.rajagopal@amd.com>

	* gas/i386/i386.exp: Remove SSE5 tests.
	* gas/i386/x86-64-sse5.s: Delete. Remove SSE5 tests.
	* gas/i386/x86-64-sse5.d: Ditto.
	* gas/i386/arch-10-1.l: Remove SSE5 tests.
	* gas/i386/arch-10-2.l: Ditto.
	* gas/i386/arch-10-3.l: Ditto.
	* gas/i386/arch-10-4.l: Ditto.
	* gas/i386/arch-10.d: Ditto.
	* gas/i386/arch-10.s: Ditto.
	* gas/i386/arch-4.s: Delete. Remove SSE5 tests.
	* gas/i386/arch-4.d: Ditto.
	* gas/i386/arch-8.s: Ditto.
	* gas/i386/arch-8.d: Ditto.
	* gas/i386/arch-2.s: Remove SSE5 tests.
	* gas/i386/arch-2.d: Remove SSE5 tests.
	* gas/i386/x86-64-arch-2.s: Ditto.

<opcodes changes>
2009-05-22  Dwarakanath Rajagopal  <dwarak.rajagopal@amd.com>

	* i386-opc.h (Cpusse5): Delete.
	(i386_cpu_flags): Delete.
	* i386-gen.c: Remove CpuSSE5, Drex, Drexv and Drexc.
	* i386-opc.tbl: Remove SSE5 instructions.
	* i386-tbl.h: Regenerate.
	* i386-init.h: Regenerate.
	* i386-dis.c (OP_E_memeory, OP_E_extended): Remove drex handling.
	(print_drex_arg): Delete.
	(OP_DREX4): Delete.
	(OP_DREX3): Delete.
	(OP_DREX_ICMP): Delete.
	(OP_DREX_FCMP): Delete.
	(DREX_*): Delete.
	(THREE_BYTE_0F24, THREE_BYTE_0F25, THREE_BYTE_0f7B): Delete.
 2009-05-22 15:57:25 +00:00
Alan Modra
2b3decb5e1 Run "make dep-am" and regenerate 2009-05-22 09:33:16 +00:00
DJ Delorie
eb9568003a * mep-asm.c: Regenerate. 
* mep-opc.c: Regenerate.
 2009-05-19 23:35:47 +00:00
DJ Delorie
3526b6802e Index: opcodes 
* mep-asm.c: Regenerate.
* mep-desc.c: Regenerate.
* mep-desc.h: Regenerate.
* mep-dis.c: Regenerate.
* mep-ibld.c: Regenerate.
* mep-opc.c: Regenerate.
* mep-opc.h: Regenerate.

Index: gas

* config/tc-mep.c (md_begin): Check coprocessor type.
(md_check_parallel64_scheduling): Use memset to initialize the buffer.
(md_check_parallel32_scheduling): Likewise.
(slot_ok): New.
(mep_check_ivc2_scheduling): New.
(mep_check_parallel_scheduling): Call it.
(mep_process_saved_insns): Add IVC2 slot support.
(md_assemble): Likewise.
 2009-04-30 21:23:30 +00:00
Anthony Green
59b1530d0b Add missing disassembler patch for moxie. 2009-04-30 04:54:08 +00:00
DJ Delorie
45be3704c8 [cgen] 
* cpu/mep-c5.cpu (f-12s20): Change to signed.
	(lhucpm1): Limit to C5 mach.
	(dsp0,dsp1): Rewrite as aliases so that intrinsics are generated.
	* cpu/mep-core.cpu (extend-cdisp10): New.
	(f-cdisp10): Change to signed, use extend-cdisp10 to sign extend.

[opcodes]
	* mep-desc.c: Regenerate.
	* mep-ibld.c: Regenerate.
	* mep-opc.c: Regenerate.
	* mep-opc.h: Regenerate.

[sid/component/cgen-cpu/mep]
	* mep-core1-decode.cxx: Regenerate.
	* mep-core1-decode.h: Regenerate.
	* mep-decode.cxx: Regenerate.
	* mep-decode.h: Regenerate.
 2009-04-18 02:56:43 +00:00
DJ Delorie
52de720d5d Add missing ChangeLog entry: 
* mep-asm.c: Regenerate.
* mep-desc.c: Regenerate.
* mep-desc.h: Regenerate.
* mep-dis.c: Regenerate.
* mep-ibld.c: Regenerate.
* mep-opc.c: Regenerate.
* mep-opc.h: Regenerate.
 2009-04-18 01:50:02 +00:00
Nick Clifton
20135e4cea Add new binutils target: moxie 2009-04-16 15:39:48 +00:00
Jan Beulich
ac5c19e6ba gas/testsuite/ 
2009-04-15  Jan Beulich  <jbeulich@novell.com>

	* gas/i386/x86-64-sse5.s: Add test of protd.
	* gas/i386/x86-64-sse5.d: Adjust expectations to match input.

opcodes/
2009-04-15  Jan Beulich  <jbeulich@novell.com>

	* i386-opc.tbl (protb, protw, protd, protq): Set opcode
	extension to None.
	(pshab, pshaw, pshad, pshaq): Likewise.
	* i386-tbl.h: Re-generate.
 2009-04-15 13:31:28 +00:00
DJ Delorie
40493983ad [cgen] 
* cpu/mep-c5.cpu: New.
	* cpu/mep-core.cpu: Add C5 support.
	* cpu/mep.opc: Likewise.
[opcodes]
	* mep-asm.c: Regenerate.
	* mep-desc.c: Regenerate.
	* mep-desc.h: Regenerate.
	* mep-dis.c: Regenerate.
	* mep-ibld.c: Regenerate.
	* mep-opc.c: Regenerate.
	* mep-opc.h: Regenerate.
[sid]
	* component/cache/cache.cxx (cache_component::cache_component):
	Add write_hint_pin().  Attach it to write-hint.
	(cache_component::write_hint): New.
	* component/cache/cache.h (write_hint_pin): New.
	(write_hint): New.

	* component/cgen-cpu/mep/Makefile.am: Regenerate.
	* component/cgen-cpu/mep/Makefile.in: Regenerate.
	* component/cgen-cpu/mep/mep-core1-decode.cxx: Regenerate.
	* component/cgen-cpu/mep/mep-core1-decode.h: Regenerate.
	* component/cgen-cpu/mep/mep-core1-defs.h: Regenerate.
	* component/cgen-cpu/mep/mep-core1-model.cxx: Regenerate.
	* component/cgen-cpu/mep/mep-core1-model.h: Regenerate.
	* component/cgen-cpu/mep/mep-core1-sem.cxx: Regenerate.
	* component/cgen-cpu/mep/mep-decode.cxx: Regenerate.
	* component/cgen-cpu/mep/mep-decode.h: Regenerate.
	* component/cgen-cpu/mep/mep-defs.h: Regenerate.
	* component/cgen-cpu/mep/mep-desc.h: Regenerate.
	* component/cgen-cpu/mep/mep-model.cxx: Regenerate.
	* component/cgen-cpu/mep/mep-model.h: Regenerate.
	* component/cgen-cpu/mep/mep-sem.cxx: Regenerate.
	* component/cgen-cpu/mep/mep.cxx (mep_cpu): Connect
	write-hint pin.
	(do_cache): Add C5 support.
	(do_cache_prefetch): Likewise.
	(do_casb3, do_cash3, do_casw3): New.
	* component/cgen-cpu/mep/mep.h: Add C5 support and write-hint pin.
	(do_casb3, do_cash3, do_casw3): New.

	* component/families/mep/Makefile.in: Regenerate.
	* component/families/mep/dsu.in: Add C5 support.
	* main/dynamic/mainDynamic.cxx: Add C5 support.
	* main/dynamic/mepCfg.cxx: Connect write-hint pin.
	* main/dynamic/mepCfg.h: Add C5 support.
 2009-04-08 20:39:35 +00:00
Peter Bergner
858d7a6db2 opcodes/ 
* ppc-opc.c (powerpc_opcodes) <"tlbilxlpid", "tlbilxpid", "tlbilxva",
	"tlbilx">: Use secondary opcode "18" as per the ISA 2.06 documentation.
	Reorder entries so the extended mnemonics are listed before tlbilx.

gas/testsuite/
	* gas/ppc/e500mc.d: Update to match extended mnemonics.
 2009-04-07 18:28:02 +00:00
Peter Bergner
70dc4e324b opcodes/ 
* ppc-dis.c (powerpc_init_dialect): Do not choose a default dialect
	due to -many/-Many.
	(print_insn_powerpc): Make sure we only deprecate instructions using
	the original dialect and not a modified dialect due to -Many handling.
	Move the handling of the condition register and default operands to
	the end of the if/else if/else chain.
	* ppc-opc.c (powerpc_opcodes): Reorder the opcode table so that
	instructions from newer processors are listed before older ones.
	<"icblce", "sync", "eieio", "tlbld">: Deprecate for processors
	that have instructions with conflicting opcodes.
 2009-04-02 13:30:56 +00:00
Peter Bergner
e401b04ca7 opcodes/ 
* ppc-opc.c (powerpc_opcodes) <"dcbzl">: Merge the POWER4 and
        E500MC entries.
 2009-04-02 00:42:29 +00:00
Christophe Lyon
b8f9ee44f9 2009-04-01 Christophe Lyon <christophe.lyon@st.com> 
opcodes/
	* arm-dis.c (print_insn): Print BE8 opcodes in little endianness.

	ld/testsuite/
	* ld-arm/arm-elf.exp: BE8 tests expect the same output as the
	default ones.
	* ld-arm/arm-be8.d: Print opcodes in little endian.
	* ld-arm/farcall-thumb-arm-be8.d: Removed useless expected result.
	* ld-arm/farcall-arm-arm-be8.d: Likewise.
 2009-04-01 15:45:13 +00:00