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[cgen]

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* cpu/mep.opc (mep_cgen_insn_supported_asm): New, skip the short
	version of BSR when assembling VLIW bundles.  Use it in mep-asm.c

[opcodes]

	* mep-asm.c: Regenerate.
	* mep-opc.c: Regenerate.
	* mep-opc.h: Regenerate.
This commit is contained in:
DJ Delorie 2009-06-24 01:44:53 +00:00
parent 3ef23cd420
commit 378a0c07ca
4 changed files with 20 additions and 0 deletions
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6
opcodes/ChangeLog
View file

@ -1,3 +1,9 @@
2009-06-23 DJ Delorie <dj@redhat.com>
* mep-asm.c: Regenerate.
* mep-opc.c: Regenerate.
* mep-opc.h: Regenerate.
2009-06-22 Nick Clifton <nickc@redhat.com>
* po/fi.po: Updated Finish translation.

1
opcodes/mep-asm.c
View file

@ -54,6 +54,7 @@ static const char * parse_insn_normal
#include "elf/mep.h"
#define CGEN_VALIDATE_INSN_SUPPORTED
#define mep_cgen_insn_supported mep_cgen_insn_supported_asm
const char * parse_csrn (CGEN_CPU_DESC, const char **, CGEN_KEYWORD *, long *);
const char * parse_tpreg (CGEN_CPU_DESC, const char **, CGEN_KEYWORD *, long *);

12
opcodes/mep-opc.c
View file

@ -163,6 +163,18 @@ mep_cgen_insn_supported (CGEN_CPU_DESC cd, const CGEN_INSN *insn)
return (ok1 && ok2 && ok3);
}
int
mep_cgen_insn_supported_asm (CGEN_CPU_DESC cd, const CGEN_INSN *insn)
{
/* If we're assembling VLIW packets, ignore the 12-bit BSR as we
can't relax that. The 24-bit BSR is matched instead. */
if (insn->base->num == MEP_INSN_BSR12
&& cgen_bitset_contains (cd->isas, ISA_EXT_COP1_64))
return 0;
return mep_cgen_insn_supported (cd, insn);
}
/* The hash functions are recorded here to help keep assembler code out of
the disassembler and vice versa. */

1
opcodes/mep-opc.h
View file

@ -96,6 +96,7 @@ extern CGEN_ATTR_VALUE_BITSET_TYPE mep_all_cop_isas_mask;
)
extern int mep_cgen_insn_supported (CGEN_CPU_DESC, const CGEN_INSN *);
extern int mep_cgen_insn_supported_asm (CGEN_CPU_DESC, const CGEN_INSN *);
/* -- asm.c */
/* Enum declaration for mep instruction types. */