opcode * rx.h (enum RX_Operand_Type): Add RX_Operand_Zero_Indirect.
opcodes * rx-decode.opc (rx_disp): If the displacement is zero, set the
type to RX_Operand_Zero_Indirect.
* rx-decode.c: Regenerate.
* rx-dis (print_insn): Handle RX_Operand_Zero_Indirect.
gas * config/rx-parse.y: Allow zero value for 5-bit displacements.
tests * gas/rx/mov.sm: Add tests for zero offset indirect moves.
* gas/rx/mov.d: Update expected output.
Nowadays aarch64_decode_insn is a public interface used by both
opcodes and gdb. However, its behaviour relies on a global variable
no_aliases, which isn't a good practise. On the other hand, In default,
no_aliases is zero, but in GDB, we do want no alias when decoding
instructions for prologue analysis (patches to be posted), so that we
can handle both instructions "add" and "mov" (an alias of "add") as
"add". The code in GDB can be simplified.
This patch adds a new argument in aarch64_decode_insn, and pass no_aliases
to it. In GDB side, always pass 1 to it.
include/opcode:
2015-10-28 Yao Qi <yao.qi@linaro.org>
* aarch64.h (aarch64_decode_insn): Update declaration.
opcodes:
2015-10-28 Yao Qi <yao.qi@linaro.org>
* aarch64-dis.c (aarch64_decode_insn): Add one argument
noaliases_p. Update comments. Pass noaliases_p rather than
no_aliases to aarch64_opcode_decode.
(print_insn_aarch64_word): Pass no_aliases to
aarch64_decode_insn.
gdb:
2015-10-28 Yao Qi <yao.qi@linaro.org>
* aarch64-tdep.c (aarch64_software_single_step): Pass 1 to
aarch64_decode_insn.
'template' is used in include/opcode/aarch64.h as below,
typedef struct
{
const char *template;
uint32_t value;
int has_xt;
} aarch64_sys_ins_reg;
and it triggers compilation errors when GDB is built in C++ mode.
In file included from git/gdb/aarch64-tdep.c:62:0:
git/gdb/../include/opcode/aarch64.h:651:15: error: expected unqualified-id before 'template'
const char *template;
This patch is to rename field template to name.
gas/
* config/tc-aarch64.c (md_begin): Access field 'name' rather
than 'template'.
include/opcode/
* aarch64.h (aarch64_sys_ins_reg) <template>: Removed.
<name>: New field.
opcodes/
* aarch64-dis.c (aarch64_ext_sysins_op): Access field
'name' rather than 'template'.
* aarch64-opc.c (aarch64_print_operand): Likewise.
This is sufficient to link an aarch64 GDB built in C++ mode. Pedro
did something similar in Feb
https://sourceware.org/ml/binutils/2015-02/msg00176.html
include/opcode/
2015-10-07 Yao Qi <yao.qi@linaro.org>
* aarch64.h [__cplusplus]: Wrap in extern "C".
We want to use disas_aarch64_insn inside GDB to decode instructions, so
this patch exposes it and rename it to aarch64_decode_insn to follow
the conventions of other interfaces.
include/opcode:
2015-10-02 Yao Qi <yao.qi@linaro.org>
* aarch64.h (aarch64_decode_insn): Declare it.
opcodes:
2015-10-02 Yao Qi <yao.qi@linaro.org>
* aarch64-dis.c (disas_aarch64_insn): Remove static. Change
argument insn type to aarch64_insn. Rename to ...
(aarch64_decode_insn): ... it.
(print_insn_aarch64_word): Caller updated.
gas * doc/c-s390.texi: Add documentation.
Add missing code markup.
* config/tc-s390.c (current_flags): New static variable.
(s390_parse_cpu): Parse cpu flags a la "+nohtm" etc.
(s390_setup_opcodes): Use cpu flags to determine the set of opcodes.
Fix indentation.
(md_parse_option): Call s390_parse_cpu with the new signature.
(s390_machine): Likewise.
Keep track of current_flags.
Simplify code a bit.
undefine MAX_HISTORY at end of function.
(s390_machinemode): undefine MAX_HISTORY at end of function.
Update an error message.
tests * gas/s390/s390.exp: Add new tests.
* gas/s390/machine-parsing-1.s: New test file.
* gas/s390/machine-parsing-1.l: Likewise.
* gas/s390/machine-parsing-2.s: Likewise.
* gas/s390/machine-parsing-2.l: Likewise.
* gas/s390/machine-parsing-3.s: Likewise.
* gas/s390/machine-parsing-3.l: Likewise.
* gas/s390/machine-parsing-4.s: Likewise.
* gas/s390/machine-parsing-4.l: Likewise.
* gas/s390/machine-parsing-5.s: Likewise.
* gas/s390/machine-parsing-5.l: Likewise.
* gas/s390/machine-parsing-6.s: Likewise.
* gas/s390/machine-parsing-6.l: Likewise.
opcode * s390.h (S390_INSTR_FLAG_HTM): New flag.
(S390_INSTR_FLAG_VX): New flag.
(S390_INSTR_FLAG_FACILITY_MASK): New flag mask.
opcodes * s390-mkopc.c (main): Parse htm and vx flag.
* s390-opc.txt: Mark instructions from the hardware transactional
memory and vector facilities with the "htm"/"vx" flag.
Other places (e.g. the gdb stack unwinder) can use these instead of
hard-coded patterns.
[include/Changelog]
2015-09-26 James Bowman <james.bowman@ftdichip.com>
* opcode/ft32.h: Add instruction macros FT32_*()
Back in the day support for these processors was added, we probably
didn't want to waste PPC_OPCODE bits on minor variations. I've had a
complaint that disassembly of mfspr/mtspr was wrong for power8. This
patch fixes that problem.
Note that since -m860/-m850/-m821 are new gas options enabling the
mpc8xx specific mfspr/mtspr variants it is possible that this change
will break some mpc8xx assembly code. ie. you might need to modify
makefiles to pass -m860 to gas.
include/opcode/
* ppc.h (PPC_OPCODE_750, PPC_OPCODE_7450, PPC_OPCODE_860): Define.
opcodes/
* ppc-opc.c (PPC750, PPC7450, PPC860): Define using PPC_OPCODE_*.
* ppc-dis.c (ppc_opts): Add 821, 850 and 860 entries. Add
PPC_OPCODE_7450 to 7450 entry. Add PPC_OPCODE_750 to 750cl entry.
gas/
* config/tc-ppc.c (md_show_usage): Add -m821, -m850, -m860.
* doc/c-ppc.texi (PowerPC-Opts): Likewise.
gas/testsuite/
* gas/ppc/titan.d: Correct mfmcsrr0 disassembly.
ISA 2.07 (ie, POWER8) added the rfebb instruction which takes one operand
with the value of either a 0 or 1. It also defines an extended mnemonic
with no operands (ie, "rfebb") that is supposed to be equivalent to "rfebb 1".
I implemented rfebb's lone operand with PPC_OPERAND_OPTIONAL, but the
problem is, optional operands that are ommitted always default to the
value 0, which is wrong in this case. I have added support for allowing
non-zero default values by adding an additional flag PPC_OPERAND_OPTIONAL_VALUE
that specifies that the default operand value to be used is stored in the
SHIFT field of the operand field immediately following this one.
This fixes the rfebb issue. I also fixed the mftb and mfcr instructions
so they use the same mechanism. This allows us to flag invalid uses of
mfcr where we explicitly pass in a zero FXM value, like the use in a2.[sd].
include/opcode/
* ppc.h (PPC_OPERAND_OPTIONAL_VALUE): New.
(ppc_optional_operand_value): New inline function.
opcodes/
* ppc-dis.h (skip_optional_operands): Use ppc_optional_operand_value.
* ppc-opc.c (FXM4): Add non-zero optional value.
(TBR): Likewise.
(SXL): Likewise.
(insert_fxm): Handle new default operand value.
(extract_fxm): Likewise.
(insert_tbr): Likewise.
(extract_tbr): Likewise.
gas/
* config/tc-ppc.c (md_assemble): Use ppc_optional_operand_value.
Allow for optional operands without insert functions.
gas/testsuite/
* gas/ppc/power8.d: Fixup rfebb test results.
* gas/ppc/a2.s: Fix invalid mfcr test.
* gas/ppc/a2.d: Likewise.
The ARMv8.1 architecture introduced the Privileged Access Never extension. This
adds a processor state field PSTATE.PAN which can be accessed using the MRS/MSR
instructions.
This patch adds support for the PAN architecture feature and processor state
field to libopcode.
include/opcode
2015-06-01 Matthew Wahab <matthew.wahab@arm.com>
* aarch64.h (AARCH64_FEATURE_PAN): New.
(aarch64_sys_reg_supported_p): Declare.
(aarch64_pstatefield_supported_p): Declare.
opcodes/
2015-06-01 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-opc.c (F_ARCHEXT): New.
(aarch64_sys_regs): Add "pan".
(aarch64_sys_reg_supported_p): New.
(aarch64_pstatefields): Add "pan".
(aarch64_pstatefield_supported_p): New.
These are sufficient to link an --enable-targets=all GDB build in C++
mode, on x86_64 Fedora 20.
include/opcode/
2015-02-19 Pedro Alves <palves@redhat.com>
* cgen.h [__cplusplus]: Wrap in extern "C".
* msp430-decode.h [__cplusplus]: Likewise.
* nios2.h [__cplusplus]: Likewise.
* rl78.h [__cplusplus]: Likewise.
* rx.h [__cplusplus]: Likewise.
* tilegx.h [__cplusplus]: Likewise.
opcodes/
2015-02-19 Pedro Alves <palves@redhat.com>
* microblaze-dis.h [__cplusplus]: Wrap in extern "C".
- 32 128 bit vector registers (overlapping with the existing 16 64 bit
floating point registers)
- vector double instructions
- vector integer instructions
- scalar vector instructions (allowing to have more floating point
registers for scalar operations)
- vector string instructions
gas/ChangeLog:
* config/tc-s390.c (struct pd_reg): Remove.
(pre_defined_registers): Remove.
(REG_NAME_CNT): Remove.
(reg_name_search): Calculate the register number instead of doing
a lookup.
(register_name, tc_s390_regname_to_dw2regnum): Adopt to the new
reg_name_search signature.
(s390_parse_cpu): Support the new arch string z13.
(s390_insert_operand): Support for vector registers with the extra
field for the fifth bit of each vector register operand.
(md_gather_operand): Adjust to the new handling of optional
parameters.
* doc/as.texinfo: Document the z13 cpu string.
gas/testsuite/ChangeLog:
* gas/s390/esa-g5.d: Add a variant without the optional operand.
* gas/s390/esa-g5.s: Likewise.
* gas/s390/esa-z9-109.d: Likewise.
* gas/s390/esa-z9-109.s: Likewise.
* gas/s390/zarch-z9-109.d: Likewise.
* gas/s390/zarch-z9-109.s: Likewise.
* gas/s390/zarch-z10.d: For variants with a zero optional argument
it is not dumped by objdump anymore.
* gas/s390/zarch-zEC12.d: Likewise.
* gas/s390/zarch-z13.d: New file.
* gas/s390/zarch-z13.s: New file.
* gas/s390/s390.exp: Run the test for the z13 files.
include/opcode/ChangeLog:
* s390.h (s390_opcode_cpu_val): Add S390_OPCODE_Z13.
ld/testsuite/ChangeLog:
* ld-s390/tlsbin.dd: The nopr register operand is optional and not
printed if 0 anymore.
opcodes/ChangeLog:
* s390-dis.c (s390_extract_operand): Support vector register
operands.
(s390_print_insn_with_opcode): Support new operands types and add
new handling of optional operands.
* s390-mkopc.c (s390_opcode_mode_val, s390_opcode_cpu_val): Remove
and include opcode/s390.h instead.
(struct op_struct): New field `flags'.
(insertOpcode, insertExpandedMnemonic): New parameter `flags'.
(dumpTable): Dump flags.
(main): Parse flags from the s390-opc.txt file. Add z13 as cpu
string.
* s390-opc.c: Add new operands types, instruction formats, and
instruction masks.
(s390_opformats): Add new formats for .insn.
* s390-opc.txt: Add new instructions.
binutils:
2014-10-31 Andrew Pinski <apinski@cavium.com>
Naveen H.S <Naveen.Hurugalawadi@caviumnetworks.com>
* readelf.c (print_mips_isa_ext): Print the value of Octeon3.
gas:
2014-10-31 Andrew Pinski <apinski@cavium.com>
Naveen H.S <Naveen.Hurugalawadi@caviumnetworks.com>
* config/tc-mips.c (CPU_IS_OCTEON): Handle CPU_OCTEON3.
(mips_cpu_info_table): Octeon3 enables virt ase.
* doc/c-mips.texi: Document octeon3 as an acceptable value for
-march=.
gas/testsuite:
2014-10-31 Andrew Pinski <apinski@cavium.com>
Naveen H.S <Naveen.Hurugalawadi@caviumnetworks.com>
* gas/mips/mips.exp: Add support for Octeon3 architecture.
Also add in support for running Octeon3 tests.
* gas/mips/octeon3.d: New test.
* gas/mips/octeon3.s: New test source.
opcodes:
2014-10-31 Andrew Pinski <apinski@cavium.com>
Naveen H.S <Naveen.Hurugalawadi@caviumnetworks.com>
* mips-dis.c (mips_arch_choices): Add octeon3.
* mips-opc.c (IOCT): Include INSN_OCTEON3.
(IOCT2): Likewise.
(IOCT3): New define.
(IVIRT): New define.
(mips_builtin_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
tlbinv, tlbinvf, tlbgr, tlbgwi, tlbginv, tlbginvf, tlbgwr, tlbgp, tlti
IVIRT instructions.
Extend mtm0, mtm1, mtm2, mtp0, mtp1, mtp2 instructions to take another
operand for IOCT3.
bfd:
2014-10-31 Andrew Pinski <apinski@cavium.com>
Naveen H.S <Naveen.Hurugalawadi@caviumnetworks.com>
* archures.c: Add octeon3 for mips target.
* bfd-in2.h: Regenerate.
* bfd/cpu-mips.c: Define I_mipsocteon3.
nfo_struct): Add octeon3 support.
* bfd/elfxx-mips.c: (_bfd_elf_mips_mach): Add support for
octeon3.
(mips_set_isa_flags): Add support for octeon3.
(bfd_mips_isa_ext): Add bfd_mach_mips_octeon3.
(mips_mach_extensions): Make bfd_mach_mips_octeon3 an
extension of bfd_mach_mips_octeon2.
(print_mips_isa_ext): Print the value of Octeon3.
This patch annotates the following SPARC instructions as VIS3B
instructions: ldx *, %efsr, fpadd64, fpsub64, fpcmpule8, fpcmpune8,
fpcmpugt8, fpcmpueq8. It also improves the documentation of the VIS3B
capability in several headers.
Tested in sparc64-unknown-linux-gnu and sparc-unknown-linux-gnu.
No visible regressions.
opcodes/ChangeLog:
2014-10-17 Jose E. Marchesi <jose.marchesi@oracle.com>
* sparc-opc.c (sparc-opcodes): Annotate several instructions with
the HWCAP2_VIS3B hwcap.
include/opcodes/ChangeLog:
2014-10-17 Jose E. Marchesi <jose.marchesi@oracle.com>
* sparc.h (HWCAP2_VIS3B): Documentation improved.
include/elf/ChangeLog:
2014-10-17 Jose E. Marchesi <jose.marchesi@oracle.com>
* sparc.h (ELF_SPARC_HWCAP2_VIS3B): Documentation improved.
First, add nds32 audio ISA extension including opcodes and registers.
Second, redesign the disassemble implement.
The original disassemble decode instruction opcode using switch-case.
It is hard to synchronize when adding new instructions.
Therefore, the new implement reuses nds32_opcodes to dump the instructions.
bfd/
* aoutx.h (NAME (aout, machine_type)): Add mips32r6 and mips64r6.
* archures.c (bfd_architecture): Likewise.
* bfd-in2.h (bfd_architecture): Likewise.
(bfd_reloc_code_real): Add relocs BFD_RELOC_MIPS_21_PCREL_S2,
BFD_RELOC_MIPS_26_PCREL_S2, BFD_RELOC_MIPS_18_PCREL_S3 and
BFD_RELOC_MIPS_19_PCREL_S2.
* cpu-mips.c (arch_info_struct): Add mips32r6 and mips64r6.
* elf32-mips.c: Define relocs R_MIPS_PC21_S2, R_MIPS_PC26_S2
R_MIPS_PC18_S3, R_MIPS_PC19_S2, R_MIPS_PCHI16 and R_MIPS_PCLO16.
(mips_reloc_map): Add entries for BFD_RELOC_MIPS_21_PCREL_S2,
BFD_RELOC_MIPS_26_PCREL_S2, BFD_RELOC_MIPS_18_PCREL_S3,
BFD_RELOC_MIPS_19_PCREL_S2, BFD_RELOC_HI16_S_PCREL and
BFD_RELOC_LO16_PCREL.
* elf64-mips.c: Define REL, and RELA relocations R_MIPS_PC21_S2,
R_MIPS_PC26_S2, R_MIPS_PC18_S3, R_MIPS_PC19_S2, R_MIPS_PCHI16
and R_MIPS_PCLO16.
(mips_reloc_map): Add entries for BFD_RELOC_MIPS_21_PCREL_S2,
BFD_RELOC_MIPS_26_PCREL_S2, BFD_RELOC_MIPS_18_PCREL_S3,
BFD_RELOC_MIPS_19_PCREL_S2, BFD_RELOC_HI16_S_PCREL and
BFD_RELOC_LO16_PCREL.
* elfn32-mips.c: Likewise.
* elfxx-mips.c (MIPSR6_P): New define.
(mipsr6_exec_plt_entry): New array.
(hi16_reloc_p): Add support for R_MIPS_PCHI16.
(lo16_reloc_p): Add support for R_MIPS_PCLO16.
(aligned_pcrel_reloc_p): New function.
(mips_elf_relocation_needs_la25_stub): Add support for relocs:
R_MIPS_PC21_S2 and R_MIPS_PC26_S2.
(mips_elf_calculate_relocation): Add support for relocs:
R_MIPS_PC21_S2, R_MIPS_PC26_S2, R_MIPS_PC18_S3, R_MIPS_PC19_S2,
R_MIPS_PCHI16 and R_MIPS_PCLO16.
(_bfd_elf_mips_mach): Add support for mips32r6 and mips64r6.
(mips_elf_add_lo16_rel_addend): Add support for R_MIPS_PCHI16.
(_bfd_mips_elf_check_relocs): Add support for relocs:
R_MIPS_PC21_S2 and R_MIPS_PC26_S2.
(_bfd_mips_elf_relocate_section): Add a check for unaligned
pc relative relocs.
(_bfd_mips_elf_finish_dynamic_symbol): Add support for MIPS r6
plt entry.
(mips_set_isa_flags): Add support for mips32r6 and mips64r6.
(_bfd_mips_elf_print_private_bfd_data): Likewise.
(mips_32bit_flags_p): Add support for mips32r6.
* libbfd.h (bfd_reloc_code_real_names): Add entries for
BFD_RELOC_MIPS_21_PCREL_S2, BFD_RELOC_MIPS_26_PCREL_S2,
BFD_RELOC_MIPS_18_PCREL_S3 and BFD_RELOC_MIPS_19_PCREL_S2.
* reloc.c: Document relocs BFD_RELOC_MIPS_21_PCREL_S2,
BFD_RELOC_MIPS_26_PCREL_S2, BFD_RELOC_MIPS_18_PCREL_S3 and
BFD_RELOC_MIPS_19_PCREL_S2.
binutils/
* readelf.c (get_machine_flags): Add support for mips32r6 and
mips64r6.
elfcpp/
* mips.h (E_MIPS_ARCH_32R6, E_MIPS_ARCH_64R6): New enum constants.
gas/
* config/tc-mips.c (mips_nan2008): New static global.
(mips_flag_nan2008): Removed.
(LL_SC_FMT): New define.
(COP12_FMT): Updated.
(ISA_IS_R6): New define.
(ISA_HAS_64BIT_REGS): Add mips64r6.
(ISA_HAS_DROR): Likewise.
(ISA_HAS_64BIT_FPRS): Add mips32r6 and mips64r6.
(ISA_HAS_ROR): Likewise.
(ISA_HAS_ODD_SINGLE_FPR): Likewise.
(ISA_HAS_MXHC1): Likewise.
(hilo_interlocks): Likewise.
(md_longopts): Likewise.
(ISA_HAS_LEGACY_NAN): New define.
(options): Add OPTION_MIPS32R6 and OPTION_MIPS64R6.
(mips_ase): Add field rem_rev.
(mips_ases): Updated to add which ISA an ASE was removed in.
(mips_isa_rev): Add support for mips32r6 and mips64r6.
(mips_check_isa_supports_ase): Add support to check if an ASE
has been removed in the specified MIPS ISA revision.
(validate_mips_insn): Skip '-' character.
(macro_build): Likewise.
(mips_check_options): Prevent R6 working with fp32, mips16,
micromips, or branch relaxation.
(file_mips_check_options): Set R6 floating point registers to
64 bit. Also deal with the nan2008 option.
(limited_pcrel_reloc_p): Add relocs: BFD_RELOC_MIPS_21_PCREL_S2,
BFD_RELOC_MIPS_26_PCREL_S2, BFD_RELOC_MIPS_18_PCREL_S3,
BFD_RELOC_MIPS_19_PCREL_S2, BFD_RELOC_HI16_S_PCREL and
BFD_RELOC_LO16_PCREL.
(operand_reg_mask): Add support for OP_SAME_RS_RT, OP_CHECK_PREV
and OP_NON_ZERO_REG.
(match_check_prev_operand): New static function.
(match_same_rs_rt_operand): New static function.
(match_non_zero_reg_operand): New static function.
(match_operand): Added entries for: OP_SAME_RS_RT, OP_CHECK_PREV
and OP_NON_ZERO_REG.
(insns_between): Added case to deal with forbidden slots.
(append_insn): Added support for relocs: BFD_RELOC_MIPS_21_PCREL_S2
and BFD_RELOC_MIPS_26_PCREL_S2.
(match_insn): Add support for operands -A, -B, +' and +". Also
skip '-' character.
(mips_percent_op): Add entries for %pcrel_hi and %pcrel_lo.
(md_parse_option): Add support for mips32r6 and mips64r6. Also
update the nan option handling.
(md_pcrel_from): Add cases for relocs: BFD_RELOC_MIPS_21_PCREL_S2,
BFD_RELOC_MIPS_26_PCREL_S2.
(mips_force_relocation): Prevent forced relaxation for MIPS r6.
(md_apply_fix): Add support for relocs: BFD_RELOC_MIPS_21_PCREL_S2,
BFD_RELOC_MIPS_26_PCREL_S2, BFD_RELOC_MIPS_18_PCREL_S3,
BFD_RELOC_MIPS_19_PCREL_S2, BFD_RELOC_HI16_S_PCREL and
BFD_RELOC_LO16_PCREL.
(s_mipsset): Add support for mips32r6 and mips64r6.
(s_nan): Update to support the new nan2008 framework.
(tc_gen_reloc): Add relocs: BFD_RELOC_MIPS_21_PCREL_S2,
BFD_RELOC_MIPS_26_PCREL_S2, BFD_RELOC_MIPS_18_PCREL_S3,
BFD_RELOC_MIPS_19_PCREL_S2, BFD_RELOC_HI16_S_PCREL and
BFD_RELOC_LO16_PCREL.
(mips_elf_final_processing): Updated to use the mips_nan2008.
(mips_cpu_info_table): Add entries for mips32r6 and mips64r6.
(macro): Enable ldc2, sdc2, ll, lld, swc2, sc, scd, cache, pref
macros for R6.
(mips_fix_adjustable): Make PC relative R6 relocations relative
to the symbol and not the section.
* configure.ac: Add support for mips32r6 and mips64r6.
* configure: Regenerate.
* doc/c-mips.texi: Document the -mips32r6 and -mips64r6 command line
options.
* doc/as.texinfo: Likewise.
gas/testsuite/
* gas/mips/24k-triple-stores-1.s: If testing for r6 prevent
non-supported instructions from being tested.
* gas/mips/24k-triple-stores-2.s: Likewise.
* gas/mips/24k-triple-stores-3.s: Likewise.
* gas/mips/24k-triple-stores-6.s: Likewise.
* gas/mips/beq.s: Likewise.
* gas/mips/eva.s: Likewise.
* gas/mips/ld-zero-3.s: Likewise.
* gas/mips/mips32-cp2.s: Likewise.
* gas/mips/mips32.s: Likewise.
* gas/mips/mips4.s: Likewise.
* gas/mips/add.s: Don't test the add instructions if r6, and
add padding.
* gas/mips/add.d: Check for a triple dot not a nop at the end of the
disassembly output.
* gas/mips/micromips@add.d: Likewise.
* gas/mips/mipsr6@24k-branch-delay-1.d: New file.
* gas/mips/mipsr6@24k-triple-stores-1.d: New file.
* gas/mips/mipsr6@24k-triple-stores-2-llsc.d: New file.
* gas/mips/mipsr6@24k-triple-stores-2.d: New file.
* gas/mips/mipsr6@24k-triple-stores-3.d: New file.
* gas/mips/mipsr6@24k-triple-stores-6.d: New file.
* gas/mips/mipsr6@add.d: New file.
* gas/mips/mipsr6@attr-gnu-4-1-msingle-float.l: New file.
* gas/mips/mipsr6@attr-gnu-4-1-msingle-float.s: New file.
* gas/mips/mipsr6@attr-gnu-4-1-msoft-float.l: New file.
* gas/mips/mipsr6@attr-gnu-4-1-msoft-float.s: New file.
* gas/mips/mipsr6@attr-gnu-4-2-mdouble-float.l: New file.
* gas/mips/mipsr6@attr-gnu-4-2-mdouble-float.s: New file.
* gas/mips/mipsr6@beq.d: New file.
* gas/mips/mipsr6@bge.d: New file.
* gas/mips/mipsr6@bgeu.d: New file.
* gas/mips/mipsr6@blt.d: New file.
* gas/mips/mipsr6@bltu.d: New file.
* gas/mips/mipsr6@branch-misc-1.d: New file.
* gas/mips/mipsr6@branch-misc-2-64.d: New file.
* gas/mips/mipsr6@branch-misc-2pic-64.d: New file.
* gas/mips/mipsr6@branch-misc-4-64.d: New file.
* gas/mips/mipsr6@cache.d: New file.
* gas/mips/mipsr6@eva.d: New file.
* gas/mips/mipsr6@jal-svr4pic-noreorder.d: New file.
* gas/mips/mipsr6@jal-svr4pic.d: New file.
* gas/mips/mipsr6@ld-zero-2.d: New file.
* gas/mips/mipsr6@ld-zero-3.d: New file.
* gas/mips/mipsr6@loc-swap-dis.d: New file.
* gas/mips/mipsr6@mips32-cp2.d: New file.
* gas/mips/mipsr6@mips32-imm.d: New file.
* gas/mips/mipsr6@mips32.d: New file.
* gas/mips/mipsr6@mips32r2.d: New file.
* gas/mips/mipsr6@mips4-fp.d: New file.
* gas/mips/mipsr6@mips4-fp.l: New file.
* gas/mips/mipsr6@mips4-fp.s: New file.
* gas/mips/mipsr6@mips4.d: New file.
* gas/mips/mipsr6@mips5-fp.d: New file.
* gas/mips/mipsr6@mips5-fp.l: New file.
* gas/mips/mipsr6@mips5-fp.s: New file.
* gas/mips/mipsr6@mips64.d: New file.
* gas/mips/mipsr6@msa-branch.d: New file.
* gas/mips/mipsr6@msa.d: New file.
* gas/mips/mipsr6@pref.d: New file.
* gas/mips/mipsr6@relax-swap3.d: New file.
* gas/mips/r6-64-n32.d: New file.
* gas/mips/r6-64-n64.d: New file.
* gas/mips/r6-64-removed.l: New file.
* gas/mips/r6-64-removed.s: New file.
* gas/mips/r6-64.s: New file.
* gas/mips/r6-attr-none-double.d: New file.
* gas/mips/r6-n32.d: New file.
* gas/mips/r6-n64.d: New file.
* gas/mips/r6-removed.l: New file.
* gas/mips/r6-removed.s: New file.
* gas/mips/r6.d: New file.
* gas/mips/r6.s: New file.
* gas/mips/mipsr6@mips32-dsp.d: New file.
* gas/mips/mipsr6@mips32-dspr2.d: New file.
* gas/mips/mipsr6@mips32r2-ill.l: New file.
* gas/mips/mipsr6@mips32r2-ill.s: New file.
* gas/mips/cache.s: Add r6 instruction varients.
* gas/mips/mips.exp: Add support for the mips32r6 and mips64r6
architectures. Also prevent non r6 supported tests from running.
Finally, add in support for running the new r6 tests.
(run_dump_test_arch): Add support for mipsr6 tests.
(run_list_test_arch): Add support for using files of the
form arch@testname.l .
include/elf/
* mips.h: Add relocs: R_MIPS_PC21_S2, R_MIPS_PC26_S2, R_MIPS_PC18_S3,
R_MIPS_PC19_S2, R_MIPS_PCHI16 and R_MIPS_PCLO16.
(E_MIPS_ARCH_32R6): New define.
(E_MIPS_ARCH_64R6): New define.
include/opcode/
* mips.h (mips_operand_type): Add new entries: OP_SAME_RS_RT,
OP_CHECK_PREV and OP_NON_ZERO_REG. Add descriptions for the MIPS R6
instruction arguments: -a, -b, -d, -s, -t, -u, -v, -w, -x, -y, -A, -B,
+I, +O, +R, +:, +\, +", +;
(mips_check_prev_operand): New struct.
(INSN2_FORBIDDEN_SLOT): New define.
(INSN_ISA32R6): New define.
(INSN_ISA64R6): New define.
(INSN_UPTO32R6): New define.
(INSN_UPTO64R6): New define.
(mips_isa_table): Add INSN_UPTO32R6 and INSN_UPTO64R6.
(ISA_MIPS32R6): New define.
(ISA_MIPS64R6): New define.
(CPU_MIPS32R6): New define.
(CPU_MIPS64R6): New define.
(cpu_is_member): Add cases for CPU_MIPS32R6, and CPU_MIPS64R6.
ld/
* ldmain.c (get_emulation): Add support for -mips32r6 and -mips64r6.
opcodes/
* mips-dis.c (mips_arch_choices): Add entries for mips32r6 and
mips64r6.
(parse_mips_dis_option): Allow MSA and virtualization support for
mips64r6.
(mips_print_arg_state): Add fields dest_regno and seen_dest.
(mips_seen_register): New function.
(print_insn_arg): Refactored code to use mips_seen_register
function. Add support for OP_SAME_RS_RT, OP_CHECK_PREV and
OP_NON_ZERO_REG. Changed OP_REPEAT_DEST_REG case to print out
the register rather than aborting.
(print_insn_args): Add length argument. Add code to correctly
calculate the instruction address for pc relative instructions.
(validate_insn_args): New static function.
(print_insn_mips): Prevent jalx disassembling for r6. Use
validate_insn_args.
(print_insn_micromips): Use validate_insn_args.
all the arguments are valid.
* mips-formats.h (PREV_CHECK): New define.
* mips-opc.c (decode_mips_operand): Add support for -a, -b, -d, -s,
-t, -u, -v, -w, -x, -y, -A, -B, +I, +O, +R, +:, +\, +", +;
(RD_pc): New define.
(FS): New define.
(I37): New define.
(I69): New define.
(mips_builtin_opcodes): Add MIPS R6 instructions. Exclude recoded
MIPS R6 instructions from MIPS R2 instructions.
This change moves the microMIPS 10-bit uninterpreted immediate code
embedded at bits 25..16 in the SYSCALL, WAIT, SDBBP and HYPCALL
instructions from `B' over to `+J' which is the operand code used in
the standard MIPS instruction set for a similar code embedded at bits
20..11, currently used by HYPCALL only in that set.
opcodes/
* micromips-opc.c (decode_micromips_operand): Rename `B' to `+J'.
(micromips_opcodes): Use "+J" in place of "B" for "hypcall",
"sdbbp", "syscall" and "wait".
include/opcode/
* mips.h: Document the move of `MICROMIPSOP_*_CODE10' from `B'
over to `+J'.
gas/
* config/tc-mips.c: Rename INSN_LOAD_COPROC_DELAY to INSN_LOAD_COPROC
and INSN_COPROC_MOVE_DELAY to INSN_COPROC_MOVE throughout.
include/opcode/
* mips.h (INSN_LOAD_COPROC_DELAY): Rename to...
(INSN_LOAD_COPROC): New define.
(INSN_COPROC_MOVE_DELAY): Rename to...
(INSN_COPROC_MOVE): New define.
opcodes/
* micromips-opc.c (COD): Rename throughout to...
(CM): New define, update to use INSN_COPROC_MOVE.
(LCD): Rename throughout to...
(LC): New define, update to use INSN_LOAD_COPROC.
* mips-opc.c: Likewise.
* archures.c: add avrtiny architecture for avr target.
* bfd-in2.h: Regenerate.
* cpu-avr.c (arch_info_struct): add avrtiny arch info.
* elf32-avr.c (elf_avr_howto_table): new relocation R_AVR_LDS_STS_16
added for 16 bit LDS/STS instruction of avrtiny arch.
(avr_reloc_map): reloc R_AVR_LDS_STS_16 is mapped to
BFD_RELOC_AVR_LDS_STS_16.
(bfd_elf_avr_final_write_processing): select machine number avrtiny arch.
(elf32_avr_object_p): set machine number for avrtiny arch.
* libbfd.h: Regenerate.
* reloc.c: Add documentation for BFD_RELOC_AVR_LDS_STS_16 reloc.
* config/tc-avr.c (mcu_types): Add avrtiny arch.
Add avrtiny arch devices attiny4, attiny5, attiny9, attiny10, attiny20
and attiny40.
(md_show_usage): Add avrtiny arch in usage message.
(avr_operand): validate and issue error for invalid register for avrtiny.
add new reloc exp for 16 bit lds/sts instruction.
(md_apply_fix): check 16 bit lds/sts operand for out of range and encode.
(md_assemble): check ISA for arch and issue diagnostic.
* include/elf/avr.h (E_AVR_MACH_AVRTINY): define avrtiny machine number.
(R_AVR_LDS_STS_16): define 16 bit lds/sts reloc number.
* include/opcode/avr.h (AVR_ISA_TINY): define avrtiny specific ISA.
(AVR_ISA_2xxxa): define ISA without LPM.
(AVR_ISA_AVRTINY): define avrtiny arch ISA.
Add doc for contraint used in 16 bit lds/sts.
Adjust ISA group for icall, ijmp, pop and push.
Add 16 bit lds/sts encoding and update 32 bit lds/sts constraints.
* opcodes/avr-dis.c (avr_operand): Handle constraint j for 16 bit lds/sts.
(print_insn_avr): do not select opcode if insn ISA is avrtiny and machine
is not avrtiny.
* Makefile.am (ALL_EMULATION_SOURCES): add avrtiny emulation source.
(eavrtiny.c): add rules for avrtiny emulation source.
* Makefile.in: Regenerate.
* configure.tgt: Add avrtiny to avr target emulations.
* scripttempl/avrtiny.sc: New file.
linker script template for avrtiny arch.
* emulparams/avrtiny.sh: New file.
emulation parameters for avrtiny arch.
* config/tc-msp430.c (CHECK_RELOC_MSP430): Add OP parameter.
Generate BFD_RELOC_MSP430_ABS_HI16 if vshift is 1.
(msp430_srcoperand): Store vshift value in operand.
* msp430.h (struct msp430_operand_s): Add vshift field.
* gas/elf/struct.d: Expect extra output from some toolchains.
* gas/symver/symver0.d: Likewise.
* gas/symver/symver1.d: Likewise.
This patch firstly adds support for mips32r3 mips32r5, mips64r3
and mips64r5. Secondly it adds support for the eretnc instruction.
ChangeLog:
bfd/
* aoutx.h (NAME (aout, machine_type)): Add mips32r3, mips64r3,
mips32r5 and mips64r5.
* archures.c (bfd_architecture): Likewise.
* bfd-in2.h (bfd_architecture): Likewise.
* cpu-mips.c (arch_info_struct): Likewise.
* elfxx-mips.c (mips_set_isa_flags): Likewise.
gas/
* tc-mips.c (ISA_SUPPORTS_MIPS16E): Add mips32r3, mips32r5, mips64r3
and mips64r5.
(ISA_HAS_64BIT_FPRS): Likewise.
(ISA_HAS_ROR): Likewise.
(ISA_HAS_ODD_SINGLE_FPR): Likewise.
(ISA_HAS_MXHC1): Likewise.
(hilo_interlocks): Likewise.
(md_longopts): Likewise.
(ISA_HAS_64BIT_REGS): Add mips64r3 and mips64r5.
(ISA_HAS_DROR): Likewise.
(options): Add OPTION_MIPS32R3, OPTION_MIPS32R5, OPTION_MIPS64R3, and
OPTION_MIPS64R5.
(mips_isa_rev): Add support for mips32r3, mips32r5, mips64r3 and
mips64r5.
(md_parse_option): Likewise.
(s_mipsset): Likewise.
(mips_cpu_info_table): Add entries for mips32r3, mips32r5, mips64r3
and mips64r5. Also change p5600 entry to be mips32r5.
* configure.in: Add support for mips32r3, mips32r5, mips64r3 and
mips64r5.
* configure: Regenerate.
* doc/c-mips.texi: Document the -mips32r3, -mips32r5, -mips64r3 and
-mips64r5 command line options.
* doc/as.texinfo: Likewise.
gas/testsuite/
* gas/mips/mips.exp: Add MIPS32r5 tests. Also add the mips32r3,
mips32r5, mips64r3 and mips64r5 isas to the testsuite.
* gas/mips/r5.s: New test.
* gas/mips/r5.d: Likewise.
include/opcode/
* mips.h (INSN_ISA_MASK): Updated.
(INSN_ISA32R3): New define.
(INSN_ISA32R5): New define.
(INSN_ISA64R3): New define.
(INSN_ISA64R5): New define.
(INSN_ISA64, INSN_ISA64R2, INSN_ISA3_32, INSN_ISA3_32R2, INSN_ISA4_32
INSN_ISA4_32R2, INSN_ISA5_32R2): Renumbered.
(mips_isa_table): Add entries for mips32r3, mips32r5, mips64r3 and
mips64r5.
(INSN_UPTO32R3): New define.
(INSN_UPTO32R5): New define.
(INSN_UPTO64R3): New define.
(INSN_UPTO64R5): New define.
(ISA_MIPS32R3): New define.
(ISA_MIPS32R5): New define.
(ISA_MIPS64R3): New define.
(ISA_MIPS64R5): New define.
(CPU_MIPS32R3): New define.
(CPU_MIPS32R5): New define.
(CPU_MIPS64R3): New define.
(CPU_MIPS64R5): New define.
opcodes/
* mips-opc.c (mips_builtin_opcodes): Add MIPS32r5 eretnc instruction.
(I34): New define.
(I36): New define.
(I66): New define.
(I68): New define.
* mips-dis.c (mips_arch_choices): Add mips32r3, mips32r5, mips64r3 and
mips64r5.
(parse_mips_dis_option): Update MSA and virtualization support to
allow mips64r3 and mips64r5.
