Commit graph

3364 commits

Author SHA1 Message Date
Tom Tromey
d6c2da5446 move version.in from gdb/common back to gdb
This reverts part of the earlier version.in change.  It moves
version.in back to the gdb directory.  This works around the CVS bug
we've found.

gdb
	* Makefile.in (version.c): Use version.in, not
	common/version.in.
	* common/create-version.sh: Likewise.
	* common/version.in: Move...
	* version.in: ...here.
gdb/doc
	* Makefile.in (version.subst): Use version.in, not
	common/version.in.
	* gdbint.texinfo (Versions and Branches, Releasing GDB):
	Likewise.
gdb/gdbserver
	* Makefile.in (version.c): Use version.in, not
	common/version.in.
sim/common
	* Make-common.in (version.c): Use version.in, not
	common/version.in.
	* create-version.sh: Likewise.
sim/ppc:
	* Make-common.in (version.c): Use version.in, not
	common/version.in.
2013-06-28 18:59:51 +00:00
Nick Clifton
7f77d948db * rx.c (SHIFT_OP): A shift by zero still sets the condition codes. 2013-06-28 07:19:44 +00:00
Tom Tromey
3cd8689bf6 * Makefile.in (dtbdir): Don't use gdb's version.in. 2013-06-26 15:55:59 +00:00
Joel Brobecker
b652c496ac Adapt sim to new version number & date locations.
This change is required now that gdb/version.in has been moved to
gdb/common/version.in and now that the date needs to be fetched
from bfd/version.h.

sim/common/ChangeLog:

        * create-version.sh: New script. Adapted from
        gdb/commong/create-version.sh.
        * Make-common.in (version.c): Update rule dependencies,
        and re-implement using create-version.sh.

sim/ppc/ChangeLog:

        * Makefile.in (srccom): New variable.
        (version.c): Update rule dependencies, and re-implement using
        sim/common/create-version.sh.
2013-06-24 23:41:35 +00:00
Mike Frysinger
48a9389710 sim: bfin: note missing parallel handling of SEARCH
The SEARCH insn is an oddball when it comes to parallel usage.  It places a
big limit on what other insns it can run in parallel with, but we don't
currently track the amount of state needed to verify this (since no other insn
really requires this).  Add a note for now in case we get around to it.
2013-06-24 02:06:32 +00:00
Mike Frysinger
03dccef1ab sim: bfin: handle invalid HLs encoding in dsp shift insns
For many of the 32bit dsp shift related insns, we were just ignoring the HLs
field.  The hardware does not though and will reject the insn if it's set
incorrectly.  Update the sim to match.
2013-06-24 02:03:03 +00:00
Mike Frysinger
19b7bc4bd8 sim: bfin: run-tests.sh: fix typo in usage exit 2013-06-24 01:59:10 +00:00
Mike Frysinger
7f5884f775 sim: bfin: se_all32bitopcodes: skip debug insns under the sim
Since the sim has a few fake debug insns that the hardware does not, we
need to check for those before attempting to run them.  Otherwise we'll
randomly trigger the sim debug asserts/aborts/halts insns.  On the
hardware, these are proper invalid insns, and the table catches that.
2013-06-24 01:52:33 +00:00
Mike Frysinger
531d5282c0 sim: bfin: speed up all insn testcases slightly
The main body of the "all insn" test is executed once per tested insn, and
we test millions of insns here.  Any shrinkage we can do in this loop will
speed things up nicely (since it's multiplied per tested insn).

To that end, simplify the end-of-table test into one less insn, and omit
the SSYNC when we build for the sim.  When we build to run on the hardware,
this insn matters, but the sim doesn't have write store buffers in the chip
that might get in the way (memory writes are atomic).
2013-06-24 01:44:55 +00:00
Mike Frysinger
88924e5fa2 sim: bfin: trim trailing whitespace 2013-06-23 06:23:54 +00:00
Nick Clifton
3346cfda88 * msp430: New Directory.
* configure.tgt: Add it.
	* configure: Regenerate.

	* gennltvals.sh: Add msp430 support.
	* nltvals.def: Regenerate.

	* Makefile.in: New.
	* aclocal.m4: Generate.
	* config.in: Generate.
	* configure.ac: New.
	* configure: Generate.
	* msp430-sim.c: New.
	* msp430-sim.h: New.
	* sim-main.h: New.
	* trace.c: New.
	* trace.h: New.
2013-06-21 10:59:14 +00:00
Mike Frysinger
f7f8a049bd sim: bfin: stricter insn decoding
We wrote a test case that tries every single 32bit opcode on the hardware
and compared it to the sim.  There were a bunch of places in the sim where
we weren't strict enough (requiring certain parts of the opcode be set) so
we were treating a lot of invalid opcodes as valid ones.  This sprinkles
out a lot additional checks in the dsp32alu class.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2013-06-19 03:12:26 +00:00
Mike Frysinger
b6857b1e6c sim: bfin: tweak run-tests for parallel usage 2013-06-17 04:58:56 +00:00
Mike Frysinger
9fb7353ff0 sim: bfin: add helpful info for generating test tables 2013-06-17 04:47:26 +00:00
Mike Frysinger
7a56db5f46 sim: bfin: drop RET[ENI] setup
Since these insns run in usermode, there should be no need to setup
RET[ENI] to safe values.  They won't be dereferenced, and any insn
that returns via them are valid only in supervisor mode.  Since this
is in the main exception code path, saving any insn at all is good
as it gets multiplied quickly (as in O(n^2) times).

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2013-06-17 04:45:54 +00:00
Mike Frysinger
7935c6b0d2 sim: bfin: add flush/HWERR todo 2013-06-17 04:43:22 +00:00
Mike Frysinger
b241c8905a sim: bfin: only regen linux-fixed-code.h in maintainer mode
Since many people don't have a Blackfin toolchain available, only try to
regenerate the header file when in maintainer mode.  This file rarely changes,
and when it does, we commit the generated output, so there's almost never a
need to run directly on an end system.
2013-06-10 02:25:35 +00:00
Mike Frysinger
31e6ad7d64 sim: use AM_MAINTAINER_MODE
I noticed the sim code is using an old implementation of the maintainer logic.
I cut it over to the new macro (like gdb has been doing).  In practice, it
makes no difference currently as nothing in the sim tree uses it, but I have a
follow up commit for the Blackfin tree that needs it.
2013-06-05 01:42:13 +00:00
Mike Frysinger
590919de6c sim: arm: add support for MOVW and MOVT instructions
From: Jayant R. Sonar <Jayant.Sonar@kpitcummins.com>

This patch adds simulator support for handling the armv7 instructions
'movw (immediate)' and 'movt'.

Compiler frequently use these instructions to load the 32bit addresses of
global variables, string pointers etc. into the general registers.

In absence of support of these instructions:
1. GDB run simulator fails to print even simple "hello world" string
   on console.
2. Loading of global variable addresses into the registers fail causing
   arithmetic operation failures.

Patch has been regression tested for arm-none-eabi (-march=armv7-a).
2013-05-15 17:49:44 +00:00
Nick Clifton
fd7b2a545d * v850.igen (LDSR): Accept but ignore a selID parameter. 2013-05-13 10:52:52 +00:00
Tom Tromey
d3685d60d6 gdb
Freddie Chopin  <freddie_chopin@op.pl>
	PR build/15414:
	* configure: Rebuild.
	* configure.ac (build_warnings): Do not use -Wformat-nonliteral
	with -Wno-format.
sim/common
	* acinclude.m4 (SIM_AC_OPTION_WARNINGS): Do not use
	-Wformat-nonliteral with -Wno-format.
sim/bfin
	* configure: Rebuild.
sim/cr16
	* configure: Rebuild.
sim/cris
	* configure: Rebuild.
sim/d10v
	* configure: Rebuild.
sim/igen
	* configure: Rebuild.
sim/m68hc11
	* configure: Rebuild.
sim/mips
	* configure: Rebuild.
sim/mn10300
	* configure: Rebuild.
sim/v850
	* configure: Rebuild.
2013-05-10 16:10:40 +00:00
Joel Brobecker
b21c850d8f Move ChangeLog entry from sim/ to sim/ppc/...
... where it belongs.
2013-05-06 10:26:41 +00:00
Hafiz Abid Qadeer
3fd5675a52 2013-05-03 Hafiz Abid Qadeer <abidh@codesourcery.com>
revert:
	2013-04-19  Nathan Froyd  <froydnj@codesourcery.com>
	* ppc-instructions (isel): New instruction.
2013-05-03 14:03:57 +00:00
Hafiz Abid Qadeer
8bf54274ec 2013-04-19 Nathan Froyd <froydnj@codesourcery.com>
* ppc-instructions (isel): New instruction.
2013-04-19 18:17:32 +00:00
Mike Frysinger
73e76d2003 sim: frv/m32r: back out hard failure when dv-sockser is not available
These sims have optional support for the dv-sockser model, so do not make
them hard failures.  The Makefile made it seem like they didn't actually
support things dynamically, but a further code dive into the source and
the Makefile shows that things work out.
2013-03-31 00:39:35 +00:00
Mike Frysinger
1517bd2742 sim: rewrite SIM_AC_OPTION_HARDWARE a bit to simplify things
There's no need to put the majority of the logic into the 3rd arg of the
AC_ARG_ENABLE.  Coupled with the lack of indentation, it makes it hard to
follow, error prone to update, and duplicates code (with the 4th arg).

So pull the logic out of the 3rd arg and outside of the AC_ARG_ENABLE
macro.  This allows us to gut the 4th arg entirely, merge with the code
that followed the macro, and fix bugs related to the new dv-sockser in
the process.

Hopefully building the various sims with the default sim-hardware
settings, as well as with explicit --{dis,en}able-sim-hardware flags,
should all just work now.
2013-03-26 18:00:04 +00:00
Joel Sherrill
256139f50b 2013-03-23 Joel Sherrill <joel.sherrill@oarcorp.com>
* configure.ac: Use $SIM_DV_SOCKSER_O.
	* configure: Regenerated.
2013-03-23 15:08:07 +00:00
Joel Sherrill
94c63d78f6 2013-03-23 Joel Sherrill <joel.sherrill@oarcorp.com>
* configure.ac: Fail if dv-sockser.o not available.
	Error when --disable-sim-hardware is specified.
	* configure: Regenerated.
2013-03-23 15:07:30 +00:00
Joel Sherrill
fb61c40add 2013-03-23 Joel Sherrill <joel.sherrill@oarcorp.com>
* configure.ac: Fail if dv-sockser.o not available.
	Error when --disable-sim-hardware is specified.
	* tconfig.in: Conditionalize use of dv_sockser_install.
	* configure: Regenerated.
	* config.in: Regenerated.
2013-03-23 15:06:59 +00:00
Joel Sherrill
3be3151681 2013-03-23 Joel Sherrill <joel.sherrill@oarcorp.com>
* configure.ac: Address use of dv-sockser.o.
	* tconfig.in: Conditionalize use of dv_sockser_install.
	* configure: Regenerated.
	* config.in: Regenerated.
2013-03-23 15:05:07 +00:00
Joel Sherrill
3fd38161b3 2013-03-23 Joel Sherrill <joel.sherrill@oarcorp.com>
* acinclude.m4: Add SIM_DV_SOCKSER_O which is empty  on hosts
	which do not support dv-sockser.o.  Add always as option to
	first argument to SIM_AC_OPTION_HARDWARE. Fail if hardware
	is always required to be enabled by simulator.
2013-03-23 15:03:01 +00:00
Steve Ellcey
3cb2ab1a46 gdb:
2013-03-15  Steve Ellcey  <sellcey@mips.com>

	* remote-sim.c (sim_command_completer): Make char arguments const.

include:


2013-03-15  Steve Ellcey  <sellcey@mips.com>

	* gdb/remote-sim.h (sim_command_completer): Make char arguments const.

sim:

2013-03-15  Steve Ellcey  <sellcey@mips.com>

	* arm/wrapper.c (sim_complete_command): Make char arguments const.
	* avr/interp.c (sim_complete_command): Ditto.
	* common/sim-options.c (sim_complete_command): Ditto.
	* cr16/interp.c (sim_complete_command): Ditto.
	* erc32/interf.c (sim_complete_command): Ditto.
	* m32c/gdb-if.c (sim_complete_command): Ditto.
	* microblaze/interp.c (sim_complete_command): Ditto.
	* ppc/sim_calls.c (sim_complete_command): Ditto.
	* rl78/gdb-if.c (sim_complete_command): Ditto.
	* rx/gdb-if.c (sim_complete_command): Ditto.
	* sh/interp.c (sim_complete_command): Ditto.
2013-03-15 17:53:44 +00:00
Joel Brobecker
7b7f7f41a8 Fix erc32 simulator out-of-tree build failure.
sim/erc32/ChangeLog:

        * Makefile.in: Include build directory in search path to find
        config.h
2013-03-14 23:33:57 +00:00
Nick Clifton
67d7515b0a * simops.c (v850_rotl): New function.
(v850_bins): New function.
	* simops.h: Add prototypes fir v850_rotl and v850_bins.
	* v850-dc: Add entries for V850e3v5.
	* v850.igen: Add support for v850e3v5.
	(ld.dw, st.dw, rotl, bins): New patterns.
2013-01-28 10:06:51 +00:00
Anthony Green
9c9e1b263d Remove debug output 2013-01-17 09:44:53 +00:00
Nick Clifton
04e65a62c6 * rx.c (decode_opcode): Handle RXO_satr. 2013-01-16 10:45:22 +00:00
Nick Clifton
853678261b * interp.c (sim_open): Add support for bfd_arch_v850_rh850
architecture type.  Add support for bfd_mach_v850e2 and
	bfd_mach_v850e2v3 machine numbers.
        * v850.igen (dbtrap): Add support for SIM_OPEN_DEBUG.
        (cmpf.d): Correct order of operands.
        (cmpf.s): Likewise.
        (trncf.dul): New pattern.
        (trncf.duw): New pattern.
        (trncf.sul): New pattern.
        (trncf.suw): New pattern.
        * v850-dc: Correct bitfield selection for TRNCF.SW and CVTF.SW.
2013-01-10 09:57:02 +00:00
Nick Clifton
69276d0264 * mem.c (MDBL): Correct value.
(MDBH): Correct value.
2013-01-08 15:05:00 +00:00
Joel Brobecker
8acc9f485b Update years in copyright notice for the GDB files.
Two modifications:
  1. The addition of 2013 to the copyright year range for every file;
  2. The use of a single year range, instead of potentially multiple
     year ranges, as approved by the FSF.
2013-01-01 06:41:43 +00:00
Joel Brobecker
048a61aa6b Revert GPL version change in sim/bfin/aclocal.m4
sim/bfin/ChangeLog:

        * aclocal.m4: Revert the previous change changing
        the license from GPL v2 or later to GPL v3 or later
        (this file was generated).
2012-12-20 05:01:54 +00:00
Joel Brobecker
d2cec11135 Revert GPL version change in linux-fixed-code.s.
sim/bfin/ChangeLog:

	* linux-fixed-code.s: Revert the previous change changing
	the license from GPL v2 or later to GPL v3 or later.
2012-12-20 04:18:53 +00:00
Joel Brobecker
19a3671ce8 Update sim's COPYING files.
sim/arm/ChangeLog:

	* COPYING: Update to GPL version 3.

sim/ppc/ChangeLog:

	* COPYING: Update to GPL version 3.
2012-12-19 07:19:14 +00:00
Joel Brobecker
51b318dec8 [sim] Update old contact info in GPL license notices
sim/ChangeLog:

        Update old contact info in GPL license notices.
2012-12-19 07:18:22 +00:00
Joel Brobecker
3fd725ef34 Update sim copyright headers from GPLv2-or-later to GPLv3-or-later.
gdb/sim/ChangeLog:

        Update the non-FSF-copyrighted files in sim to GPLv3 or later.
2012-12-19 07:12:02 +00:00
H.J. Lu
6bb11ab3b2 Fix sim build when configured with --enable-plugins
* common/Make-common.in: Use lt_cv_dlopen_libs under PLUGINS
	condition.
	* common/acinclude.m4: Define lt_cv_dlopen_libs.
	* arm/configure: Regenerate.
	* avr/configure: Regenerate.
	* bfin/configure: Regenerate.
	* common/configure: Regenerate.
	* cr16/configure: Regenerate.
	* cris/configure: Regenerate.
	* d10v/configure: Regenerate.
	* erc32/configure: Regenerate.
	* frv/configure: Regenerate.
	* h8300/configure: Regenerate.
	* igen/configure: Regenerate.
	* iq2000/configure: Regenerate.
	* lm32/configure: Regenerate.
	* m32c/configure: Regenerate.
	* m32r/configure: Regenerate.
	* m68hc11/configure: Regenerate.
	* mcore/configure: Regenerate.
	* microblaze/configure: Regenerate.
	* mips/configure: Regenerate.
	* mn10300/configure: Regenerate.
	* moxie/configure: Regenerate.
	* ppc/configure: Regenerate.
	* rl78/configure: Regenerate.
	* rx/configure: Regenerate.
	* sh/configure: Regenerate.
	* sh64/configure: Regenerate.
	* testsuite/configure: Regenerate.
	* v850/configure: Regenerate.
2012-11-20 14:41:26 +00:00
Stephane Carrez
2d1ef085ab * MAINTAINERS: Update my email address. 2012-11-05 22:08:10 +00:00
Steve Ellcey
37cb8f8e70 2012-10-04 Chao-ying Fu <fu@mips.com>
Steve Ellcey  <sellcey@mips.com>

	* mips/mips3264r2.igen (rdhwr): New.
2012-10-03 21:11:46 +00:00
Steve Ellcey
c429cfcf4b Forgot to include ChangeLog in last checkin. 2012-09-24 18:04:03 +00:00
Steve Ellcey
cc2202431b 2012-09-24 Steve Ellcey <sellcey@mips.com>
* mips/basic.exp: Add mips*-mti-elf* target.
	* configure.ac: Add mips*-mti-elf* target.
	* configure: Regenerate.
2012-09-24 18:03:18 +00:00
Nick Clifton
d99ff40fae * v850.igen (W,WWWW): Correct computation of register number.
(JR32): Remove unnecessary comma.
	(cmovf.s): Register 0 is an invalid source register.
	(maddf.s): Remove bogus intermediary rounding.
	(nmaddf.s): Likewise.
	(trncf.sl): Remove bogus initial rounding.
	(trncf.dw): Likewise.
	(trncf.sl): Likewise.
	(trncf.sw): Likewise.
2012-09-13 08:09:26 +00:00