* interp.c (sim_open): Add support for bfd_arch_v850_rh850
architecture type. Add support for bfd_mach_v850e2 and bfd_mach_v850e2v3 machine numbers. * v850.igen (dbtrap): Add support for SIM_OPEN_DEBUG. (cmpf.d): Correct order of operands. (cmpf.s): Likewise. (trncf.dul): New pattern. (trncf.duw): New pattern. (trncf.sul): New pattern. (trncf.suw): New pattern. * v850-dc: Correct bitfield selection for TRNCF.SW and CVTF.SW.
This commit is contained in:
parent
a3c629886c
commit
853678261b
4 changed files with 121 additions and 16 deletions
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@ -1,3 +1,17 @@
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2013-01-10 Nick Clifton <nickc@redhat.com>
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* interp.c (sim_open): Add support for bfd_arch_v850_rh850
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architecture type. Add support for bfd_mach_v850e2 and
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bfd_mach_v850e2v3 machine numbers.
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* v850.igen (dbtrap): Add support for SIM_OPEN_DEBUG.
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(cmpf.d): Correct order of operands.
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(cmpf.s): Likewise.
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(trncf.dul): New pattern.
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(trncf.duw): New pattern.
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(trncf.sul): New pattern.
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(trncf.suw): New pattern.
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* v850-dc: Correct bitfield selection for TRNCF.SW and CVTF.SW.
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2012-09-13 Nick Clifton <nickc@redhat.com>
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* v850.igen (W,WWWW): Correct computation of register number.
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@ -267,7 +267,8 @@ sim_open (kind, cb, abfd, argv)
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/* determine the machine type */
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if (STATE_ARCHITECTURE (sd) != NULL
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&& STATE_ARCHITECTURE (sd)->arch == bfd_arch_v850)
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&& (STATE_ARCHITECTURE (sd)->arch == bfd_arch_v850
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|| STATE_ARCHITECTURE (sd)->arch == bfd_arch_v850_rh850))
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mach = STATE_ARCHITECTURE (sd)->mach;
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else
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mach = bfd_mach_v850; /* default */
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@ -278,6 +279,8 @@ sim_open (kind, cb, abfd, argv)
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case bfd_mach_v850:
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case bfd_mach_v850e:
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case bfd_mach_v850e1:
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case bfd_mach_v850e2:
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case bfd_mach_v850e2v3:
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STATE_CPU (sd, 0)->psw_mask = (PSW_NP | PSW_EP | PSW_ID | PSW_SAT
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| PSW_CY | PSW_OV | PSW_S | PSW_Z);
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break;
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@ -42,7 +42,7 @@
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# for trncf.sw, cvtf.sw
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switch,combine : 0 : 0 : : : : 0 :F_I : v850e2v3
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switch,combine : 3 : 3 : : : : 0 :F_I : v850e2v3
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switch,combine : 4 : 0 : : : : 0 :F_I : v850e2v3
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# for rsqrtf.s, sqrtf.s
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switch,combine : 1 : 1 : : : : 0 :F_I : v850e2v3
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@ -2179,12 +2179,19 @@ rrrrr,110101,RRRRR + iiiiiiiiiiiiiiii:VI:::xori
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*v850e2v3
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"dbtrap"
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{
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DBPC = cia + 2;
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DBPSW = PSW;
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PSW = PSW | (PSW_NP | PSW_EP | PSW_ID);
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PC = 0x00000060;
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nia = 0x00000060;
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TRACE_BRANCH0 ();
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if (STATE_OPEN_KIND (SD) == SIM_OPEN_DEBUG)
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{
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sim_engine_halt (SD, CPU, NULL, cia, sim_stopped, SIM_SIGTRAP);
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}
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else
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{
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DBPC = cia + 2;
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DBPSW = PSW;
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PSW = PSW | (PSW_NP | PSW_EP | PSW_ID);
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PC = 0x00000060;
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nia = 0x00000060;
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TRACE_BRANCH0 ();
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}
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}
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// New breakpoint: 0x7E0 0x7E0
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@ -2374,8 +2381,8 @@ rrrrr,111111,RRRRR!0 + wwwww!0,1000000,bbb,0:F_I:::cmovf_s
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// CMPF.D
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rrrr,0111111,RRRR,0 + 0,FFFF,1000011,bbb,0:F_I:::cmpf_d
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*v850e2v3
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"cmpf.d %s<FFFF>, r<reg1e>, r<reg2e>":(bbb == 0)
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"cmpf.d %s<FFFF>, r<reg1e>, r<reg2e>, <bbb>"
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"cmpf.d %s<FFFF>, r<reg2e>, r<reg1e>":(bbb == 0)
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"cmpf.d %s<FFFF>, r<reg2e>, r<reg1e>, <bbb>"
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{
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int result;
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sim_fpu wop1;
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@ -2383,9 +2390,9 @@ rrrr,0111111,RRRR,0 + 0,FFFF,1000011,bbb,0:F_I:::cmpf_d
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sim_fpu_232to (&wop1, GR[reg1e+1], GR[reg1e]);
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sim_fpu_232to (&wop2, GR[reg2e+1], GR[reg2e]);
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TRACE_FP_INPUT_FPU2 (&wop1, &wop2);
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TRACE_FP_INPUT_FPU2 (&wop2, &wop1);
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result = v850_float_compare(sd, FFFF, wop1, wop2, 1);
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result = v850_float_compare(sd, FFFF, wop2, wop1, 1);
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if (result)
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SET_FPCC(bbb);
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@ -2398,8 +2405,8 @@ rrrr,0111111,RRRR,0 + 0,FFFF,1000011,bbb,0:F_I:::cmpf_d
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// CMPF.S
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rrrrr,111111,RRRRR + 0,FFFF,1000010,bbb,0:F_I:::cmpf_s
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*v850e2v3
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"cmpf.s %s<FFFF>, r<reg1>, r<reg2>":(bbb == 0)
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"cmpf.s %s<FFFF>, r<reg1>, r<reg2>, <bbb>"
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"cmpf.s %s<FFFF>, r<reg2>, r<reg1>":(bbb == 0)
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"cmpf.s %s<FFFF>, r<reg2>, r<reg1>, <bbb>"
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{
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int result;
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sim_fpu wop1;
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@ -2407,9 +2414,9 @@ rrrrr,111111,RRRRR + 0,FFFF,1000010,bbb,0:F_I:::cmpf_s
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sim_fpu_32to( &wop1, GR[reg1] );
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sim_fpu_32to( &wop2, GR[reg2] );
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TRACE_FP_INPUT_FPU2 (&wop1, &wop2);
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TRACE_FP_INPUT_FPU2 (&wop2, &wop1);
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result = v850_float_compare(sd, FFFF, wop1, wop2, 0);
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result = v850_float_compare(sd, FFFF, wop2, wop1, 0);
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if (result)
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SET_FPCC(bbb);
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@ -3197,6 +3204,27 @@ rrrr,011111100001 + wwww,010001010100:F_I:::trncf_dl
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TRACE_FP_RESULT_WORD2 (GR[reg3e], GR[reg3e+1]);
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}
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// TRNCF.DUL
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rrrr,011111110001 + wwww,010001010100:F_I:::trncf_dul
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*v850e2v3
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"trncf.dul r<reg2e>, r<reg3e>"
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{
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signed64 ans;
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sim_fpu wop;
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sim_fpu_status status;
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sim_fpu_232to (&wop, GR[reg2e+1], GR[reg2e]);
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TRACE_FP_INPUT_FPU1 (&wop);
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status = sim_fpu_to64u (&ans, &wop, sim_fpu_round_zero);
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check_cvt_fi(sd, status, 1);
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GR[reg3e] = ans;
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GR[reg3e+1] = ans>>32L;
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TRACE_FP_RESULT_WORD2 (GR[reg3e], GR[reg3e+1]);
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}
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// TRNCF.DW
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rrrr,011111100001 + wwwww,10001010000:F_I:::trncf_dw
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*v850e2v3
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TRACE_FP_RESULT_WORD1 (ans);
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}
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// TRNCF.DUW
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rrrr,011111110001 + wwwww,10001010000:F_I:::trncf_duw
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*v850e2v3
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"trncf.duw r<reg2e>, r<reg3>"
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{
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uint32 ans;
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sim_fpu wop;
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sim_fpu_status status;
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sim_fpu_232to (&wop, GR[reg2e+1], GR[reg2e]);
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TRACE_FP_INPUT_FPU1 (&wop);
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status = sim_fpu_to32u (&ans, &wop, sim_fpu_round_zero);
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check_cvt_fi(sd, status, 1);
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GR[reg3] = ans;
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TRACE_FP_RESULT_WORD1 (ans);
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}
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// TRNCF.SL
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rrrrr,11111100001 + wwww,010001000100:F_I:::trncf_sl
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*v850e2v3
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TRACE_FP_RESULT_WORD2 (GR[reg3e], GR[reg3e+1]);
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}
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// TRNCF.SUL
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rrrrr,11111110001 + wwww,010001000100:F_I:::trncf_sul
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*v850e2v3
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"trncf.sul r<reg2>, r<reg3e>"
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{
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signed64 ans;
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sim_fpu wop;
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sim_fpu_status status;
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sim_fpu_32to (&wop, GR[reg2]);
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TRACE_FP_INPUT_FPU1 (&wop);
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status = sim_fpu_to64u (&ans, &wop, sim_fpu_round_zero);
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GR[reg3e] = ans;
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GR[reg3e+1] = ans >> 32L;
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TRACE_FP_RESULT_WORD2 (GR[reg3e], GR[reg3e+1]);
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}
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// TRNCF.SW
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rrrrr,11111100001 + wwwww,10001000000:F_I:::trncf_sw
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*v850e2v3
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GR[reg3] = ans;
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TRACE_FP_RESULT_WORD1 (ans);
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}
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// TRNCF.SUW
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rrrrr,11111110001 + wwwww,10001000000:F_I:::trncf_suw
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*v850e2v3
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"trncf.suw r<reg2>, r<reg3>"
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{
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uint32 ans;
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sim_fpu wop;
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sim_fpu_status status;
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sim_fpu_32to (&wop, GR[reg2]);
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TRACE_FP_INPUT_FPU1 (&wop);
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status = sim_fpu_to32u (&ans, &wop, sim_fpu_round_zero);
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check_cvt_fi(sd, status, 0);
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GR[reg3] = ans;
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TRACE_FP_RESULT_WORD1 (ans);
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}
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