Andrew Cagney
baa7ae6f10
When SIM_HAVE_ENVIRONMENT: use sim_set_trace() to enable tracing
...
instead of sim_trace() to run the program; include support for ``-o''
option (operating environment); when a signal occurs, only continue
execution when operating environment mode.
Update d10v.
2000-02-22 08:52:21 +00:00
Jason Molenda
c3f6f71df3
import gdb-2000-01-05 snapshot
2000-01-06 03:07:20 +00:00
Jason Molenda
4ce44c668d
import gdb-1999-11-16 snapshot
1999-11-17 02:31:06 +00:00
Jason Molenda
cff3e48be7
import gdb-1999-09-13 snapshot
1999-09-13 21:40:00 +00:00
Stan Shebs
c906108c21
Initial creation of sourceware repository
1999-04-16 01:35:26 +00:00
Stan Shebs
071ea11e85
Initial creation of sourceware repository
1999-04-16 01:34:07 +00:00
Andrew Cagney
93c6a010dc
Test switching between SPI/SPU.
1998-02-13 05:19:02 +00:00
Andrew Cagney
86b46474fd
Update tests to match recently modified ABI
1998-02-11 07:12:48 +00:00
Andrew Cagney
38d0ccc27a
Fix typo, REP_S was refering to REP_E register.
...
Add test.
1997-12-08 23:44:11 +00:00
Andrew Cagney
bc6df23d14
For "trap", IBT and RIE exceptions, mask all PSW.SM. NB: Stepping
...
through an exception may not work correctly.
For GDB reads/writes to the control registers, ensure the cpu state is
updated correctly.
1997-12-08 03:22:58 +00:00
Andrew Cagney
7f48c9fe1d
Add DM (bit 4) to PSW. See 7-1 for more info.
...
Test.
1997-12-04 07:01:30 +00:00
Andrew Cagney
aa49c64f3e
* d10v_sim.h (SEXT56): Define.
...
* simops.c (OP_4201): For "rac", sign extend 56 bit value before
it is shifted.
* d10v_sim.h (MAX32, MIN32, MASK32, MASK40): Re-define using
SIGNED64 macro.
1997-12-03 08:03:33 +00:00
Andrew Cagney
d294a657d5
For "msbu", subtract unsigned product from ACC,
...
Test.
1997-12-02 07:18:53 +00:00
Andrew Cagney
9420287ed2
For "mulxu", store unsigned product in ACC.
...
Test.
1997-12-02 06:37:09 +00:00
Andrew Cagney
51b057f27b
For sub2w, compute carry according to negated addition rules.
...
Test.
1997-12-02 00:27:27 +00:00
Andrew Cagney
51624b4bf6
Test rachi instruction.
1997-11-10 08:27:15 +00:00
