When generating relocation (tc_gen_reloc) 32 bit relocation fixup
is changed to new 32 bit PC relative relocation if the fixup has pc-relative
flag set.
bfd/ChangeLog
2015-07-06 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
* elf32-avr.c: Add 32 bit PC relative relocation for AVR target.
gas/ChangeLog
2015-07-06 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
* config/tc-avr.c (tc_gen_reloc): Change 32 bit relocation to
32 bit PC relative and update offset if the fixup is pc-relative.
* config/tc-avr.h (DIFF_EXPR_OK): Define to enable PC relative diff
relocs.
gas/testsuite/ChangeLog
2015-07-06 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
* gas/avr/pc-relative-reloc.d: New test for 32 bit pc relative reloc.
* gas/avr/per-function-debugline.s: New test source.
include/ChangeLog
2015-07-06 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
* elf/avr.h: Add new 32 bit PC relative relocation.
ld/testsuite/ChangeLog
2015-07-06 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
* ld-avr/gc-section-debugline.d: New test.
* ld-avr/per-function-debugline.s: Source for new test.
Back in the day support for these processors was added, we probably
didn't want to waste PPC_OPCODE bits on minor variations. I've had a
complaint that disassembly of mfspr/mtspr was wrong for power8. This
patch fixes that problem.
Note that since -m860/-m850/-m821 are new gas options enabling the
mpc8xx specific mfspr/mtspr variants it is possible that this change
will break some mpc8xx assembly code. ie. you might need to modify
makefiles to pass -m860 to gas.
include/opcode/
* ppc.h (PPC_OPCODE_750, PPC_OPCODE_7450, PPC_OPCODE_860): Define.
opcodes/
* ppc-opc.c (PPC750, PPC7450, PPC860): Define using PPC_OPCODE_*.
* ppc-dis.c (ppc_opts): Add 821, 850 and 860 entries. Add
PPC_OPCODE_7450 to 7450 entry. Add PPC_OPCODE_750 to 750cl entry.
gas/
* config/tc-ppc.c (md_show_usage): Add -m821, -m850, -m860.
* doc/c-ppc.texi (PowerPC-Opts): Likewise.
gas/testsuite/
* gas/ppc/titan.d: Correct mfmcsrr0 disassembly.
include * dis-asm.h (struct disassemble_info): Add stop_vma field.
binuti * objdump.c (disassemble_bytes): Set the stop_vma field in the
disassemble_info structure when disassembling code sections with
-d.
* doc/binutils.texi (objdump): Document the discrepancy between -d
and -D.
opcodes * dis-buf.c (buffer_read_memory): Fail is stop_vma is set and the
requested region lies beyond it.
* bfin-dis.c (print_insn_bfin): Ignore sysop instructions when
looking for 32-bit insns.
* mcore-dis.c (print_insn_mcore): Disable stop_vma when reading
data.
* sh-dis.c (print_insn_sh): Likewise.
* tic6x-dis.c (print_insn_tic6x): Disable stop_vma when reading
blocks of instructions.
* vax-dis.c (print_insn_vax): Check that the requested address
does not clash with the stop_vma.
tests * gas/arm/backslash-at.s: Add extra .byte directives so that the
foo symbol does not appear to point half way through an
instruction.
* gas/arm/backslash-at.d: Update expected disassembly.
* gas/i386/ilp32/x86-64-opcode-inval-intel.d: Likewise.
* gas/i386/ilp32/x86-64-opcode-inval.d: Likewise.
* gas/i386/x86-64-opcode-inval-intel.d: Likewise.
* gas/i386/x86-64-opcode-inval.d: Likewise.
ISA 2.07 (ie, POWER8) added the rfebb instruction which takes one operand
with the value of either a 0 or 1. It also defines an extended mnemonic
with no operands (ie, "rfebb") that is supposed to be equivalent to "rfebb 1".
I implemented rfebb's lone operand with PPC_OPERAND_OPTIONAL, but the
problem is, optional operands that are ommitted always default to the
value 0, which is wrong in this case. I have added support for allowing
non-zero default values by adding an additional flag PPC_OPERAND_OPTIONAL_VALUE
that specifies that the default operand value to be used is stored in the
SHIFT field of the operand field immediately following this one.
This fixes the rfebb issue. I also fixed the mftb and mfcr instructions
so they use the same mechanism. This allows us to flag invalid uses of
mfcr where we explicitly pass in a zero FXM value, like the use in a2.[sd].
include/opcode/
* ppc.h (PPC_OPERAND_OPTIONAL_VALUE): New.
(ppc_optional_operand_value): New inline function.
opcodes/
* ppc-dis.h (skip_optional_operands): Use ppc_optional_operand_value.
* ppc-opc.c (FXM4): Add non-zero optional value.
(TBR): Likewise.
(SXL): Likewise.
(insert_fxm): Handle new default operand value.
(extract_fxm): Likewise.
(insert_tbr): Likewise.
(extract_tbr): Likewise.
gas/
* config/tc-ppc.c (md_assemble): Use ppc_optional_operand_value.
Allow for optional operands without insert functions.
gas/testsuite/
* gas/ppc/power8.d: Fixup rfebb test results.
* gas/ppc/a2.s: Fix invalid mfcr test.
* gas/ppc/a2.d: Likewise.
When tracing, we often want to display the human readable name for the
various syscall/errno values. Rather than make each target duplicate
the lookup, extend the existing maps to include the string directly,
and add helper functions to look up the constants.
While most targets are autogenerated (from libgloss), the bfin/cris
targets have custom maps for the Linux ABI which need to be updated
by hand.
The ARMv8.1 architecture introduced the Privileged Access Never extension. This
adds a processor state field PSTATE.PAN which can be accessed using the MRS/MSR
instructions.
This patch adds support for the PAN architecture feature and processor state
field to libopcode.
include/opcode
2015-06-01 Matthew Wahab <matthew.wahab@arm.com>
* aarch64.h (AARCH64_FEATURE_PAN): New.
(aarch64_sys_reg_supported_p): Declare.
(aarch64_pstatefield_supported_p): Declare.
opcodes/
2015-06-01 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-opc.c (F_ARCHEXT): New.
(aarch64_sys_regs): Add "pan".
(aarch64_sys_reg_supported_p): New.
(aarch64_pstatefields): Add "pan".
(aarch64_pstatefield_supported_p): New.
Merge with gcc:
2014-11-11 Anthony Brandon <anthony.brandon@gmail.com>
Manuel López-Ibáñez <manu@gcc.gnu.org>
PR driver/36312
* filenames.h: Add prototype for canonical_filename_eq.
Taking them out showed a bug in the powerpc64 backend with .branch_lt
being removed from output_bfd but not from previously set up segment
section maps. Removing the bfd sections meant their sh_flags (and
practically everything else) remaining zero, ie. not SHF_ALLOC,
triggering complaints about "`.branch_lt' can't be allocated in
segment".
include/elf/
* internal.h (ELF_SECTION_IN_SEGMENT_1): Ensure PT_LOAD and
similar segments only contain alloc sections.
ld/
* emultempl/ppc64elf.em (gld${EMULATION_NAME}_after_allocation):
Call gld${EMULATION_NAME}_map_segments regardless of need_laying_out.
ld/testsuite/
* ld-powerpc/tocnovar.d: Revert last change.
Bits in section flags should only be defined in bfd/section.c. This
patch moves SEC_MEP_VLIW to bfd/section.c.
bfd/
PR binutils/18316
* section.c (SEC_MEP_VLIW): New.
* bfd-in2.h: Regenerated.
include/elf/
PR binutils/18316
* mep.h (SEC_MEP_VLIW): Removed.
This patch adds --compress-debug-sections=[none|zlib|zlib-gnu|zlib-gabi]
to ld for ELF targets to support generating compressed DWARF debug
sections. We always generate .zdebug_* section since section names have
been finalized and they can't be changed easily when compression is
being performed.
bfd/
* bfd-in.h (compressed_debug_section_type): New.
* compress.c (bfd_compress_section_contents): Add an argument
for linker write compression and always generate .zdebug_*
section when linking.
(bfd_init_section_compress_status): Pass FALSE to
bfd_compress_section_contents.
(bfd_compress_section): New function.
* elf.c (elf_fake_sections): For linking, set SEC_ELF_COMPRESS
on DWARF debug sections if COMPRESS_DEBUG is set and rename
section if COMPRESS_DEBUG_GABI_ZLIB isn't set.
(assign_file_positions_for_non_load_sections): Set sh_offset
to -1 if SEC_ELF_COMPRESS is set.
(assign_file_positions_except_relocs): Likwise.
(_bfd_elf_assign_file_positions_for_relocs): Renamed to ...
(_bfd_elf_assign_file_positions_for_non_load): This. Change
return time to bfd_boolean. Compress the section if
SEC_ELF_COMPRESS is set.
(_bfd_elf_write_object_contents): Updated.
(_bfd_elf_set_section_contents): Write section contents to
the buffer if SEC_ELF_COMPRESS is set.
* merge.c: Include "elf-bfd.h".
(sec_merge_emit): Add arguments for contents and offset. Write
to contents with offset if contents isn't NULL.
(_bfd_write_merged_section): Write section contents to the
buffer if SEC_ELF_COMPRESS is set. Pass contents and
output_offset to sec_merge_emit.
* elflink.c (bfd_elf_final_link): Allocate the buffer for
output section contents if SEC_ELF_COMPRESS is set.
* section.c (SEC_ELF_COMPRESS): New.
* bfd-in2.h: Regenerated.
gas/
* as.h (compressed_debug_section_type): Removed.
include/
* bfdlink.h (bfd_link_info): Add compress_debug.
ld/
* ld.texinfo: Document --compress-debug-sections=.
* ldmain.c (main): Set BFD_COMPRESS on output_bfd if
COMPRESS_DEBUG is set. Set BFD_COMPRESS_GABI on output_bfd
for COMPRESS_DEBUG_GABI_ZLIB.
* lexsup.c (elf_static_list_options): Add
--compress-debug-sections=.
* emultempl/elf32.em (OPTION_COMPRESS_DEBUG): New.
(xtra_long): Add "compress-debug-sections".
(gld${EMULATION_NAME}_handle_option): Handle
OPTION_COMPRESS_DEBUG.
ld/testsuite/
* ld-elf/compress.exp (build_tests): Add tests for
--compress-debug-sections=.
(run_tests): Likewise.
Add additonal tests for --compress-debug-sections=.
* ld-elf/gabiend.rt: New file.
* ld-elf/gabinormal.rt: Likewise.
* ld-elf/gnubegin.rS: Likewise.
* ld-elf/gnunormal.rS: Likewise.
* ld-elf/zlibbegin.rS: Likewise.
* ld-elf/zlibnormal.rS: Likewise.
Address of protected data defined in the shared library may be external,
i.e., due to copy relocation. By default, linker backend checks if
relocations against protected data symbols are valid for building shared
library and issues an error if relocation isn't allowed. The new option
override linker backend default. When -z noextern-protected-data is used,
updates on protected data symbols by another module won't be visibile
to the resulting shared library. This option is specific to ELF/i386
and ELF/x86-64.
bfd/
PR ld/pr17709
* elflink.c (_bfd_elf_adjust_dynamic_copy): Check
info->extern_protected_data when warning copy relocs against
protected symbols.
(_bfd_elf_symbol_refs_local_p): Check info->extern_protected_data
when checking protected non-function symbols.
include/
PR ld/pr17709
* bfdlink.h (bfd_link_info): Add extern_protected_data.
ld/
PR ld/pr17709
* ld.texinfo: Document "-z noextern-protected-data".
* ldmain.c (main): Initialize link_info.extern_protected_data
to -1.
* lexsup.c (elf_shlib_list_options): Add
"-z [no]extern-protected-data".
* emulparams/elf32_x86_64.sh: Source extern_protected_data.sh.
* emulparams/elf_i386.sh: Likewise.
* emulparams/elf_i386_be.sh: Likewise.
* emulparams/elf_i386_chaos.sh: Likewise.
* emulparams/elf_i386_ldso.sh: Likewise.
* emulparams/elf_i386_vxworks.sh: Likewise.
* emulparams/elf_k1om.sh: Likewise.
* emulparams/elf_l1om.sh: Likewise.
* emulparams/elf_x86_64.sh: Source extern_protected_data.sh.
(PARSE_AND_LIST_OPTIONS): Renamed to ...
(PARSE_AND_LIST_OPTIONS_BNDPLT): This.
(PARSE_AND_LIST_ARGS_CASE_Z): Renamed to ...
(PARSE_AND_LIST_ARGS_CASE_Z_BNDPLT): This.
(PARSE_AND_LIST_OPTIONS): Append $PARSE_AND_LIST_OPTIONS_BNDPLT.
(PARSE_AND_LIST_ARGS_CASE_Z): Append
$PARSE_AND_LIST_ARGS_CASE_Z_BNDPLT.
* emulparams/extern_protected_data.sh: New file.
ld/testsuite/
PR ld/pr17709
* ld-i386/i386.exp: Run protected6b.
* ld-i386/protected6b.d: New file.
* ld-x86-64/protected6b.d: Likewise.
* ld-x86-64/x86-64.exp: Run protected6b.
bfd * elf32-rx.c (describe_flags): Report the settings of the string
insn using bits.
(rx_elf_merge_private_bfd_data): Handle merging of the string insn
using bits.
bin * readelf.c (get_machine_flags): Report the setting of the string
insn using bits.
gas * config/tc-rx.c (enum options): Add OPTION_DISALLOW_STRING_INSNS.
(md_longopts): Add -mno-allow-string-insns.
(md_parse_option): Handle -mno-allow-string-insns.
(md_show_usage): Mention -mno-allow-string-insns.
(rx_note_string_insn_use): New function. Produces an error
message if a string insn is used when it is not allowed.
* config/rx-parse.y (SCMPU): Call rx_note_string_insn_use.
(SMOVU, SMOVB, SMOVF, SUNTIL, SWHILE, RMPA): Likewise.
* config/rx-defs.h (rx_note_string_insn_use): Prototype.
* doc/c-rx.texi: Document -mno-allow-string-insns.
elf * rx.h (E_FLAG_RX_SINSNS_SET): New bit in e_flags field.
(E_FLAG_RX_SINSNS_YES): Likewise.
(E_FLAG_RX_SINSNS_MASK): New define.
inc * rl78.h (E_FLAG_RL78_G10): Redefine.
(E_FLAG_RL78_CPU_MASK, E_FLAG_RL78_ANY_CPU, E_FLAG_RL78_G13
E_FLAG_RL78_G14): New flags.
bin * readelf.c (get_machine_flags): Decode RL78's G13 and G14 flags.
gas * config/tc-rl78.c (enum options): Add G13 and G14.
(md_longopts): Add -mg13 and -mg14.
(md_parse_option): Handle -mg13 and -mg14.
(md_show_usage): List -mg13 and -mg14.
* doc/c-rl78.texi: Add description of -mg13 and -mg14 options.
bfd * elf32-rl78.c (rl78_cpu_name): New function. Prints the name of
the RL78 core based upon the flags.
(rl78_elf_merge_private_bfd_data): Handle merging of G13 and G14
flags.
(rl78_elf_print_private_bfd_data): Use rl78_cpu_name.
(elf32_rl78_machine): Always return bfd_mach_rl78.
Pull out the duplicated dv_sockser_install prototype from the tconfig.in
files and put it in the one place it gets used -- sim-module.c. This is
still arguably incorrect, but it's better than the status quo where the
tconfig.in has to include header files and duplicate the dv-sockser func.
The tconfig header is meant to be simple and contain a target defines.
bfd * elf32-v850.c (v850_set_note): New function. Creates a Renesas
style note entry.
(v850_elf_make_note_section): New function. Creates a note
section.
(v850_elf_create_sections): New function. Create a note section
if one is not already present.
(v850_elf_set_note): New function. Adds a note to a bfd.
(v850_elf_copy_private_bfd_data): New function. Copies V850
notes.
(v850_elf_merge_notes): New function. Merges V850 notes.
(print_v850_note): New function. Displays a V850 note.
(v850_elf_print_notes): New function. Displays all notes attached
to a bfd.
(v850_elf_merge_private_bfd_data): Call v850_elf_merge_notes.
(v850_elf_print_private_bfd_data): Call v850_elf_print_notes.
(v850_elf_fake_sections): Set the type of the V850 note section.
* bfd-in.h (v850_elf_create_sections): Add prototype.
(v850_elf_set_note): Add prototype.
* bfd-in2.h: Regenerate.
binutils* readelf.c (get_machine_flags): Remove deprecated V850 machine
flags.
(get_v850_section_type_name): New function. Handles V850 special
sections.
(get_section_type_name): Add support for V850.
(get_v850_elf_note_type): New function. Returns the name of a
V850 note.
(print_v850_note): New function. Prints a V850 note.
(process_v850_notes): New function. Prints V850 notes.
(process_note_sections): Add support for V850.
binutils/testsute
* binutils-all/objcopy.exp: Skip the strip-10 test for the V850.
gas * config/tc-v850.c (soft_float): New variable.
(v850_data_8): New variable.
(md_show_usage): Add -msoft-float/-mhard-float.
(md_parse_option): Likewise.
(md_begin): Set the default value of soft_float.
(v850_md_end): New function. Creates a note section.
* config/tc-v850.h (md_end): Define.
* doc/c-v850.texi: Document -msoft-float/-mhard-float.
gas/testsuite
* gas/elf/elf.exp: Add special version of the section2 test for
the V850.
* gas/elf/section2.e-v850: New file.
include/elf
* v850.h (EF_RH850_SIMD): Delete deprecated flag.
(EF_RH850_CACHE): Likewise.
(EF_RH850_MMU): Likewise.
(EF_RH850_DATA_ALIGN8): Likewise.
(SHT_RENESAS_IOP): Fix typo in name.
(SHT_RENESAS_INFO): Define.
(V850_NOTE_SECNAME): Define.
(SIZEOF_V850_NOTE): Define.
(V850_NOTE_NAME): Define.
(enum v850_notes): New enum.
(NUM_V850_NOTES): Define.
ld/ChangeLog
2015-02-24 Nick Clifton <nickc@redhat.com>
* Makefile.am (ev850.c): Add dependency upon
$(srcdir)/emultempl/v850elf.em.
(ev850_rh850.c): Likewise.
* Makefile.in: Regenerate.
* emultempl/v850elf.em: New file.
* emulparams/v850.sh (EXTRA_EM_FILE): Define.
* emulparams/v850_rh850.sh (EXTRA_EM_FILE): Define.
* scripttempl/v850.sc: Add .note.renesas section.
* scripttempl/v850_rh850.sc: Likewise.
ld/testsuite
* ld-elf/extract-symbol-1sec.d: Expect to fail on the V850.
The IBM z13 has new 128-bit wide vector registers v0-v31, where v0-v15
include the existing 64-bit wide floating point registers. The Linux
kernel presents the vector registers as two additional register sets,
one for the right halves of v0-v15 and another one for the full
registers v16-v31. Thus a new core file may contain two new register
note sections, and this patch adds support to binutils for them.
bfd/
* elf-bfd.h (elfcore_write_s390_vxrs_low): Add prototype.
(elfcore_write_s390_vxrs_high): Likewise.
* elf.c (elfcore_grok_s390_vxrs_low): New function.
(elfcore_grok_s390_vxrs_high): New function.
(elfcore_grok_note): Call them.
(elfcore_write_s390_vxrs_low): New function.
(elfcore_write_s390_vxrs_high): New function.
(elfcore_write_register_note): Call them.
binutils/
* readelf.c (get_note_type): Add NT_S390_VXRS_LOW and
NT_S390_VXRS_HIGH.
include/elf/
* common.h (NT_S390_VXRS_LOW): New macro.
(NT_S390_VXRS_HIGH): Likewise.
