The disasm framework reserves the private_data field for the disassemblers
themselves, not for people who use the disassembler. Instead, there is an
application_data field for callers such as the sim. Switch to it to avoid
random corruption/crashes when the disassemblers use private_data.
Pretty much all targets are using this module already, so add it to the
common list of objects. The only oddball out here is cris and that's
because it supports loading via an offset for all the phdrs. We drop
support for that.
No arch is using this anymore, and we want all new ports using the
hardware framework instead. Punt WITH_DEVICES and the two callbacks
device_io_{read,write}_buffer.
We can also punt the tconfig.h file as no port is using it anymore.
This fixes in-tree builds that get confused by picking up the wrong
one (common/ vs <port>/) caused by commit ae7d0cac8c.
Any port that needs to set up a global define can use their own
sim-main.h file that they must provide regardless.
The bfin port is using the WITH_DEVICES framework for two reasons:
- get access to the cpu making the request (if available)
- check the alignment & size for core & system MMRs
We addressed the first part with commit dea10706e9,
and we handle the second part with this commit. Arguably this is more
correct too because trying to do bad reads/writes directly (when devices
support is disabled) often results in bad memory accesses.
As part of this clean up, we also adjust all of the existing logic that
would reject invalid accesses: the code was relying on the checks never
returning, but that's not the case when things like gdb (via the user's
commands) are making the requests. Thus we'd still end up with bad mem
accesses, or sometimes gdb being hung due to while(1) loops.
Now we can connect (most of) these models into any address and have them
work correctly.
We set up an array of 3 elements and then index into it with a 2bit
value. We check the range before we actually use the pointer, but
the indexing is enough to make asan upset, so just stuff a fourth
value in there to keep things simple.
The bfin port has been using the device callback largely so it could be
passed the cpu when available. Add this logic to the common core code
so all ports get access to the active cpu.
The semantics of these buffer functions are changed slightly in that
errors halt the engine synchronously rather than returning the length
to the caller. We'll probably adjust this in a follow up commit.
The bfin code isn't updated just yet as it has a bit more logic in the
device layer that needs to be unwound at which point we can delete it
entirely.
The only unique thing about mip's sim_{read,write} helpers is the call to
address_translation on the incoming address. When we look closer at that
function though, we see it's just a stub that maps physical to virtual,
and the cache/return values are hardcoded. If we delete this function,
we can then collapse all the callers and drop the custom sim_{read,write}
logic entirely.
Some day we might want to add MMU support, but when we do, we'll want to
have the common layers handle things so all targets benefit.
The point of passing down the cpu to core reads/writes is to signal which
cpu is making the access. For system accesses (such as internal memory
initialization), passing the cpu down doesn't make sense, and in the case
of early init like cris, can cause crashes. Since the cpu isn't fully set
up at this point, if the core code tries to access some fields (like the
PC reg), it'll crash. While cris shouldn't be doing this setup here (it
should be in the inferior stage), we'll deal with that later.
For targets that process argv in sim_create_inferior, improve the code:
- provide more details in the comment
- make the check for when to re-init more robust
- clean out legacy sim_copy_argv code
This will be cleaned up more in the future when we have a common inferior
creation function, but at least help new ports get it right until then.
2015-12-24 Thomas Preud'homme <thomas.preudhomme@arm.com>
ld/testsuite/
* ld-arm/arm-elf.exp: Run new test "Thumb-Thumb farcall v6-M (no
profile)".
* ld-arm/farcall-thumb-thumb-m-no-profile-a.s: New file.
* ld-arm/farcall-thumb-thumb-m-no-profile-b.s: Likewise.
* ld-arm/farcall-thumb-thumb-m-no-profile.d: Likewise.
2015-12-25 Sandra Loosemore <sandra@codesourcery.com>
gdb/testsuite/
* lib/gdb.exp (gdb_test): Update comments to clarify that the
PATTERN argument is optional.
The frv port used the device logic to support a single cache address,
and the comments around that are "these were merely copied from a diff
port and are unused", plus the code to attach the memory is "#if 0".
Just punt it all.
The m32r port was using the device framework to handle two devices: the
cache and uart registers. Both can be implemented in the newer hardware
framework instead which allows us to drop the device logic entirely, as
well as delete the tconfig.h file.
While creating the new uart device model, I also added support for using
stdin to read/write data rather than only supporting sockets.
This has been lightly tested as there doesn't appear to be test coverage
for the code already. If anyone still cares about this port, then they
should (hopefully) file bug reports.
The cris port was using the device framework to handle two addresses when
the --cris-900000xx flag was specified. That can be implemented using the
newer hardware framework instead which allows us to drop the device logic
entirely, as well as delete the tconfig.h file. Basically we create a new
cris_900000xx device model and move the read logic out of devices.c and
into that. The rest of the devices logic was callback to the hardware
framework already.
Much like we autodetect the path to the run program when there is none
set explicitly, do the same for the rvdummy program. Otherwise the
default make check fails to execute the helper properly.
These trace calls don't seem to add anything useful and break the cris
hw tests, so punt them. They were disabled before commit 6d519a4606
but were re-enabled as part of TRACE macro cleanups.
Rather than include this for some targets, set it up so we can build it
all the time via the common code. This makes it easier for targets to
opt into it when they're ready, increases build coverage, and allows us
to centralize much of the logic.
We also get to delete tconfig.h from two more targets -- they were
setting WITH_DEVICES to 0 which has the same behavior as not defining
it at all.
While the SIM_HAVE_MODEL knob is gone, we now have WITH_MODEL_P, but it
is only used by the common sim-model code. We use it to declare dummy
model lists when the arch hasn't created its own.
The "MACH" and "MODEL" names are a bit generic and collide with symbols
used by other sections of code (like h8300's opcodes). Since these are
sim-specific types, they really should have a "SIM_" prefix.
Only four targets implement this function, and three of them do nothing.
The 4th merely calls abort. Since calls to this function are followed
by calls to sim_hw_abort or sim_io_error, this is largely useless. In
the two places where we don't, replace the call with sim_engine_abort.
We want to kill off the WITH_DEVICES logic in favor of WITH_HW, so this
is a good first step.
We enable WITH_CALLBACK_MEMORY everywhere and don't provide a way to
turn it off, and no target does so. Make it unconditional for all
to keep things simple.
Since the core always provides CPU_INDEX, use it. The current code
doesn't actually use it even though it should since it doesn't include
the right headers.
Most targets already default to loading code via their LMA, but for
a few, this means the default changes from loading VMA to LMA. It's
better to have the different targets be consistent, and allows some
code clean up.
We've moved custom option install for other targets to sim_open, so update
cris too. It's the last one using MODULE_LIST, so we can drop that from
the common code too.
This code relies on the old sim-break module, but that was deleted in 2003.
The module only existed for gdb to tell the sim to set breakpoints on its
behalf, but then that logic was abandoned in favor of gdb knowing all about
proper breakpoints (since it does already for non-sim targets). Some dead
code lived on in the older ports though -- clean it up now.
We build & bundle the watchpoint module everywhere, but we don't make
the command line flags available by default. A few targets opted in,
but most did not. Just enable the flag for everyone. Not all targets
will respect the flags (making them nops), but shouldn't be a big deal.
This is how we handle other common modules already.
No target has used this, and it's a cheap hack in place in using the
common memory module. We want everyone using that though, so drop
support for flatmem entirely.
2015-12-24 Thomas Preud'homme <thomas.preudhomme@arm.com>
bfd/
(tag_cpu_arch_combine): Adjust comment in v4t_plus_v6_m with regards
to merging with ARMv8-M Baseline.
binutils/
* readelf.c (arm_attr_tag_CPU_arch): Add ARMv8-M Baseline Tag_CPU_arch
value.
gas/
* config/tc-arm.c (arm_ext_v6t2_v8m): New feature for instructions
shared between ARMv6T2 and ARMv8-M.
(move_or_literal_pool): Check mov.w/mvn and movw availability against
arm_ext_v6t2 and arm_ext_v6t2_v8m respectively instead of checking
arm_arch_t2.
(do_t_branch): Error out for wide conditional branch instructions if
targetting ARMv8-M Baseline.
(non_v6t2_wide_only_insn): Add the logic for new wide-only instructions
in ARMv8-M Baseline.
(wide_insn_ok): New function.
(md_assemble): Use wide_insn_ok instead of non_v6t2_wide_only_insn and
adapt error message for unsupported wide instruction to ARMv8-M
Baseline.
(insns): Reorganize instructions shared by ARMv8-M Baseline and
ARMv6t2 architecture.
(arm_cpus): Set feature bit ARM_EXT2_V6T2_V8M for marvell-pj4 and
marvell-whitney cores.
(arm_archs): Define armv8-m.base architecture.
(cpu_arch_ver): Define ARM_ARCH_V8M_BASE architecture version.
(aeabi_set_public_attributes): Add logic to set Tag_CPU_arch to 17 for
ARMv8-M Mainline. Set Tag_DIV_use for ARMv8-M Baseline as well.
gas/testsuite/
* gas/arm/archv8m-base.d: New file.
* gas/arm/attr-march-armv8m.base.d: Likewise.
* gas/arm/armv8m.base-idiv.d: Likewise.
* gas/arm/any-armv8m.d: Adapt to deal with ARMv8-M Baseline.
include/elf/
* arm.h (TAG_CPU_ARCH_V8M_BASE): Declare.
include/opcode/
* arm.h (ARM_EXT2_V6T2_V8M): New extension bit.
(ARM_AEXT2_V8A): New architecture extension bitfield.
(ARM_AEXT2_V8_1A): Use ARM_AEXT2_V8A instead of ARM_EXT2_ATOMICS.
(ARM_AEXT_V8M_BASE): New architecture extension bitfield.
(ARM_AEXT2_V8M): Add extension bit ARM_EXT2_V6T2_V8M.
(ARM_ARCH_V6T2): Use ARM_EXT2_V6T2_V8M for the second extension
bitfield.
(ARM_ARCH_V6KT2): Likewise.
(ARM_ARCH_V6ZT2): Likewise.
(ARM_ARCH_V6KZT2): Likewise.
(ARM_ARCH_V7): Likewise.
(ARM_ARCH_V7A): Likewise.
(ARM_ARCH_V7VE): Likewise.
(ARM_ARCH_V7R): Likewise.
(ARM_ARCH_V7M): Likewise.
(ARM_ARCH_V7EM): Likewise.
(ARM_ARCH_V8A): Likewise.
(ARM_ARCH_V8M_BASE): New architecture bitfield.
(ARM_ARCH_THUMB2): Include instructions shared by ARMv6t2 and ARMv8-M.
(ARM_ARCH_V7A_SEC): Use ARM_EXT2_V6T2_V8M for the second extension
bitfield and reindent.
(ARM_ARCH_V7A_MP_SEC): Likewise.
(ARM_ARCH_V7R_IDIV): Likewise.
(ARM_ARCH_V8A_FP): Use ARM_AEXT2_V8A instead of ARM_EXT2_ATOMICS.
(ARM_ARCH_V8A_SIMD): Likewise.
(ARM_ARCH_V8A_CRYPTOV1): Likewise.
opcodes/
* arm-dis.c (arm_opcodes): Guard movw, movt cbz, cbnz, clrex, ldrex,
ldrexb, ldrexh, strex, strexb, strexh shared by ARMv6T2 and ARMv8-M by
ARM_EXT2_V6T2_V8M instead of ARM_EXT_V6T2.
2015-12-24 Thomas Preud'homme <thomas.preudhomme@arm.com>
bfd/
(tag_cpu_arch_combine): Adjust v4t_plus_v6_m and comb array to account
for new TAG_CPU_ARCH_V4T_PLUS_V6_M value. Deal with NULL values in
comb array.
binutils/
* readelf.c (arm_attr_tag_CPU_arch): Add ARMv8-M Mainline Tag_CPU_arch
value.
(arm_attr_tag_THUMB_ISA_use): Add ARMv8-M Mainline Tag_THUMB_ISA_use
value.
gas/
* config/tc-arm.c (arm_ext_m): Include ARMv8-M.
(arm_ext_v8m): New feature for ARMv8-M.
(arm_ext_atomics): New feature for ARMv8 atomics.
(do_tt): New encoding function for TT* instructions.
(insns): Add new entries for ARMv8-M specific instructions and
reorganize the ones shared by ARMv8-M Mainline and ARMv8-A.
(arm_archs): Define armv8-m.main architecture.
(cpu_arch_ver): Define ARM_ARCH_V8M_MAIN architecture version and
clarify the ordering rule.
(aeabi_set_public_attributes): Use TAG_CPU_ARCH_* macro to refer to
Tag_CPU_arch values for ARMv7e-M detection. Add logic to keep setting
Tag_CPU_arch to ARMv8-A for -march=all. Also set Tag_CPU_arch_profile
to 'A' if extension bit for atomic instructions is set, unless it is
ARMv8-M. Set Tag_THUMB_ISA_use to 3 for ARMv8-M. Set Tag_DIV_use to 0
for ARMv8-M Mainline.
gas/testsuite/
* gas/arm/archv8m.s: New file.
* gas/arm/archv8m-main.d: Likewise.
* gas/arm/attr-march-armv8m.main.d: Likewise.
* gas/arm/any-armv8m.s: Likewise.
* gas/arm/any-armv8m.d: Likewise.
include/elf/
* arm.h (TAG_CPU_ARCH_V8M_MAIN): Declare.
(MAX_TAG_CPU_ARCH): Define to TAG_CPU_ARCH_V8M_MAIN.
(TAG_CPU_ARCH_V4T_PLUS_V6_M): Define to unused value 15.
include/opcode/
* arm.h (ARM_EXT2_ATOMICS): New extension bit.
(ARM_EXT2_V8M): Likewise.
(ARM_EXT_V8): Adjust comment with regards to atomics and remove
mention of legacy use for that bit.
(ARM_AEXT2_V8_1A): New architecture extension bitfield.
(ARM_AEXT2_V8_2A): Likewise.
(ARM_AEXT_V8M_MAIN): Likewise.
(ARM_AEXT2_V8M): Likewise.
(ARM_ARCH_V8A): Use ARM_EXT2_ATOMICS for features in second bitfield.
(ARM_ARCH_V8_1A): Likewise with ARM_AEXT2_V8_1A.
(ARM_ARCH_V8_2A): Likewise with ARM_AEXT2_V8_2A.
(ARM_ARCH_V8M_MAIN): New architecture feature bitfield.
(ARM_ARCH_V8A_FP): Use ARM_EXT2_ATOMICS for features in second bitfield
and reindent.
(ARM_ARCH_V8A_SIMD): Likewise.
(ARM_ARCH_V8A_CRYPTOV1): Likewise.
(ARM_ARCH_V8_1A_FP): Use ARM_AEXT2_V8_1A to set second bitfield of
feature bits.
(ARM_ARCH_V8_1A_SIMD): Likewise.
(ARM_ARCH_V8_1A_CRYPTOV1): Likewise.
opcodes/
* arm-dis.c (arm_opcodes): Guard lda, ldab, ldaex, ldaexb, ldaexh, stl,
stlb, stlh, stlex, stlexb and stlexh by ARM_EXT2_ATOMICS instead of
ARM_EXT_V8.
(thumb32_opcodes): Add entries for wide ARMv8-M instructions.
2015-12-24 Thomas Preud'homme <thomas.preudhomme@arm.com>
gas/
* config/tc-arm.c (move_or_literal_pool): Check mov.w, mvm and movw
availability against arm_ext_v6t2 instead of checking arm_arch_t2,
fixing comments along the way.
(handle_it_state): Check arm_ext_v6t2 instead of arm_arch_t2 to
generate IT instruction.
(t1_isa_t32_only_insn): New function.
(md_assemble): Use above new function to check for invalid wide
instruction for CPU Thumb ISA and to determine what Thumb extension
bit is necessary for that instruction.
(md_apply_fix): Use arm_ext_v6t2 instead of arm_arch_t2 to decide if
branch is out of range.
include/opcode/
* arm.h (ARM_ARCH_THUMB2): Add comment explaining its meaning and
remove extension bit not including any Thumb-2 instruction.
The current approach when building Ada programs for testing is
based on the use of a project file (testsuite/gdb.ada/gnat_ada.gpr).
To do that, we pass a number of additional arguments to target_compile,
one of them being the project file (via "-P/path/to/gnat_ada.gpr").
This used to work well-enough, but AdaCore is currently working towards
removing project-file support from gnatmake (the prefered tool for
using project files is gprbuild). So, we need to either switch
the compilation to gprbuild, or stop using project files.
First, using gprbuild is not always what users will be using to
build their applications. So having the option of using gnatmake
provides more flexibility towards exactly reproducing past bugs.
If we ever need a testcase that requires the use of gprbuild, then
I believe support for a new target needs to be added to dejagnu's
target_compile.
Also, the only real reason behind using a project file in the first
place is that we wanted to make it easy to specify the directory
where all compilation artifacts get stored. This is a consequence
of the organization choice we made for gdb.ada to keep each testcase
well organized. It is very easy to achieve that goal without using
project files.
This is therefore what this patch does: It change gdb_compile_ada
to build any program using gnatmake without using a project file
(by temporarily changing the current working directory).
There is a small (beneficial) side-effect; in the situation where
GDB is built in-tree, gnatmake is called as...
% gnatmake [...] unit.adb
... which means that the debugging info in unit.o will say contain
a filename whose name is 'unit.adb', rather than '/path/to/unit.adb'.
This also better matches what users might typically do. But the side-
effect is that the unit name in the GDB output is not always a full
path. This patch tweaks a couple of testcases to make the path part
optional.
gdb/testsuite:
* lib/ada.exp (target_compile_ada_from_dir): New function.
(gdb_compile_ada): Reimplement avoiding the use of project files.
* gdb.ada/gnat_ada.gpr: Delete.
* gdb.ada/cond_lang.exp: Adjust test to make path before
filename optional.
* gdb.ada/small_reg_param.exp: Likewise.
Tested on x86_64-linux, with both in-tree and out-of-tree builds.
One more I just found.
Tested with native, native-gdbserver and native-extended-gdbserver on
Linux.
gdb/testsuite/ChangeLog:
* gdb.base/foll-vork.exp: Remove HP-UX special case.
bfd * elf-bfd.h: Add callback to count additional relocations.
* elf32-arm.c (_arm_elf_section_data): Add new counter.
(insert_cantunwind_after): Increment relocations counter.
(elf32_arm_fix_exidx_coverage): Remove exidx entries and add
terminating CANTUNWIND entry only in final builds.
(elf32_arm_add_relocation): New function.
(elf32_arm_write_section): Add relocations in relocatable builds.
(elf32_arm_count_additional_relocs): New function.
(elf_backend_count_additional_relocs): New define.
* bfd/elflink.c (bfd_elf_final_link): Use callback and adjust size of
.rel section.
* bfd/elfxx-target.h (elf_backend_count_additional_relocs): New define.
ld * emultempl/armelf.em (gld${EMULATION_NAME}_after_allocation): Call
elf32_arm_fix_exidx_coverage for relocatable builds.
ld/testsuite
* ld-arm/arm-elf.exp: New test.
* ld-arm/unwind-rel.d: New file.
* ld-arm/unwind-rel1.s: New file.
* ld-arm/unwind-rel2.s: New file.
* ld-arm/unwind-rel3.s: New file.
