Consolidate Thumb-1/Thumb-2 ISA detection
2015-12-24 Thomas Preud'homme <thomas.preudhomme@arm.com>
gas/
* config/tc-arm.c (move_or_literal_pool): Check mov.w, mvm and movw
availability against arm_ext_v6t2 instead of checking arm_arch_t2,
fixing comments along the way.
(handle_it_state): Check arm_ext_v6t2 instead of arm_arch_t2 to
generate IT instruction.
(t1_isa_t32_only_insn): New function.
(md_assemble): Use above new function to check for invalid wide
instruction for CPU Thumb ISA and to determine what Thumb extension
bit is necessary for that instruction.
(md_apply_fix): Use arm_ext_v6t2 instead of arm_arch_t2 to decide if
branch is out of range.
include/opcode/
* arm.h (ARM_ARCH_THUMB2): Add comment explaining its meaning and
remove extension bit not including any Thumb-2 instruction.
This commit is contained in:
Thomas Preud'homme
parent
443bfd5a37
commit
fc289b0a83
4 changed files with 68 additions and 33 deletions
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@ -1,3 +1,17 @@
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2015-12-24 Thomas Preud'homme <thomas.preudhomme@arm.com>
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* config/tc-arm.c (move_or_literal_pool): Check mov.w, mvm and movw
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availability against arm_ext_v6t2 instead of checking arm_arch_t2,
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fixing comments along the way.
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(handle_it_state): Check arm_ext_v6t2 instead of arm_arch_t2 to
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generate IT instruction.
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(t1_isa_t32_only_insn): New function.
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(md_assemble): Use above new function to check for invalid wide
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instruction for CPU Thumb ISA and to determine what Thumb extension
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bit is necessary for that instruction.
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(md_apply_fix): Use arm_ext_v6t2 instead of arm_arch_t2 to decide if
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branch is out of range.
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2015-12-21 Nick Clifton <nickc@redhat.com>
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PR gas/19386
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@ -7869,10 +7869,10 @@ move_or_literal_pool (int i, enum lit_type t, bfd_boolean mode_3)
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return TRUE;
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}
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if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_arch_t2))
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if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2))
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{
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/* Check if on thumb2 it can be done with a mov.w or mvn.w
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instruction. */
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/* Check if on thumb2 it can be done with a mov.w, mvn or
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movw instruction. */
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unsigned int newimm;
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bfd_boolean isNegated;
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@ -7886,19 +7886,22 @@ move_or_literal_pool (int i, enum lit_type t, bfd_boolean mode_3)
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isNegated = TRUE;
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}
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/* The number can be loaded with a mov.w or mvn
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instruction. */
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if (newimm != (unsigned int) FAIL)
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{
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inst.instruction = (0xf04f0000
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inst.instruction = (0xf04f0000 /* MOV.W. */
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| (inst.operands[i].reg << 8));
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/* Change to MOVN. */
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inst.instruction |= (isNegated ? 0x200000 : 0);
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inst.instruction |= (newimm & 0x800) << 15;
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inst.instruction |= (newimm & 0x700) << 4;
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inst.instruction |= (newimm & 0x0ff);
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return TRUE;
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}
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/* The number can be loaded with a movw instruction. */
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else if ((v & ~0xFFFF) == 0)
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{
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/* The number can be loaded with a mov.w instruction. */
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int imm = v & 0xFFFF;
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inst.instruction = 0xf2400000; /* MOVW. */
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@ -17563,7 +17566,7 @@ handle_it_state (void)
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else
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{
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if ((implicit_it_mode & IMPLICIT_IT_MODE_THUMB)
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&& ARM_CPU_HAS_FEATURE (cpu_variant, arm_arch_t2))
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&& ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2))
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{
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/* Automatically generate the IT instruction. */
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new_automatic_it_block (inst.cond);
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@ -17795,6 +17798,22 @@ in_it_block (void)
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return now_it.state != OUTSIDE_IT_BLOCK;
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}
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/* Whether OPCODE only has T32 encoding and makes build attribute
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Tag_THUMB_ISA_use be set to 1 if assembled without any cpu or arch info. */
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static bfd_boolean
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t1_isa_t32_only_insn (const struct asm_opcode *opcode)
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{
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/* Original Thumb-1 wide instruction. */
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if (opcode->tencode == do_t_blx
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|| opcode->tencode == do_t_branch23
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|| ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_msr)
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|| ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_barrier))
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return TRUE;
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return FALSE;
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}
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void
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md_assemble (char *str)
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{
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@ -17854,24 +17873,24 @@ md_assemble (char *str)
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return;
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}
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if (!ARM_CPU_HAS_FEATURE (variant, arm_ext_v6t2))
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/* Two things are addressed here:
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1) Implicit require narrow instructions on Thumb-1.
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This avoids relaxation accidentally introducing Thumb-2
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instructions.
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2) Reject wide instructions in non Thumb-2 cores.
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Only instructions with narrow and wide variants need to be handled
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but selecting all non wide-only instructions is easier. */
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if (!ARM_CPU_HAS_FEATURE (variant, arm_ext_v6t2)
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&& !t1_isa_t32_only_insn (opcode))
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{
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if (opcode->tencode != do_t_blx && opcode->tencode != do_t_branch23
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&& !(ARM_CPU_HAS_FEATURE(*opcode->tvariant, arm_ext_msr)
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|| ARM_CPU_HAS_FEATURE(*opcode->tvariant, arm_ext_barrier)))
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if (inst.size_req == 0)
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inst.size_req = 2;
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else if (inst.size_req == 4)
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{
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/* Two things are addressed here.
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1) Implicit require narrow instructions on Thumb-1.
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This avoids relaxation accidentally introducing Thumb-2
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instructions.
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2) Reject wide instructions in non Thumb-2 cores. */
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if (inst.size_req == 0)
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inst.size_req = 2;
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else if (inst.size_req == 4)
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{
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as_bad (_("selected processor does not support `%s' in Thumb-2 mode"), str);
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return;
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}
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as_bad (_("selected processor does not support `%s' in Thumb-2 "
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"mode"), str);
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return;
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}
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}
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@ -17906,13 +17925,10 @@ md_assemble (char *str)
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ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
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*opcode->tvariant);
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/* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
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set those bits when Thumb-2 32-bit instructions are seen. ie.
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anything other than bl/blx and v6-M instructions.
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The impact of relaxable instructions will be considered later after we
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finish all relaxation. */
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if ((inst.size == 4 && (inst.instruction & 0xf800e800) != 0xf000e800)
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&& !(ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_msr)
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|| ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_barrier)))
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set those bits when Thumb-2 32-bit instructions are seen. The impact
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of relaxable instructions will be considered later after we finish all
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relaxation. */
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if (inst.size == 4 && !t1_isa_t32_only_insn (opcode))
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ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
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arm_ext_v6t2);
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@ -22880,7 +22896,7 @@ md_apply_fix (fixS * fixP,
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if ((value & ~0x3fffff) && ((value & ~0x3fffff) != ~0x3fffff))
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{
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if (!(ARM_CPU_HAS_FEATURE (cpu_variant, arm_arch_t2)))
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if (!(ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2)))
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as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
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else if ((value & ~0x1ffffff)
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&& ((value & ~0x1ffffff) != ~0x1ffffff))
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@ -1,3 +1,8 @@
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2015-12-24 Thomas Preud'homme <thomas.preudhomme@arm.com>
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* arm.h (ARM_ARCH_THUMB2): Add comment explaining its meaning and
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remove extension bit not including any Thumb-2 instruction.
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2015-12-15 Matthew Wahab <matthew.wahab@arm.com>
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* arm.h (ARM_ARCH_V8_1A): Add the CRC_EXT_ARMV8 co-processor
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@ -263,10 +263,10 @@
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#define ARM_ANY ARM_FEATURE (-1, -1, 0) /* Any basic core. */
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#define ARM_FEATURE_ALL ARM_FEATURE (-1, -1, -1)/* All CPU and FPU features. */
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#define FPU_ANY_HARD ARM_FEATURE_COPROC (FPU_FPA | FPU_VFP_HARD | FPU_MAVERICK)
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/* Extensions containing some Thumb-2 instructions. If any is present, Thumb
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ISA is Thumb-2. */
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#define ARM_ARCH_THUMB2 ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2 | ARM_EXT_V7 \
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| ARM_EXT_V7A | ARM_EXT_V7R \
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| ARM_EXT_V7M | ARM_EXT_DIV \
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| ARM_EXT_V8)
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| ARM_EXT_DIV | ARM_EXT_V8)
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/* v7-a+sec. */
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#define ARM_ARCH_V7A_SEC ARM_FEATURE_CORE_LOW (ARM_AEXT_V7A | ARM_EXT_SEC)
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/* v7-a+mp+sec. */
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