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Author SHA1 Message Date
Nick Clifton
77db8e2e96 * write.c (fixup_segment): Do not assume we know the section a 
defined weak symbol is in.
        * config/tc-arm.c (relax_adr, relax_branch, md_apply_fix): Treat
        weak symbols as not known to be in the same section, even if they
        are defined.

        * gas/arm/weakdef-1.s: New.
        * gas/arm/weakdef-1.d: New.
        * gas/arm/weakdef-2.s: New.
        * gas/arm/weakdef-2.d: New.
        * gas/arm/weakdef-2.l: New.
 2010-04-29 14:44:15 +00:00
Joseph Myers
d99e5b3995 gas: 
* config/tc-tic6x.h (tic6x_label_list): New.
	(tic6x_segment_info_type): Keep a list of labels and a current
	frag instead of a boolean for whether labels seen and a count of
	instructions.
	(tic6x_frag_info, TC_FRAG_TYPE, TC_FRAG_INIT, tic6x_frag_init,
	md_do_align, tic6x_do_align, md_end, tic6x_end): New.
	* config/tc-tic6x.c (tic6x_frob_label): Put label on list.
	(tic6x_cleanup): Correct comment.
	(tic6x_free_label_list): New.
	(tic6x_cons_align): Free label list and update for
	tic6x_segment_info_type changes.
	(tic6x_do_align): New.
	(md_assemble): Handle list of labels and saved frag for execute
	packet.  Create machine-dependent frag for new execute packet and
	adjust labels accordingly.
	(tic6x_adjust_section, tic6x_frag_init, tic6x_end): New.
	(md_convert_frag, md_estimate_size_before_relax): Update comments.

gas/testsuite:
	* gas/tic6x/align-1-be.d, gas/tic6x/align-1.d,
	gas/tic6x/align-1.s, gas/tic6x/align-2.d, gas/tic6x/align-2.s:
	New.
 2010-04-27 23:43:25 +00:00
H.J. Lu
253036079b Restore "call|jmp [xtrn]" in x86 assembler. 
gas/

2010-04-24  H.J. Lu  <hongjiu.lu@intel.com>

	PR gas/11535
	* config/tc-i386-intel.c (intel_state): Add is_indirect.
	(i386_intel_operand): Initialize intel_state.is_indirect.  Check
	intel_state.is_indirect for "call|jmp [symbol]".

gas/testsuite/

2010-04-24  H.J. Lu  <hongjiu.lu@intel.com>

	PR gas/11535
	* gas/i386/intelok.s: Add tests for "call|jmp [xtrn]".
	* gas/i386/intelok.d: Updated.
 2010-04-24 17:41:04 +00:00
H.J. Lu
0398aac575 Remove i386_is_register. 
2010-04-21  H.J. Lu  <hongjiu.lu@intel.com>

	* config/tc-i386.c (i386_is_register): Removed.
	(x86_cons): Don't use i386_is_register.
	(parse_register): Likewise.
	* config/tc-i386-intel.c (i386_intel_simplify): Likewise.
	(i386_intel_operand): Likewise.
 2010-04-22 03:10:48 +00:00
H.J. Lu
e96d56a1c8 Don't use i386_is_register in tc_x86_parse_to_dw2regnum. 
2010-04-21  H.J. Lu  <hongjiu.lu@intel.com>

	* config/tc-i386.c (tc_x86_parse_to_dw2regnum): Don't use
	i386_is_register.
 2010-04-22 01:01:34 +00:00
H.J. Lu
8d46fc7c2f Remove is_intel_syntax from i386_is_register. 
2010-04-21  H.J. Lu  <hongjiu.lu@intel.com>

	* config/tc-i386.c (i386_is_register): Remove is_intel_syntax.
	(x86_cons): Updated.
	(parse_register): Likewise.
	(tc_x86_parse_to_dw2regnum): Likewise.
	* config/tc-i386-intel.c (i386_intel_simplify): Likewise.
	(i386_intel_operand): Likewise.
 2010-04-22 00:43:38 +00:00
H.J. Lu
3c7b9c2c54 Properly handle ".equ symbol, reg + NUM" in x86 Intel syntax. 
gas/

2010-04-21  H.J. Lu  <hongjiu.lu@intel.com>

	PR gas/11509
	* config/tc-i386-intel.c (i386_intel_simplify_register): New.
	(i386_intel_simplify): Use i386_is_register and
	i386_intel_simplify_register. Set X_md for O_register and
	check X_md for O_constant.
	(i386_intel_operand): Use i386_is_register.

	* config/tc-i386.c (i386_is_register): New.
	(x86_cons): Initialize the X_md field.  Use i386_is_register.
	(parse_register): Use i386_is_register.
	(tc_x86_parse_to_dw2regnum): Likewise.

gas/testsuite/

2010-04-21  H.J. Lu  <hongjiu.lu@intel.com>

	PR gas/11509
	* gas/i386/equ.s: Add tests for ".equ symbol, reg + NUM".
	* gas/i386/equ.d: Updated.
 2010-04-21 18:09:52 +00:00
Joseph Myers
418205099b bfd: 
* elf32-tic6x.h: New.
	* elf-bfd.h (enum elf_target_id): Define TIC6X_ELF_DATA.
	* elf32-tic6x.c (struct elf32_tic6x_obj_tdata, elf32_tic6x_tdata,
	elf32_tic6x_howto_table_rel, elf32_tic6x_info_to_howto_rel,
	elf32_tic6x_set_use_rela_p, elf32_tic6x_mkobject,
	elf32_tic6x_new_section_hook, elf32_tic6x_rel_relocation_p,
	bfd_elf32_mkobject, bfd_elf32_new_section_hook): New.
	(elf32_tic6x_reloc_type_lookup, elf32_tic6x_reloc_name_lookup,
	elf32_tic6x_relocate_section): Handle REL relocations.
	(elf_info_to_howto_rel): Define to elf32_tic6x_info_to_howto_rel.

gas:
	* config/tc-tic6x.c (OPTION_MGENERATE_REL): New.
	(md_longopts): Add -mgenerate-rel.
	(tic6x_generate_rela): New.
	(md_parse_option): Handle -mgenerate-rel.
	(md_show_usage): Add comment that -mgenerate-rel is undocumented.
	(tic6x_init_after_args): New.
	(md_apply_fix): Correct shift calculations for SB-relative
	relocations.
	(md_pcrel_from): Change to tic6x_pcrel_from_section.  Do not
	adjust addresses for relocations referencing symbols in other
	sections.
	(tc_gen_reloc): Adjust addend calculations for REL relocations.
	* config/tc-tic6x.h (MD_PCREL_FROM_SECTION,
	tic6x_pcrel_from_section, tc_init_after_args,
	tic6x_init_after_args): New.

ld/testsuite:
	* ld-tic6x/data-reloc-global-rel.d,
	ld-tic6x/data-reloc-global-rel.s,
	ld-tic6x/data-reloc-local-r-rel.d,
	ld-tic6x/data-reloc-local-rel.d, ld-tic6x/mvk-reloc-global-rel.d,
	ld-tic6x/mvk-reloc-global-rel.s, ld-tic6x/mvk-reloc-local-1-rel.s,
	ld-tic6x/mvk-reloc-local-2-rel.s,
	ld-tic6x/mvk-reloc-local-r-rel.d, ld-tic6x/mvk-reloc-local-rel.d,
	ld-tic6x/pcrel-reloc-global-rel.d,
	ld-tic6x/pcrel-reloc-local-r-rel.d,
	ld-tic6x/pcrel-reloc-local-rel.d, ld-tic6x/sbr-reloc-global-rel.d,
	ld-tic6x/sbr-reloc-global-rel.s, ld-tic6x/sbr-reloc-local-1-rel.s,
	ld-tic6x/sbr-reloc-local-2-rel.s,
	ld-tic6x/sbr-reloc-local-r-rel.d, ld-tic6x/sbr-reloc-local-rel.d:
	New.
 2010-04-20 22:03:00 +00:00
Mike Frysinger
048e5b805b gas: bfin: replace index() with strchr() 2010-04-20 07:10:31 +00:00
Nick Clifton
bb7835b8e5 PR gas/11395 
* config/tc-hppa.c (pa_ip): Do not allow 64-bit add condition
        matcher to accept and unconditional 32-bit add instruction.
        (pa_build_unwind_subspace): Cope with error conditions not
        allowing the start symbol to be set.

        * gas/hppa/basic/add2.s: Add test of simple 32-bit instruction.
        * gas/hppa/basic/basic.exp (do_add2): Add grep for expected
        disassembly.
 2010-04-16 11:20:41 +00:00
Matthew Gretton-Dann
75375b3e00 * ld/testsuite/ld-arm/attr-merge-2.attr: Update for changes in attribute output. 
* ld/testsuite/ld-arm/attr-merge-3.attr: Likewise.
	* ld/testsuite/ld-arm/attr-merge-vfp-1.d: Likewise.
	* ld/testsuite/ld-arm/attr-merge-vfp-1r.d: Likewise.
	* ld/testsuite/ld-arm/attr-merge-vfp-2.d: Likewise.
	* ld/testsuite/ld-arm/attr-merge-vfp-2r.d: Likewise.
	* ld/testsuite/ld-arm/attr-merge-vfp-3.d: Likewise.
	* ld/testsuite/ld-arm/attr-merge-vfp-3r.d: Likewise.
	* ld/testsuite/ld-arm/attr-merge-vfp-4.d: Likeiwse.
	* ld/testsuite/ld-arm/attr-merge-vfp-4r.d: Likewise.
	* ld/testsuite/ld-arm/attr-merge-vfp-5.d: Likewise.
	* ld/testsuite/ld-arm/attr-merge-vfp-5r.d: Likewise.
	* ld/testsuite/ld-arm/attr-merge-wchar-00-nowarn.d: Likewise.
	* ld/testsuite/ld-arm/attr-merge-wchar-00.d: Likewise.
	* ld/testsuite/ld-arm/attr-merge-wchar-02-nowarn.d: Likewise.
	* ld/testsuite/ld-arm/attr-merge-wchar-02.d: Likewise.
	* ld/testsuite/ld-arm/attr-merge-wchar-04-nowarn.d: Likewise.
	* ld/testsuite/ld-arm/attr-merge-wchar-04.d: Likewise.
	* ld/testsuite/ld-arm/attr-merge-wchar-20-nowarn.d: Likewise.
	* ld/testsuite/ld-arm/attr-merge-wchar-20.d: Likewise.
	* ld/testsuite/ld-arm/attr-merge-wchar-22-nowarn.d: Likewise.
	* ld/testsuite/ld-arm/attr-merge-wchar-22.d: Likewise.
	* ld/testsuite/ld-arm/attr-merge-wchar-24-nowarn.d: Likewise.
	* ld/testsuite/ld-arm/attr-merge-wchar-40-nowarn.d: Likewise.
	* ld/testsuite/ld-arm/attr-merge-wchar-40.d: Likewise.
	* ld/testsuite/ld-arm/attr-merge-wchar-42-nowarn.d: Likewise.
	* ld/testsuite/ld-arm/attr-merge-wchar-44-nowarn.d: Likewise.
	* ld/testsuite/ld-arm/attr-merge-wchar-44.d: Likewise.
	* ld/testsuite/ld-arm/attr-merge.attr: Likewise.
	* binutils/readelf.c (arm_attr_tag_FP_arch): Rename from arm_attr_tag_VFP_arch.
	(arm_attr_tag_ABI_align8_needed): Remove.
	(arm_attr_tag_ABI_align8_preserved): Remove.
	(arm_attr_tag_ABI_HardFP_use): Update text strings.
	(arm_attr_public_tags): Add strings for ABI v2.08 attribute tags.
	(display_arm_attribute): Add decoding of ABI v2.08 attributes.
	* include/elf/arm.h (Tag_FP_arch, Tag_ABI_align_needed, Tag_ABI_align_preserved,
	Tag_FP_HP_extension): Add new ABI attribute tags.
	* gas/config/tc-arm.c (arm_convert_symbolic_attribute): Add support for
	new tag names in v2.08 of ARM ABI.
	* gas/doc/c-arm.texi: Document new tag names in ABI.
	* gas/testsuite/gas/arm/attr-mcpu.d: Update for new attribute tag names.
	* gas/testsuite/gas/arm/attr-mfpu-arm1020e.d: Likewise.
	* gas/testsuite/gas/arm/attr-mfpu-arm1020t.d: Likewise.
	* gas/testsuite/gas/arm/attr-mfpu-arm1136jf-s.d: Likewise.
	* gas/testsuite/gas/arm/attr-mfpu-arm1136jfs.d: Likewise.
	* gas/testsuite/gas/arm/attr-mfpu-neon-fp16.d: Likewise.
	* gas/testsuite/gas/arm/attr-mfpu-neon.d: Likewise.
	* gas/testsuite/gas/arm/attr-mfpu-softvfp+vfp.d: Likewise.
	* gas/testsuite/gas/arm/attr-mfpu-vfp.d: Likewise.
	* gas/testsuite/gas/arm/attr-mfpu-vfp10-r0.d: Likewise.
	* gas/testsuite/gas/arm/attr-mfpu-vfp10.d: Likewise.
	* gas/testsuite/gas/arm/attr-mfpu-vfp3.d: Likewise.
	* gas/testsuite/gas/arm/attr-mfpu-vfp9.d: Likewise.
	* gas/testsuite/gas/arm/attr-mfpu-vfpv2.d: Likewise.
	* gas/testsuite/gas/arm/attr-mfpu-vfpv3-d16.d: Likewise.
	* gas/testsuite/gas/arm/attr-mfpu-vfpv3.d: Likewise.
	* gas/testsuite/gas/arm/attr-mfpu-vfpv4-d16.d: Likewise.
	* gas/testsuite/gas/arm/attr-mfpu-vfpv4.d: Likewise.
	* gas/testsuite/gas/arm/attr-mfpu-vfpxd.d: Likewise.
	* gas/testsuite/gas/arm/attr-names.d: Add test to make sure all attribute names
	are recognised.
	* gas/testsuite/gas/arm/attr-names.s: Likewise.
 2010-04-15 10:56:39 +00:00
Tristan Gingold
d8703844ce 2010-04-14 Tristan Gingold <gingold@adacore.com> 
* config/tc-alpha.c: Includes vms/egps.h on EVAX.
	(s_alpha_comm): Used new EGPS macros from egps.h
	(RGPS__V_NO_SHIFT, EGPS__V_MASK): New local macros.
	(s_alpha_section_word): Add comments.  Use new EGPS macros.
	Adjust for modified bfd_vms_set_section_flags function.
 2010-04-14 09:25:34 +00:00
Alan Modra
aa0c8c1ae1 PR gas/11486 
* config/tc-ppc.c (ppc_elf_cons): Clear frag contents.
 2010-04-10 14:12:56 +00:00
Eric B. Weddington
e760a81b79 2010-04-07 Eric B. Weddington <eric.weddington@atmel.com> 
* config/tc-avr.c (mcu_types): Add support for atmega16a, atmega168a,
	atmega164a, atmega165a, atmega169a, atmega169pa, atmega16hva2,
	atmega324a, atmega324pa, atmega325a, atmega3250a, atmega328,
	atmega329a, atmega329pa, atmega3290a, atmega48a, atmega644a,
	atmega645a, atmega645p, atmega6450a, atmega6450p, atmega649a,
	atmega649p, atmega6490a, atmega6490p, atmega64hve, atmega88a,
	atmega88pa, attiny461a, attiny84a, m3000.
	Remove support for atmega8m1, atmega8c1, atmega16c1, atmega4hvd,
	atmega8hvd, attiny327, m3000f, m3000s, m3001b.
	* doc/c-avr.texi: Same.
 2010-04-09 03:48:54 +00:00
Jie Zhang
2de7820f27 * config/tc-arm.c (make_mapping_symbol): Handle the case 
that multiple mapping symbols have the same value 0.

	testsuite/
	* gas/arm/mapmisc.s: Test multiple mapping symbols have
	the same value 0.
 2010-04-07 10:39:06 +00:00
Joseph Myers
40b365969f bfd: 
* Makefile.am (ALL_MACHINES): Add cpu-tic6x.lo.
	(ALL_MACHINES_CFILES): Add cpu-tic6x.c.
	(BFD32_BACKENDS): Add elf32-tic6x.lo.
	(BFD32_BACKENDS_CFILES): Add elf32-tic6x.c.
	* Makefile.in: Regenerate.
	* archures.c (bfd_arch_tic6x, bfd_tic6x_arch): New.
	(bfd_archures_list): Update.
	* config.bfd (tic6x-*-elf): New.
	* configure.in (bfd_elf32_tic6x_be_vec, bfd_elf32_tic6x_le_vec):
	New.
	* configure: Regenerate.
	* cpu-tic6x.c, elf32-tic6x.c: New.
	* reloc.c (BFD_RELOC_C6000_PCR_S21, BFD_RELOC_C6000_PCR_S12,
	BFD_RELOC_C6000_PCR_S10, BFD_RELOC_C6000_PCR_S7,
	BFD_RELOC_C6000_ABS_S16, BFD_RELOC_C6000_ABS_L16,
	BFD_RELOC_C6000_ABS_H16, BFD_RELOC_C6000_SBR_U15_B,
	BFD_RELOC_C6000_SBR_U15_H, BFD_RELOC_C6000_SBR_U15_W,
	BFD_RELOC_C6000_SBR_S16, BFD_RELOC_C6000_SBR_L16_B,
	BFD_RELOC_C6000_SBR_L16_H, BFD_RELOC_C6000_SBR_L16_W,
	BFD_RELOC_C6000_SBR_H16_B, BFD_RELOC_C6000_SBR_H16_H,
	BFD_RELOC_C6000_SBR_H16_W, BFD_RELOC_C6000_SBR_GOT_U15_W,
	BFD_RELOC_C6000_SBR_GOT_L16_W, BFD_RELOC_C6000_SBR_GOT_H16_W,
	BFD_RELOC_C6000_DSBT_INDEX, BFD_RELOC_C6000_PREL31,
	BFD_RELOC_C6000_COPY, BFD_RELOC_C6000_ALIGN,
	BFD_RELOC_C6000_FPHEAD, BFD_RELOC_C6000_NOCMP): New.
	* targets.c (bfd_elf32_tic6x_be_vec, bfd_elf32_tic6x_le_vec): New.
	(_bfd_target_vector): Update.
	* bfd-in2.h, libbfd.h: Regenerate.

binutils:
	* MAINTAINERS: Add self as TI C6X maintainer.
	* NEWS: Add news entry for TI C6X support.
	* readelf.c: Include elf/tic6x.h.
	(guess_is_rela): Handle EM_TI_C6000.
	(dump_relocations): Likewise.
	(get_tic6x_dynamic_type): New.
	(get_dynamic_type): Call it.
	(get_machine_flags): Handle EF_C6000_REL.
	(get_osabi_name): Handle machine-specific values only for relevant
	machines.  Handle C6X values.
	(get_tic6x_segment_type): New.
	(get_segment_type): Call it.
	(get_tic6x_section_type_name): New.
	(get_section_type_name): Call it.
	(is_32bit_abs_reloc, is_16bit_abs_reloc, is_none_reloc): Handle
	EM_TI_C6000.

gas:
	* Makefile.am (TARGET_CPU_CFILES): Add config/tc-tic6x.c.
	(TARGET_CPU_HFILES): Add config/tc-tic6x.h.
	* Makefile.in: Regenerate.
	* NEWS: Add news entry for TI C6X support.
	* app.c (do_scrub_chars): Handle "||^" for TI C6X.  Handle
	TC_PREDICATE_START_CHAR and TC_PREDICATE_END_CHAR.  Keep spaces in
	operands if TC_KEEP_OPERAND_SPACES.
	* configure.tgt (tic6x-*-*): New.
	* config/tc-ia64.h (TC_PREDICATE_START_CHAR,
	TC_PREDICATE_END_CHAR): Define.
	* config/tc-tic6x.c, config/tc-tic6x.h: New.
	* doc/Makefile.am (CPU_DOCS): Add c-tic6x.texi.
	* doc/Makefile.in: Regenerate.
	* doc/all.texi (TIC6X): Define.
	* doc/as.texinfo: Add TI C6X documentation.  Include c-tic6x.texi.
	* doc/c-tic6x.texi: New.

gas/testsuite:
	* gas/tic6x: New directory and testcases.

include:
	* dis-asm.h (print_insn_tic6x): Declare.

include/elf:
	* common.h (ELFOSABI_C6000_ELFABI, ELFOSABI_C6000_LINUX): Define.
	* tic6x.h: New.

include/opcode:
	* tic6x-control-registers.h, tic6x-insn-formats.h,
	tic6x-opcode-table.h, tic6x.h: New.

ld:
	* Makefile.am (ALL_EMULATIONS): Add eelf32_tic6x_be.o and
	eelf32_tic6x_le.o.
	(eelf32_tic6x_be.c, eelf32_tic6x_le.c): New.
	* NEWS: Add news entry for TI C6X support.
	* configure.tgt (tic6x-*-*): New.
	* emulparams/elf32_tic6x_be.sh, emulparams/elf32_tic6x_le.sh: New.

ld/testsuite:
	* ld-elf/flags1.d, ld-elf/merge.d: XFAIL for tic6x-*-*.
	* ld-elf/sec-to-seg.exp: Set B_test_same_seg to 0 for tic6x-*-*.
	* ld-tic6x: New directory and testcases.

opcodes:
	* Makefile.am (TARGET_LIBOPCODES_CFILES): Add tic6x-dis.c.
	* Makefile.in: Regenerate.
	* configure.in (bfd_tic6x_arch): New.
	* configure: Regenerate.
	* disassemble.c (ARCH_tic6x): Define if ARCH_all.
	(disassembler): Handle TI C6X.
	* tic6x-dis.c: New.
 2010-03-25 21:12:36 +00:00
H.J. Lu
cff8d58ab4 Use STRING_COMMA_LEN to avoid strlen. 
2010-03-22  H.J. Lu  <hongjiu.lu@intel.com>

	* config/tc-i386.c (lex_got): Use STRING_COMMA_LEN on gotrel.
 2010-03-22 13:49:50 +00:00
H.J. Lu
86e026a449 Replace oprand_size_mismatch with operand_size_mismatch. 
2010-03-21  H.J. Lu  <hongjiu.lu@intel.com>

	* config/tc-i386.c (i386_error): Replace oprand_size_mismatch
	with operand_size_mismatch.
	(operand_size_match): Updated.
	(match_template): Likewise.
 2010-03-22 03:29:47 +00:00
H.J. Lu
a65babc949 Set error instead of err_msg on failure. 
2010-03-21  H.J. Lu  <hongjiu.lu@intel.com>

	* config/tc-i386.c (i386_error): New.
	(_i386_insn): Replace err_msg with error.
	(operand_size_match): Set error instead of err_msg on failure.
	(operand_type_match): Likewise.
	(operand_type_register_match): Likewise.
	(VEX_check_operands): Likewise.
	(match_template): Likewise.  Use error instead of err_msg with
	as_bad.
 2010-03-22 02:20:58 +00:00
Jie Zhang
0f020cefaa * config/tc-arm.c (make_mapping_symbol): Hanle the case 
that two mapping symbols have the same value.

	testsuite/
	* gas/arm/mapmisc.s: Add the test case for two mapping
	symbols having the same value.
	* gas/arm/mapmisc.d: Likewise.
 2010-03-19 14:43:09 +00:00
Nick Clifton
b43420e6cd bfd/ 
2010-03-15  Wei Guozhi  <carrot@google.com>

       PR gas/11323
       * bfd-in2.h (enum bfd_reloc_code_real): New BFD_RELOC_GOT_PREL type.
       * elf32-arm.c (elf32_arm_reloc_map): BFD_RELOC_GOT_PREL to
       R_ARM_GOT_PREL map.
       * libbfd.h (bfd_reloc_code_real_names): BFD_RELOC_GOT_PREL name.
       * reloc.c (comments): Document the new relocation.

gas/
2010-03-15  Wei Guozhi  <carrot@google.com>

       PR gas/11323
       * config/tc-arm.c (reloc_names): New relocation names.
       (md_apply_fix): New case for BFD_RELOC_ARM_GOT_PREL.
       (tc_gen_reloc): New case for BFD_RELOC_ARM_GOT_PREL.
       * doc/c-arm.texi (ARM-Relocations): Document the new relocation.

gas/testsuite
2010-03-15  Wei Guozhi  <carrot@google.com>

       PR gas/11323
       * gas/arm/got_prel.s: New test case.
       * gas/arm/got_prel.d: Likewise.
 2010-03-18 11:22:46 +00:00
Segher Boessenkool
dc86b458e9 2010-03-13 Segher Boessenkool <segher@kernel.crashing.org> 
* config/tc-v850.c (v850_insert_operand): Handle out-of-range
        assembler constants on 64-bit hosts.
 2010-03-13 15:54:21 +00:00
Mike Frysinger
ee9e7c780e strip trailing whitespace in Blackfin files 2010-03-10 14:23:58 +00:00
Mike Frysinger
a23c851aa4 add support for Blackfin bf504/bf506 2010-03-10 13:03:29 +00:00
Jie Zhang
9982501a0d * doc/as.texinfo: Add Blackfin options. 
* doc/c-bfin.texi: Document -mfdpic, -mno-fdpic and -mnopic.
	* config/tc-bfin.c (md_show_usage): Show usage for all
	Blackfin specific options.
 2010-03-10 03:57:00 +00:00
Rainer Orth
40cf28aa1c * config/tc-i386.h [TE_SOLARIS] (ELF_TARGET_FORMAT): Define. 
(ELF_TARGET_FORMAT64): Define.
 2010-03-08 14:07:45 +00:00
Paul Brook
26b6f1917c 2010-03-05 Paul Brook <paul@codesourcery.com> 
gas/
	* config/tc-arm.c (arm_cpu_option_table): Add cortex-m4.
 2010-03-05 10:41:04 +00:00
Andrew Stubbs
772657e995 2010-03-02 Andrew Stubbs <ams@codesourcery.com> 
* config/tc-sh.c (get_specific): Move overflow checking code to avoid
	reading uninitialized data.
 2010-03-02 09:32:21 +00:00
Tristan Gingold
bd56defd73 2010-03-01 Tristan Gingold <gingold@adacore.com> 
* config/tc-score7.c (s7_frag_check): Add ATTRIBUTE_UNUSED.
 2010-03-01 16:47:52 +00:00
Jie Zhang
f8a8e9d60e * config/tc-arm.c (do_t_strexd): Remove 
operand[1] != operand[2] contraint.

	testsuite/
	* gas/arm/thumb32.s, gas/arm/thumb32.d: Add a new test
	for strexd.
	* gas/arm/thumb32.l: Adjust.
 2010-02-26 15:57:59 +00:00
Jie Zhang
3fde54a228 * config/tc-arm.c (neon_select_shape): No need to match 
the remaining operands in the shape when one operand does
	not match.
 2010-02-26 15:52:41 +00:00
Jie Zhang
e23c0ad820 2010-02-26 Jie Zhang <jie@codesourcery.com> 
* config/tc-arm.c (do_neon_ld_st_interleave): Reject bad
	alignment.

	testsuite/
	* gas/arm/neon-ldst-align-bad.d: New test.
	* gas/arm/neon-ldst-align-bad.l: New test.
	* gas/arm/neon-ldst-align-bad.s: New test.
 2010-02-26 15:49:07 +00:00
H.J. Lu
a6c560506b Update x86 assembler error messages. 
2010-02-25  H.J. Lu  <hongjiu.lu@intel.com>

	* config/tc-i386.c (match_template): Update error messages.
 2010-02-25 21:47:27 +00:00
H.J. Lu
891edac42b Improve x86 assembler error message. 
2010-02-25  H.J. Lu  <hongjiu.lu@intel.com>

	* config/tc-i386.c (_i386_insn): Add err_msg.
	(operand_size_match): Set err_msg on failure.
	(operand_type_match): Likewise.
	(operand_type_register_match): Likewise.
	(VEX_check_operands): Likewise.
	(match_template): Likewise.  Use i.err_msg with as_bad.
 2010-02-25 17:59:52 +00:00
Nick Clifton
c67a084a24 * config/tc-mips.c (mips_fix_loongson2f, mips_fix_loongson2f_nop, 
mips_fix_loongson2f_jump): New variables.
        (md_longopts): Add New options -mfix-loongson2f-nop/jump,
        -mno-fix-loongson2f-nop/jump.
        (md_parse_option): Initialize variables via above options.
        (options): New enums for the above options.
        (md_begin): Initialize nop_insn from LOONGSON2F_NOP_INSN.
        (fix_loongson2f, fix_loongson2f_nop, fix_loongson2f_jump):
        New functions.
        (append_insn): call fix_loongson2f().
        (mips_handle_align): Replace the implicit nops.
        * config/tc-mips.h (MAX_MEM_FOR_RS_ALIGN_CODE): Modified
        for the new mips_handle_align().
        * doc/c-mips.texi: Document the new options.

        * gas/mips/loongson-2f-2.s: New test of -mfix-loongson2f-nop.
        * gas/mips/loongson-2f-2.d: Likewise.
        * gas/mips/loongson-2f-3.s: New test of -mfix-loongson2f-jump.
        * gas/mips/loongson-2f-3.d: Likewise.
        * gas/mips/mips.exp: Run the new tests.

        * opcode/mips.h (LOONGSON2F_NOP_INSN): New macro.
 2010-02-25 11:15:48 +00:00
Daniel Gutson
56adecf405 gas/ 
* config/tc-arm.c (do_rd_rm_rn): Added warning.

    gas/testsuite/
    * gas/arm/depr-swp.d: New test case.
    * gas/arm/depr-swp.s: New file.
    * gas/arm/depr-swp.l: New file.
 2010-02-23 18:04:14 +00:00
Nick Clifton
17e5723725 PR 11297: Add support for 8-bit relocations to the AVR toolchain. 2010-02-23 11:38:36 +00:00
Matthew Gretton-Dann
8a59fff3dd PR 9861 
* gas/config/tc-arm.c (CPU_DEFAULT): Do not define based upon build
	compiler's predefines.
 2010-02-22 10:24:56 +00:00
Matthew Gretton-Dann
cd21e5460f * bfd/elf32-arm.c (elf32_arm_merge_eabi_attributes): Add support for 
merging Tag_DIV_use, Tag_MPextension_use, and
	Tag_MPextension_use_legacy tags.
	* binutils/readelf.c (arm_attr_tag_Advanced_SIMD_arch): Add
	description of newly permitted attribute values.
	(arm_attr_tag_Virtualization_use): Likewise.
	(arm_attr_tag_DIV_use): Add description of new attribute.
	(arm_attr_tag_MPextension_use_legacy): Likewise.
	* gas/config/tc-arm.c (arm_convert_symbolic_attribute):
	Add Tag_DIV_use.
	* gas/doc/c-arm.texi: Likewise.
	* gas/testsuite/gas/arm/attr-order.d: Fix test for new names for
	attribute values.
	* include/elf/arm.h (Tag_MPextension_use): Renumber.
	(Tag_DIV_use): Add.
	(Tag_MPextension_use_legacy): Likewise.
	* ld/testsuite/ld-arm/attr-merge-3.attr: Fix test for new attribute
	values.
	* ld/testsuite/ld-arm/attr-merge-3b.s: Likewise.
	* ld/testsuite/ld-arm/attr-merge-unknown-1.d: Fix test now that 42
	is a recognised attribute ID.
	* ld/testsuite/ld-arm/attr-merge-unknown-1.s: Likewise.
	* ld/testsuite/ld-arm/attr-merge-6.attr: New test.
	* ld/testsuite/ld-arm/attr-merge-6a.s: Likewise.
	* ld/testsuite/ld-arm/attr-merge-6b.s: Likewise.
	* ld/testsuite/ld-arm/attr-merge-7.attr: Likewise.
	* ld/testsuite/ld-arm/attr-merge-7a.s: Likewise.
	* ld/testsuite/ld-arm/attr-merge-7b.s: Likewise.
	* ld/testsuite/ld-arm/arm-elf.exp: Run the new tests.
 2010-02-18 10:56:28 +00:00
Daniel Gutson
5be8be5d5d gas/ 
* config/tc-arm.c (asm_opcode): operands type
	change.
	(BAD_PC_ADDRESSING): New macro message.
	(BAD_PC_WRITEBACK): Likewise.
	(MIX_ARM_THUMB_OPERANDS): New macro.
	(operand_parse_code): Added enum values.
	(parse_operands): Added thumb/arm distinction,
	plus new enum values handling.
	(encode_arm_addr_mode_2): Validations enhanced.
	(encode_arm_addr_mode_3): Likewise.
	(do_rm_rd_rn): Likewise.
	(encode_thumb32_addr_mode): Likewise.
	(do_t_ldrex): Likewise.
	(do_t_ldst): Likewise.
	(do_t_strex): Likewise.
	(md_assemble): Call parse_operands with
	a new parameter.
	(OPS_1): New macro.
	(OPS_2): Likewise.
	(OPS_3): Likewise.
	(OPS_4): Likewise.
	(OPS_5): Likewise.
	(OPS_6): Likewise.
	(insns): Updated insns operands.

	gas/testsuite/
	* gas/arm/sp-pc-validations-bad.d: New testcase.
	* gas/arm/sp-pc-validations-bad.l: New file.
	* gas/arm/sp-pc-validations-bad.s: New file.
	* gas/arm/sp-pc-validations-bad-t.d: New testcase.
	* gas/arm/sp-pc-validations-bad-t.l: New file.
	* gas/arm/sp-pc-validations-bad-t.s: New file.
	* gas/arm/sp-pc-usage-t.d: Removed invalid insns.
	* gas/arm/sp-pc-usage-t.s: Likewise.
	* gas/arm/unpredictable.d: Likewise.
	* gas/arm/unpredictable.s: Likewise.
	* gas/arm/thumb2_bcond.d: Added test.
	* gas/arm/thumb2_bcond.s: Likewise.
 2010-02-12 20:15:13 +00:00
Tristan Gingold
9d0e849713 gas/ 
2010-02-12  Tristan Gingold  <gingold@adacore.com>
	    Douglas B Rupp  <rupp@gnat.com>

	* config/tc-ia64.c (enum reloc_func): Add FUNC_SLOTCOUNT_RELOC.
	(DUMMY_RELOC_IA64_SLOTCOUNT): Added.
	(pseudo_func): Add an entry for slotcount.
	(md_begin): Initialize slotcount pseudo symbol.
	(ia64_parse_name): Handle @slotcount parameter.
	(ia64_gen_real_reloc_type): Handle slotcount.
	(md_apply_fix): Ditto.
	* doc/c-ia64.texi (IA-64-Relocs): Document @slotcount.

gas/testsuite/
2010-02-12  Tristan Gingold  <gingold@adacore.com>

	* gas/ia64/slotcount.s, gas/ia64/slotcount.s: New test.
	* gas/ia64/ia64.exp: Add slotcount test (vms only).
 2010-02-12 14:34:45 +00:00
Sterling Augustine
6fa78d941b 2010-02-11 Sterling Augustine <sterling@jaw.hq.tensilica.com> 
* config/tc-xtensa.c (istack_init): Don't call memset.
 2010-02-11 19:08:09 +00:00
Sterling Augustine
a89c407e4b 2010-02-11 Sterling Augustine <sterling@tensilica.com> 
* config/tc-xtensa.c (cache_literal_section): Handle prefixes as
	well as suffixes.
 2010-02-11 19:00:21 +00:00
H.J. Lu
24981e7b95 Reformat build_modrm_byte. 
2010-02-11  H.J. Lu  <hongjiu.lu@intel.com>

	* config/tc-i386.c (build_modrm_byte): Reformat.
 2010-02-11 14:02:50 +00:00
H.J. Lu
c75ef631bd Update copyright. 
gas/

2010-02-11  H.J. Lu  <hongjiu.lu@intel.com>

	* config/tc-i386.c: Update copyright.

opcodes/

2010-02-11  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis.c: Update copyright.
	* i386-gen.c: Likewise.
	* i386-opc.h: Likewise.
	* i386-opc.tbl: Likewise.
 2010-02-11 13:41:19 +00:00
Sebastian Pop
a683cc34e4 2010-02-10 Quentin Neill <quentin.neill@amd.com> 
Sebastian Pop  <sebastian.pop@amd.com>

gas:
        * config/tc-i386.c (vec_imm4) New operand type.
        (fits_in_imm4): New.
        (VEX_check_operands): New.
        (check_reverse): Call VEX_check_operands.
        (build_modrm_byte): Reintroduce code for 5
        operand insns.  Fix whitespace.

gas/testsuite:
        * gas/i386/x86-64-xop.d: Add vpermil2p[sd] tests.
        * gas/i386/x86-64-xop.s: Likewise.
        * gas/i386/xop.d: Likewise.
        * gas/i386/xop.s: Likewise.

opcodes:
        * i386-dis.c (OP_EX_VexImmW): Reintroduced
        function to handle 5th imm8 operand.
        (PREFIX_VEX_3A48): Added.
        (PREFIX_VEX_3A49): Added.
        (VEX_W_3A48_P_2): Added.
        (VEX_W_3A49_P_2): Added.
        (prefix table): Added entries for PREFIX_VEX_3A48
        and PREFIX_VEX_3A49.
        (vex table): Added entries for VEX_W_3A48_P_2 and
        and VEX_W_3A49_P_2.
        * i386-gen.c (operand_type_init): Added OPERAND_TYPE_VEC_IMM4
        for Vec_Imm4 operands.
        * i386-opc.h (enum): Added Vec_Imm4.
        (i386_operand_type): Added vec_imm4.
        * i386-opc.tbl: Add entries for vpermilp[ds].
        * i386-init.h: Regenerated.
        * i386-tbl.h: Regenerated.
 2010-02-11 05:06:14 +00:00
Sterling Augustine
3c83b96e24 2010-02-10 Sterling Augustine <sterling@tensilica.com> 
* config/tc-xtensa.c (xtensa_find_unaligned_loops): Rewrite.
 2010-02-10 20:18:14 +00:00
Richard Sandiford
cdc51b0748 gas/ 
* config/tc-ppc.c (md_show_usage): Add -mpwr4, -mpwr5, -mpwr5x,
	-mpwr6 and -mpwr7.

opcodes/
	* ppc-dis.c (ppc_opts): Add "pwr4", "pwr5", "pwr5x", "pwr6"
	and "pwr7".  Move "a2" into alphabetical order.
 2010-02-10 19:59:07 +00:00
Sterling Augustine
3a1e9c4a2d 2010-02-09 Sterling Augustine <sterling@tensilica.com> 
* config/tc-xtensa.c (RELAXED_LOOP_INSN_BYTES): New.
	(next_frag_pre_opcode_bytes): Use RELAXED_LOOP_INSN_BYTES.
	(xtensa_mark_zcl_first_insns): Rewrite to handle corner case.
 2010-02-09 19:36:50 +00:00
Christophe Lyon
486499d044 2010-02-08 Christophe Lyon <christophe.lyon@st.com> 
gas/
	* config/tc-arm.c (md_pcrel_from_section): Keep base to zero for
	non-local branches (BFD_RELOC_THUMB_PCREL_BRANCH23,
	BFD_RELOC_THUMB_PCREL_BLX, BFD_RELOC_ARM_PCREL_BLX,
	BFD_RELOC_ARM_PCREL_CALL)

	gas/testsuite/
	* gas/arm/branch-reloc.s, gas/arm/branch-reloc.d,
	gas/arm/branch-reloc.l: New tests and expected results with all
	variants of call: ARM/Thumb, local/global, inter/intra-section,
	using BL/BLX.
 2010-02-09 14:44:50 +00:00
Sterling Augustine
19ef5f3d6d 2010-02-08 Sterling Augustine <sterling@tensilica.com> 
* config/tc-xtensa.c (frag_format_size): Generalize logic to
	handle more instruction	sizes and fetch widths.
	(branch_align_power): Likewise.
	(text_align_power): Likewise.
	(bytes_to_stretch): Likewise.
 2010-02-08 18:45:05 +00:00
Alan Modra
ce3d2015b2 include/ 
* opcode/ppc.h (PPC_OPCODE_TITAN): Define.
bfd/
	* archures.c (bfd_mach_ppc_titan): Define.
	* bfd-in2.h: Regenerate.
	* cpu-powerpc.c (bfd_powerpc_archs): Add titan entry.
opcodes/
	* ppc-dis.c (ppc_opts): Add titan entry.
	* ppc-opc.c (TITAN, MULHW): Define.
	(powerpc_opcodes): Support AppliedMicro Titan core (APM83xxx).
gas/
	* config/tc-ppc.c (md_show_usage): Mention -mtitan.  Don't use tabs.
	(ppc_mach): Handle titan.
	* doc/c-ppc.texi: Mention -mtitan.
gas/testsuite/
	* gas/ppc/titan.d, * gas/ppc/titan.s: New test.
	* gas/ppc/ppc.exp: Run it.
 2010-02-08 01:59:38 +00:00
Sterling Augustine
1beeb6866d 10-02-05 Sterling Augustine <sterling@tensilica.com> 
* config/tc-xtensa.c (UNREACHABLE_MAX_WIDTH): Delete and
	replace with...
	(xtensa_fetch_width) ...this.
 2010-02-05 18:52:27 +00:00
Sebastian Pop
68339fdf88 2010-02-03 Quentin Neill <quentin.neill@amd.com> 
gas/
	* config/tc-i386.c (cpu_arch): Change amdfam15 to bdver1.
	(i386_align_code): Rename  PROCESSOR_AMDFAM15 to PROCESSOR_BDVER1.
	* config/tc-i386.h (processor_type): Same.
	* doc/c-i386.texi: Change amdfam15 to bdver1.

opcodes/
	* i386-gen.c (cpu_flag_init): Rename CPU_AMDFAM15_FLAGS
	to CPU_BDVER1_FLAGS
	* i386-init.h: Regenerated.

testsuite/
	* gas/i386/i386.exp: Rename amdfam15 test cases to bdver1.
	* gas/i386/x86-64-nops-1-amdfam15.d: Renamed test case to
	gas/i386/x86-64-nops-1-bdver1.d.
	* gas/i386/nops-1-amdfam15.d: Renamed test case to
	gas/i386/nops-1-bdver1.d.
 2010-02-03 20:36:14 +00:00
Nick Clifton
99b253c514 PR 11136 
* config/tc-arm.c (neon_check_type): Handle a neon_shape value of
        NS_NULL.
        * gas/arm/neon-omit.s: Add instruction that causes crash.
        * gas/arm/neon-omit.d: Add expected disassembly.
 2010-01-29 16:02:41 +00:00
Dave Korn
31907d5e90 gas/ChangeLog: 
* NEWS: Mention new feature.
	* config/obj-coff.c (obj_coff_section): Accept digits and use
	to override default section alignment power if specified.
	* doc/as.texinfo (.section directive): Update documentation.

gas/testsuite/ChangeLog:

	* gas/pe/section-align-1.s: New test source file.
	* gas/pe/section-align-1.d: Likewise control script.
	* gas/pe/section-align-2.s: Likewise ...
	* gas/pe/section-align-2.d: ... and likewise.
	* gas/pe/pe.exp: Invoke new testcases.
 2010-01-27 22:01:38 +00:00
H.J. Lu
539f890d01 Allow VL=1 on AVX scalar instructions. 
gas/

2010-01-27  H.J. Lu  <hongjiu.lu@intel.com>

	* config/tc-i386.c (avxscalar): New.
	(OPTION_MAVXSCALAR): Likewise.
	(build_vex_prefix): Select vector_length for scalar instructions
	based on avxscalar.
	(md_longopts): Add OPTION_MAVXSCALAR.
	(md_parse_option): Handle OPTION_MAVXSCALAR.
	(md_show_usage): Add -mavxscalar=.

	* doc/c-i386.texi: Document -mavxscalar=.

gas/testsuite/

2010-01-27  H.J. Lu  <hongjiu.lu@intel.com>

	* gas/i386/avx-scalar-intel.d: New.
	* gas/i386/avx-scalar.d: Likewise.
	* gas/i386/avx-scalar.s: Likewise.
	* gas/i386/x86-64-avx-scalar-intel.d: Likewise.
	* gas/i386/x86-64-avx-scalar.d: Likewise.
	* gas/i386/x86-64-avx-scalar.s: Likewise.

	* gas/i386/i386.exp: Run avx-scalar, avx-scalar-intel,
	x86-64-avx-scalar and x86-64-avx-scalar-intel.

opcodes/

2010-01-27  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis.c (XMScalar): New.
	(EXdScalar): Likewise.
	(EXqScalar): Likewise.
	(EXqScalarS): Likewise.
	(VexScalar): Likewise.
	(EXdVexScalarS): Likewise.
	(EXqVexScalarS): Likewise.
	(XMVexScalar): Likewise.
	(scalar_mode): Likewise.
	(d_scalar_mode): Likewise.
	(d_scalar_swap_mode): Likewise.
	(q_scalar_mode): Likewise.
	(q_scalar_swap_mode): Likewise.
	(vex_scalar_mode): Likewise.
	(vex_len_table): Duplcate entries for VEX_LEN_10_P_1,
	VEX_LEN_10_P_3, VEX_LEN_11_P_1, VEX_LEN_11_P_3, VEX_LEN_2A_P_1,
	VEX_LEN_2A_P_3, VEX_LEN_2C_P_3, VEX_LEN_2D_P_1, VEX_LEN_2E_P_0,
	VEX_LEN_2E_P_2, VEX_LEN_2F_P_2, VEX_LEN_51_P_1, VEX_LEN_51_P_3,
	VEX_LEN_52_P_1, VEX_LEN_53_P_1, VEX_LEN_58_P_1, VEX_LEN_58_P_3,
	VEX_LEN_59_P_1, VEX_LEN_5A_P_1, VEX_LEN_5A_P_3, VEX_LEN_5C_P_1,
	VEX_LEN_5C_P_3, VEX_LEN_5D_P_1, VEX_LEN_5D_P_3, VEX_LEN_5E_P_1,
	VEX_LEN_5E_P_3, VEX_LEN_5F_P_1, VEX_LEN_5F_P_3, VEX_LEN_6E_P_2,
	VEX_LEN_7E_P_1, VEX_LEN_7E_P_2, VEX_LEN_D6_P_2, VEX_LEN_C2_P_1,
	VEX_LEN_C2_P_3, VEX_LEN_3A0A_P_2 and VEX_LEN_3A0B_P_2.
	(vex_w_table): Update entries for VEX_W_10_P_1, VEX_W_10_P_3,
	VEX_W_11_P_1, VEX_W_11_P_3, VEX_W_2E_P_0, VEX_W_2E_P_2,
	VEX_W_2F_P_0, VEX_W_2F_P_2, VEX_W_51_P_1, VEX_W_51_P_3,
	VEX_W_52_P_1, VEX_W_53_P_1, VEX_W_58_P_1, VEX_W_58_P_3,
	VEX_W_59_P_1, VEX_W_59_P_3, VEX_W_5A_P_1, VEX_W_5A_P_3,
	VEX_W_5C_P_1, VEX_W_5C_P_3, VEX_W_5D_P_1, VEX_W_5D_P_3,
	VEX_W_5E_P_1, VEX_W_5E_P_3, VEX_W_5F_P_1, VEX_W_5F_P_3,
	VEX_W_7E_P_1, VEX_W_D6_P_2  VEX_W_C2_P_1, VEX_W_C2_P_3,
	VEX_W_3A0A_P_2 and VEX_W_3A0B_P_2.
	(intel_operand_size): Handle d_scalar_mode, d_scalar_swap_mode,
	q_scalar_mode, q_scalar_swap_mode.
	(OP_XMM): Handle scalar_mode.
	(OP_EX): Handle d_scalar_mode, d_scalar_swap_mode, q_scalar_mode
	and q_scalar_swap_mode.
	(OP_VEX): Handle vex_scalar_mode.
 2010-01-27 14:34:40 +00:00
H.J. Lu
80de6e001d Set the first 3byte VEX prefix individually. 
2010-01-24  H.J. Lu  <hongjiu.lu@intel.com>

	* config/tc-i386.c (build_vex_prefix): Set i.vex.bytes[0] to
	0xc4 individually.
 2010-01-24 15:44:05 +00:00
Richard Sandiford
c865e45b1b bfd/ 
* coff-rs6000.c (xcoff_howto_table): Change size to 0 and bitsize to 1.
	(_bfd_xcoff_reloc_type_lookup): Handle BFD_RELOC_NONE.
	* coff64-rs6000.c (xcoff64_howto_table): Change size to 0 and
	bitsize to 1.
	(xcoff64_reloc_type_lookup): Handle BFD_RELOC_NONE.

gas/
	* write.h (fix_at_start): Declare.
	* write.c (fix_new_internal): Add at_beginning parameter.
	Use it instead of REVERSE_SORT_RELOCS.  Fix the handling of
	seg_fix_tailP for the at_beginning/REVERSE_SORT_RELOCS case.
	(fix_new, fix_new_exp): Update accordingly.
	(fix_at_start): New function.
	* config/tc-ppc.c (md_pseudo_table): Add .ref to the OBJ_XCOFF section.
	(ppc_ref): New function, for OBJ_XCOFF.
	(md_apply_fix): Handle BFD_RELOC_NONE for OBJ_XCOFF.
	* config/te-i386aix.h (REVERSE_SORT_RELOCS): Remove #undef.

gas/testsuite/
	* gas/ppc/xcoff-ref-1.s, gas/ppc/xcoff-ref-1.l: New test.
	* gas/ppc/aix.exp: Run it.


ld/testsuite/
	* ld-powerpc/aix-ref-1-32.od, ld-powerpc/aix-ref-1-64.od,
	ld-powerpc/aix-ref-1.s: New tests.
	* ld-powerpc/aix52.exp: Run them.
 2010-01-23 12:05:33 +00:00
Rainer Orth
53e5c8fee6 * config/te-solaris.h (DWARF2_EH_FRAME_READ_ONLY): Make read-only 
on 64-bit Solaris/x86.
	Include obj-format.h earlier.
 2010-01-21 20:58:34 +00:00
Andreas Krebbel
55786da2bf 2010-01-21 Andreas Krebbel <Andreas.Krebbel@de.ibm.com> 
* readelf.c (get_machine_flags): Handle EF_S390_HIGH_GPRS.

2010-01-21  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>

	* s390.h (EF_S390_HIGH_GPRS): Added macro definition.

2010-01-21  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>

	* config/tc-s390.c (s390_elf_final_processing): New function.
	* config/tc-s390.h (elf_tc_final_processing): New macro definition.
	(s390_elf_final_processing): Added prototype.

2010-01-21  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>

	* elf32-s390.c (elf32_s390_merge_private_bfd_data): New function.
	(bfd_elf32_bfd_merge_private_bfd_data): New macro definition.
 2010-01-21 11:40:28 +00:00
Tristan Gingold
37a1f2771f 2010-01-18 Tristan Gingold <gingold@adacore.com> 
* config/tc-ia64.c (ia64_vms_note): Generate 24 bytes note headers.
 2010-01-19 09:14:54 +00:00
Sebastian Pop
a6461c0251 2010-01-15 Sebastian Pop <sebastian.pop@amd.com> 
gas/
	* config/tc-i386.c (md_assemble): Before accessing the IMM field
	check that it's not an XOP insn.

gas/testsuite/
	* gas/i386/x86-64-xop.d: Add missing patterns.
	* gas/i386/x86-64-xop.s: Same.
	* gas/i386/xop.d: Same.
	* gas/i386/xop.s: Same.

opcodes/
	* i386-opc.tbl: Support all the possible aliases for VPCOM* insns.
	* i386-tbl.h: Regenerated.
 2010-01-15 21:24:13 +00:00
Jie Zhang
62fb9fe1fc * config/bfin-aux.h: Remove argument names in function 
declarations.
	* config/bfin-lex.l (parse_int): Fix shadowed variable name
	warning.
	* config/bfin-parse.y (value_match): Remove argument names
	in declaration.
	(notethat): Likewise.
	(yyerror): Likewise.
 2010-01-14 04:52:57 +00:00
Daniel Jacobowitz
afa62d5e34 gas/ 
* config/tc-arm.c (do_t_nop): Correct check for Thumb-2 NOP.

	gas/testsuite/
	* gas/arm/thumb-nop.d, gas/arm/thumb-nop.s: New test.
	* gas/arm/relax_branch_align.d: Expect a default NOP instruction.
	* gas/arm/vfp1_t2.d, gas/arm/vfp1xD_t2.d: Specify a CPU with
	Thumb-2.

	ld/testsuite/
	* ld-arm/arm-elf.exp (armelftests): Assemble Cortex-A8 tests with
	-mcpu=cortex-a8.
 2010-01-13 19:01:10 +00:00
Nick Clifton
52b010e442 * config/tc-h8300.c (h8300_elf_section): New function - issue a 
warning message if a new section is created without setting any
        attributes for it.
        (md_pseudo_table): Intercept section creation pseudos.
        (md_pcrel_from): Replace abort with an error message.
        * config/obj-elf.c (obj_elf_section_name): Export this function.
        * config/obj-elf.h (obj_elf_section_name): Prototype.

        * gas/elf/section0.d: Skip this test for the h8300.
        * gas/elf/section1.d: Likewise.
        * gas/elf/section6.d: Likewise.
        * gas/elf/elf.exp: Skip section2 and section5 tests when the
        target is the h8300.

        * ld-scrips/sort.exp: Skip these tests when the target is the
        h8300.
 2010-01-13 14:08:54 +00:00
Sebastian Pop
69dd98654a 2010-01-06 Quentin Neill <quentin.neill@amd.com> 
gas/
       * config/tc-i386.c (cpu_arch): Add amdfam15.
         (i386_align_code): Add PROCESSOR_AMDFAM15 cases.
       * config/tc-i386.h (processor_type): Add PROCESSOR_AMDFAM15.
       * doc/c-i386.texi: Add amdfam15.

opcodes/
       * i386-gen.c (cpu_flag_init): Add new CPU_AMDFAM15_FLAGS.
       * i386-init.h: Regenerated.

testsuite/
       * gas/i386/i386.exp: Add new amdfam15 test cases.
       * gas/i386/nops-1-amdfam15.d: New.
 2010-01-06 22:52:47 +00:00
Nick Clifton
e3e535bc58 * arm-dis.c (print_insn): Fixed search for next 
symbol and data dumping condition, and the
    initial mapping symbol state.

    * gas/arm/dis-data.d: New test case.
    * gas/arm/dis-data.s: New file.
 2010-01-06 15:02:45 +00:00
Daniel Gutson
4316f0d240 2010-01-04 Daniel Gutson <dgutson@codesourcery.com> 
gas/
        * config/tc-arm.c (do_neon_logic): Accept imm value
        in the third operand too.
        (operand_parse_code): OP_RNDQ_IMVNb renamed to
        OP_RNDQ_Ibig.
        (parse_operands): OP_NILO case removed, applied renaming.
        (insns): Neon shape changed for some logic instructions.

        gas/testsuite/
        * gas/arm/neon-logic.d: New test case.
        * gas/arm/neon-logic.s: New file.
 2010-01-04 23:31:04 +00:00
Daniel Gutson
b1a769ed35 2010-01-04 Daniel Gutson <dgutson@codesourcery.com> 
gas/
    * config/tc-arm.c (do_neon_ldx_stx): Added
    validation for vector load/store insns.

    gas/testsuite/
    * gas/arm/neon-addressing-bad.d: New test case.
    * gas/arm/neon-addressing-bad.s: New file.
    * gas/arm/neon-addressing-bad.l: New file.
 2010-01-04 22:19:03 +00:00
Alan Modra
0dc9305793 bfd/ 
* archures.c: Add bfd_mach_ppc_e500mc64.
	* bfd-in2.h: Regenerate.
	* cpu-powerpc.c (bfd_powerpc_archs): Add entry for
	bfd_mach_ppc_e500mc64.
gas/
	* config/tc-ppc.c (md_show_usage): Document -me500mc64.
opcodes/
	* ppc-dis.c (ppc_opts): Add entry for "e500mc64".
 2010-01-04 02:32:56 +00:00
Daniel Gutson
88714cb802 2010-01-03 Daniel Gutson <dgutson@codesourcery.com> 
gas/
    * config/tc-arm.c (struct arm_it): New flag 'is_neon'.
    (NEON_ENC_*): Macros renamed to _NEON_ENC_*.
    (NEON_ENCODE): New macro.
    (check_neon_suffixes): New macro.
    (do_vfp_cond_or_thumb): Set the 'is_neon' flag.
    (do_vfp_nsyn_opcode): Likewise.
    (do_vfp_nsyn_nmul): Use the new 'NEON_ENCODE' macro.
    (do_vfp_nsyn_cmp): Likewise.
    (do_neon_shl_imm): Likewise.
    (do_neon_qshl_imm): Likewise.
    (neon_dyadic_misc): Likewise.
    (do_neon_mac_maybe_scalar): Likewise.
    (do_neon_qdmulh): Likewise.
    (do_neon_qmovn): Likewise.
    (do_neon_qmovun): Likewise.
    (do_neon_movn): Likewise.
    (neon_mac_reg_scalar_long): Likewise.
    (do_neon_vmull): Likewise.
    (do_neon_trn): Likewise.
    (do_neon_ldx_stx): Likewise.
    (neon_dp_fixup): Changed signature and set the flag.
    (neon_three_same): Call the above with new signature.
    (neon_two_same): Likewise.
    (neon_imm_shift): Likewise.
    (neon_mul_mac): Likewise.
    (do_neon_abs_neg): Likewise.
    (neon_mixed_length): Likewise.
    (do_neon_ext): Likewise.
    (do_neon_mov): Likewise.
    (do_neon_tbl_tbx): Likewise.
    (do_neon_logic): Likewise, and use the new 'NEON_ENCODE' macro.
    (neon_compare): Likewise.
    (do_neon_shll): Likewise.
    (do_neon_cvt): Likewise.
    (do_neon_mvn): Likewise.
    (do_neon_dup): Likewise.
    (md_assemble): Call check_neon_suffixes ().

    gas/testsuite/
    * gas/arm/neon-suffix-bad.d: New test case.
    * gas/arm/neon-suffix-bad.s: New file.
    * gas/arm/neon-suffix-bad.l: New file.
 2010-01-04 00:39:28 +00:00
Ramana Radhakrishnan
4a42ebbc0e Fix Thumb2 bl range options. 
2009-12-21  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
            Richard Earnshaw  <richard.earnshaw@arm.com>

        * config/tc-arm.c (encode_thumb2_b_bl_offset): New. Refactored
        from md_apply_fix.
        (md_apply_fix): Fixup range checks for Thumb2 version
        of unconditional calls. Call encode_thumb2_b_bl_offset for
        unconditional branches / function calls.
 2009-12-21 12:56:41 +00:00
H.J. Lu
2426c15ff8 Replace VexNDS, VexNDD and VexLWP with VexVVVV. 
gas/

2009-12-19  H.J. Lu  <hongjiu.lu@intel.com>

	* config/tc-i386.c (process_operands): Check vexvvvv instead
	of vexnds and vexndd.
	(build_modrm_byte): Check vexvvvv instead of vexnds, vexndd
	and vexlwp.

opcodes/

2009-12-19  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (opcode_modifiers): Remove VexNDS, VexNDD and
	VexLWP.  Add VexVVVV.

	* i386-opc.h (VexNDS): Removed.
	(VexNDD): Likewise.
	(VexLWP): Likewise.
	(VEXXDS): New.
	(VEXNDD): Likewise.
	(VEXLWP): Likewise.
	(VexVVVV): Likewise.
	(i386_opcode_modifier): Remove vexnds, vexndd and vexlwp.
	Add vexvvvv.

	* i386-opc.tbl: Replace VexNDS with VexVVVV=1, VexNDD with
	VexVVVV=2 and VexLWP with VexVVVV=3.
	* i386-tbl.h: Regenerated.
 2009-12-19 18:36:27 +00:00
Maciej W. Rozycki
7c0fc5246b gas/ 
* config/tc-mips.c (s_mips_ent): Also set BSF_FUNCTION for
	".aent".

	gas/testsuite/
	* gas/mips/aent.d: New test.
	* gas/mips/aent.s: Source for the new test.
	* gas/mips/mips.exp: Run it.
 2009-12-19 00:21:29 +00:00
Steve Ellcey
fd4db1a12f 2009-12-18 Steve Ellcey <sje@cup.hp.com> 
* config/tc-hppa.c: Change access to access_ctr.
 2009-12-18 18:11:56 +00:00
Nick Clifton
ff4a8d2b93 PR binutils/10924 
* config/tc-arm.c (do_ldstv4): Do not allow r15 as the destination
        register.
        (do_mrs): Likewise.
        (do_mul): Likewise.

        * arm-dis.c: Add support for %<>ru and %<>rU formats to enforce
        unique register numbers.  Extend support for %<>R format to
        thumb32 and coprocessor instructions.

        * gas/arm/unpredictable.s: Add more unpredictable instructions.
        * gas/arm/unpredictable.d: Add expected disassemblies.
 2009-12-17 09:52:18 +00:00
H.J. Lu
2eb952a4d9 Remove ByteOkIntel. 
gas/

2009-12-16  H.J. Lu  <hongjiu.lu@intel.com>

	* config/tc-i386.c (process_suffix): Set i.suffix to 0 in
	Intel syntax if size is ignored and b/l/w suffixes are
	illegal.
	(check_byte_reg): Remove byteokintel check.

opcodes/

2009-12-16  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (opcode_modifiers): Remove ByteOkIntel.

	* i386-opc.h (ByteOkIntel): Removed.
	(i386_opcode_modifier): Remove byteokintel.

	* i386-opc.tbl: Remove ByteOkIntel.
	* i386-tbl.h: Regenerated.
 2009-12-16 20:08:32 +00:00
H.J. Lu
7f399153c6 Replace Vex0F, Vex0F38, Vex0F3A, XOP08, XOP09 and XOP0A with VexOpcode. 
gas/

2009-12-16  H.J. Lu  <hongjiu.lu@intel.com>

	* config/tc-i386.c (build_vex_prefix): Replace vex0f, vex0f38,
	vex0f3a, xop08, xop09 and xop0a with vexopcode.

opcodes/

2009-12-16  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (opcode_modifiers): Remove Vex0F, Vex0F38,
	Vex0F3A, XOP08, XOP09 and XOP0A.  Add VexOpcode.

	* i386-opc.h (Vex0F): Removed.
	(Vex0F38): Likewise.
	(Vex0F3A): Likewise.
	(VexOpcode): New.
	(VEX0F): Likewise.
	(VEX0F38): Likewise.
	(VEX0F3A): Likewise.
	(XOP08): Defined as a macro.
	(XOP09): Likewise.
	(XOP0A): Likewise.
	(i386_opcode_modifier): Remove vex0f, vex0f38, vex0f3a, xop08,
	xop09 and xop0a.  Add vexopcode.

	* i386-opc.tbl: Replace Vex0F with VexOpcode=0, Vex0F38 with
	VexOpcode=1, Vex0F3A with VexOpcode=2, XOP08 with VexOpcode=3,
	XOP09 with VexOpcode=4 and XOP0A with VexOpcode=5.
	* i386-tbl.h: Regenerated.
 2009-12-16 15:43:16 +00:00
H.J. Lu
8c43a48b28 Replace VEX2SOURCES with XOP2SOURCES. 
gas/

2009-12-15  H.J. Lu  <hongjiu.lu@intel.com>

	* config/tc-i386.c (build_modrm_byte): Check XOP2SOURCES
	instead VEX2SOURCES.

opcodes/

2009-12-15  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-opc.h (VEX2SOURCES): Renamed to ...
	(XOP2SOURCES): This.
 2009-12-16 05:18:11 +00:00
H.J. Lu
8cd7925b45 Replace Vex2Sources and Vex3Sources with VexSources. 
gas/

2009-12-15  H.J. Lu  <hongjiu.lu@intel.com>

	* config/tc-i386.c (process_operands): Check vexsources
	instead of vex3sources.
	(build_modrm_byte): Check vexsources instead of vex2sources
	and vex3sources.

opcodes/

2009-12-15  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (opcode_modifiers): Remove Vex3Sources and
	Vex2Sources.  Add VexSources.

	* i386-opc.h ()Vex2Sources: Removed.
	(Vex3Sources): Likewise.
	(VEX2SOURCES): New.
	(VEX3SOURCES): Likewise.
	(VexSources): Likewise.
	(i386_opcode_modifier): Remove vex2sources and vex3sources.
	Add vexsources.

	* i386-opc.tbl: Replace Vex2Sources with VexSources=1 and
	Vex3Sourceswith VexSources=2.
	* i386-tbl.h: Regenerated.
 2009-12-16 04:00:35 +00:00
H.J. Lu
1ef99a7be9 Remove VexW0 and VexW1. Add VexW. 
gas/

2009-12-15  H.J. Lu  <hongjiu.lu@intel.com>

	* config/tc-i386.c (build_vex_prefix): Replace vexw0/vexw1
	with vexw.
	(build_modrm_byte): Likewise.

opcodes/

2009-12-15  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (opcode_modifiers): Remove VexW0 and VexW1.  Add
	VexW.

	* i386-opc.h (VexW0): Removed.
	(VexW1): Likewise.
	(VEXW0): New.
	(VEXW1): Likewise.
	(VexW): Likewise.
	(i386_opcode_modifier): Remove vexw0 and vexw1.  Add vexw.

	* i386-opc.tbl: Replace VexW0 with VexW=1 and VexW1 with
	Vex=2.
	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.
 2009-12-16 02:10:45 +00:00
H.J. Lu
e3c58833bf Define VEX128 and VEX256. 
gas/

2009-12-15  H.J. Lu  <hongjiu.lu@intel.com>

	* config/tc-i386.c (build_vex_prefix): Use VEX256.

opcodes/

2009-12-15  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-opc.h (VEX128): New.
	(VEX256): Likewise.
 2009-12-15 16:36:59 +00:00
Nick Clifton
34ab888845 PR gas/11089 
* config/tc-rx.c (rx_equ): Rename 'expr' to 'expression' in order
        to avoid shadowing a global symbol of the same name.
 2009-12-14 10:59:37 +00:00
Nick Clifton
c7d6f51805 * config/tc-microblaze.c (md_assemble): Rename 'imm' to 'immed' in 
order to avoid shadowing global variable of the same name.
 2009-12-14 09:50:18 +00:00
Andrew Jenner
2e98972ef6 * config/tc-arm.c (arm_init_frag): Set thumb MODE_RECORDED flag for 
non-elf.
       (arm_handle_align): Re-enable assert for non-elf.
 2009-12-11 17:44:24 +00:00
Nick Clifton
91d6fa6a03 Add -Wshadow to the gcc command line options used when compiling the binutils. 
Fix up all warnings generated by the addition of this switch.
 2009-12-11 13:42:17 +00:00
H.J. Lu
8a2c8fef19 2009-12-09 H.J. Lu <hongjiu.lu@intel.com> 
* config/tc-i386.c (arch_entry): Add len and skip.
	(cpu_arch): Use STRING_COMMA_LEN.
	(MESSAGE_TEMPLATE): New.
	(show_arch): Likewise.
	(md_show_usage): Use show_arch.
 2009-12-10 02:51:39 +00:00
Nick Clifton
03ee1b7f8e PR gas/11013 
* arm-dis.c (thumb32_opc): Adjust disassembly of QADD, QDADD, QSUB
        and QDSUB.

        * gas/arm/arch7em.d: Update expected disassembly.
        * gas/arm/thumb32.d: Likewise.

        * config/tc-arm.c (do_t_simd2): New function.
        (insns): Use do_t_simd2 for QADD, QDADD, QSUB and QDSUB.
 2009-12-02 20:26:30 +00:00
Nick Clifton
974da60de1 PR gas/11032 
* config/tc-arm.c (relax_adr): Cope with a frag with no symbol.
 2009-11-30 14:36:21 +00:00
Sebastian Pop
f0ae4a24b0 2009-11-18 Sebastian Pop <sebastian.pop@amd.com> 
gas/
	* config/tc-i386.c (cpu_arch): Remove cvt16.
	(md_show_usage): Same.
	* doc/c-i386.texi: Same.

	gas/testsuite/
	* gas/i386/cvt16.d: Removed.
	* gas/i386/cvt16.s: Removed.
	* gas/i386/x86-64-cvt16.d: Removed.
	* gas/i386/x86-64-cvt16.s: Removed.
	* gas/i386/i386.exp: Remove cvt16 and x86-64-cvt16 tests.

	opcodes/
	* i386-dis.c (VEX_LEN_XOP_08_A0): Removed.
	(VEX_LEN_XOP_08_A1): Removed.
	(xop_table): Remove entries for VEX_LEN_XOP_08_A0 and
	VEX_LEN_XOP_08_A1.
	(vex_len_table): Same.
	* i386-gen.c (CPU_CVT16_FLAGS): Removed.
	(cpu_flags): Remove field for CpuCVT16.
	* i386-opc.h (CpuCVT16): Removed.
	(i386_cpu_flags): Remove bitfield cpucvt16.
	(i386-opc.tbl): Remove CVT16 instructions.
	* i386-init.h: Regenerated.
	* i386-tbl.h: Regenerated.
 2009-11-18 20:28:59 +00:00
Paul Brook
ada65aa377 2009-11-18 Paul Brook <paul@codesourcery.com> 
gas/
	* config/tc-arm.c (arm_fpus): Add fpv4-sp-d16.
	(aeabi_set_public_attributes): Correctly mark VFPv3xD.

	include/opcode/
	* arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
 2009-11-18 15:48:59 +00:00
Alan Modra
2d0f389600 bfd/ 
* bfd-in.h (_bfd_elf_ppc_at_tls_transform): Declare.
	* bfd-in2.h: Regenerate.
	* elf64-ppc.c (ppc64_elf_relocate_section): Move code for R_PPC64_TLS
	insn optimisation to..
	* elf32-ppc.c (_bfd_elf_ppc_at_tls_transform): ..here.  New function.
	(ppc_elf_relocate_section): Use it.
gas/
	* config/tc-ppc.c (md_assemble): Report error on invalid @tls operands
	and opcode.
 2009-11-18 12:42:52 +00:00
Sebastian Pop
5dd85c9970 2009-11-17 Sebastian Pop <sebastian.pop@amd.com> 
Quentin Neill  <quentin.neill@amd.com>

	gas/
	* config/tc-i386.c (cpu_arch): Added .xop and .cvt16.
	(build_vex_prefix): Handle xop08.
	(md_assemble): Don't special case the constant 3 for insns using MODRM.
	(build_modrm_byte): Handle vex2sources.
	(md_show_usage): Add xop and cvt16.
	* doc/c-i386.texi: Document fma4, xop, and cvt16.

	gas/testsuite/
	* gas/i386/i386.exp: Run xop and cvt16 in 32-bit mode.
	Run x86-64-xop and x86-64-cvt16 in 64-bit mode.
	* gas/i386/lwp.d: Update name of the testcase.
	* gas/i386/x86-64-xop.d: New.
	* gas/i386/x86-64-xop.s: New.
	* gas/i386/xop.d: New.
	* gas/i386/xop.s: New.
	* gas/i386/cvt16.d: New.
	* gas/i386/cvt16.s: New.

	opcodes/
	* i386-dis.c (OP_Vex_2src_1): New.
	(OP_Vex_2src_2): New.
	(Vex_2src_1): New.
	(Vex_2src_2): New.
	(XOP_08): Added.
	(VEX_LEN_XOP_08_A0): Added.
	(VEX_LEN_XOP_08_A1): Added.
	(VEX_LEN_XOP_09_80): Added.
	(VEX_LEN_XOP_09_81): Added.
	(xop_table): Added an entry for XOP_08.  Handle xop instructions.
	(vex_len_table): Added entries for VEX_LEN_XOP_08_A0,
	VEX_LEN_XOP_08_A1, VEX_LEN_XOP_09_80, VEX_LEN_XOP_09_81.
	(get_valid_dis386): Handle XOP_08.
	(OP_Vex_2src): New.
	* i386-gen.c (cpu_flag_init): Add CPU_XOP_FLAGS and CPU_CVT16_FLAGS.
	(cpu_flags): Add CpuXOP and CpuCVT16.
	(opcode_modifiers): Add XOP08, Vex2Sources.
	* i386-opc.h (CpuXOP): Added.
	(CpuCVT16): Added.
	(i386_cpu_flags): Add cpuxop and cpucvt16.
	(XOP08): Added.
	(Vex2Sources): Added.
	(i386_opcode_modifier): Add xop08, vex2sources.
	* i386-opc.tbl: Add entries for XOP and CVT16 instructions.
	* i386-init.h: Regenerated.
	* i386-tbl.h: Regenerated.
 2009-11-18 04:04:17 +00:00
Paul Brook
9e3c6df664 2009-11-17 Paul Brook <paul@codesourcery.com> 
Daniel Jacobowitz  <dan@codesourcery.com>

	gas/
	* doc/c-arm.texi: Document .arch armv7e-m.
	* config/tc-arm.c (arm_ext_v6_dsp, arm_ext_v7m): New.
	(insns): Put Thumb versions of v5TExP instructions into
	arm_ext_v5exp also.  Move some Thumb variants from
	arm_ext_v6_notm to arm_ext_v6_dsp.
	(arm_archs): Add armv7e-m architecture.
	(aeabi_set_public_attributes): Handle -march=armv7e-m.

	gas/testsuite/
	* gas/arm/attr-march-armv7em.d: New test.
	* gas/arm/arch7em-bad.d: New test.
	* gas/arm/arch7em-bad.l: New test.
	* gas/arm/arch7em.d: New test.
	* gas/arm/arch7em.s: New test.

	include/elf/
	* arm.h (TAG_CPU_ARCH_V7E_M): Define.

	include/opcode/
	* arm.h (ARM_EXT_V6_DSP): Define.
	(ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
	(ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.

	binutils/
	* readelf.c (arm_attr_tag_CPU_arch): Add v7E-M.

	bfd/
	* elf32-arm.c (using_thumb_only, arch_has_arm_nop,
	arch_has_thumb2_nop): Handle TAG_CPU_ARCH_V7E_M.
	(tag_cpu_arch_combine): Ditto. Correct MAX_TAG_CPU_ARCH test.
 2009-11-17 16:31:56 +00:00
Nick Clifton
f7c21dc7b8 * config/tc-arm.c (parse_operands): Encode APSR_nzcv as r15. 
(do_vmrs): New function.
        (do_vmsr): New function.
        (insns): Add vmrs and vmsr.

        * gas/arm/vfp1xD.s: Add vmrs and vmsr instructions.
        * gas/arm/vfp1xD.d: Update expected disassembly.
 2009-11-16 11:47:36 +00:00
H.J. Lu
c1ba026631 Check destination operand for lockable instructions. 
gas/

2009-11-13  H.J. Lu  <hongjiu.lu@intel.com>

	* config/tc-i386.c (md_assemble): Check destination operand
	for lockable instructions.

gas/testsuite/

2009-11-13  H.J. Lu  <hongjiu.lu@intel.com>

	* gas/i386/lock-1-intel.d: Updated.
	* gas/i386/lock-1.d: Likewise.
	* gas/i386/lock-1.s: Likewise.
	* gas/i386/lockbad-1.l: Likewise.
	* gas/i386/lockbad-1.s: Likewise.
	* gas/i386/x86-64-lock-1-intel.d: Likewise.
	* gas/i386/x86-64-lock-1.d: Likewise.
	* gas/i386/x86-64-lock-1.s: Likewise.
	* gas/i386/x86-64-lockbad-1.l: Likewise.
	* gas/i386/x86-64-lockbad-1.s: Likewise.
 2009-11-14 06:04:34 +00:00
H.J. Lu
4473e00469 2009-11-13 H.J. Lu <hongjiu.lu@intel.com> 
* config/tc-i386.c (_i386_insn): Don't use bit field on
	swap_operand.
 2009-11-14 01:46:28 +00:00
H.J. Lu
c32fa91d70 gas/ 
2009-11-12  H.J. Lu  <hongjiu.lu@intel.com>

	* config/tc-i386.c (LOCKREP_PREFIX): Removed.
	(REP_PREFIX): New.
	(LOCK_PREFIX): Likewise.
	(PREFIX_GROUP): Likewise.
	(REX_PREFIX): Updated.
	(MAX_PREFIXES): Likewise.
	(add_prefix): Updated.  Return enum PREFIX_GROUP.
	(md_assemble): Check for lock without a lockable instruction.
	(parse_insn): Updated.
	(output_insn): Likewise.

gas/testsuite/

2009-11-12  H.J. Lu  <hongjiu.lu@intel.com>

	* gas/i386/i386.exp: Run lock-1, lock-1-intel, lockbad-1,
	x86-64-lock-1, x86-64-lock-1-intel and x86-64-lockbad-1.

	* gas/i386/lock-1-intel.d: New.
	* gas/i386/lock-1.d: Likewise.
	* gas/i386/lock-1.s: Likewise.
	* gas/i386/lockbad-1.l: Likewise.
	* gas/i386/lockbad-1.s: Likewise.
	* gas/i386/x86-64-lock-1-intel.d: Likewise.
	* gas/i386/x86-64-lock-1.d: Likewise.
	* gas/i386/x86-64-lock-1.s: Likewise.
	* gas/i386/x86-64-lockbad-1.l: Likewise.
	* gas/i386/x86-64-lockbad-1.s: Likewise.

opcodes/

2009-11-12  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (opcode_modifiers): Add IsLockable.

	* i386-opc.h (IsLockable): New.
	(i386_opcode_modifier): Add islockable.

	* i386-opc.tbl: Add IsLockable to add, adc, and, btc, btr,
	bts, cmpxchg, cmpxch8b, dec, inc, neg, not, or, sbb, sub,
	xor, xadd and xchg.
	* i386-tbl.h: Regenerated.
 2009-11-12 18:57:14 +00:00
H.J. Lu
1b9f0c97ad 2009-11-11 H.J. Lu <hongjiu.lu@intel.com> 
* config/tc-i386.c (build_modrm_byte): Don't set register
	operand twice.
 2009-11-12 02:21:46 +00:00