On ia64-linux, GDB sometimes prints the following error when trying
to switch to a different task:
(gdb) task 3
Register 0 is not available
This is a random failure that sometimes happens, sometimes does not.
The error comes from the fact that the libunwind library is requesting
the value of register 0 (zero): This eventually leads us to
ia64-linux-nat.c:ia64_linux_fetch_register.
This function relies on ia64_cannot_fetch_register to determine
whether or not we have access to the register's value. The ptrace
interface does not provide the r0 value, and so we end up telling
the regcache that this register's value is not available. And yet,
for r0, we do not need to ask ptrace for its value, since it is
always zero.
So, the fix was to add a special rule for supplying a nul value
when regnum == IA64_GR0_REGNUM.
gdb/ChangeLog:
* ia64-linux-nat.c (ia64_linux_fetch_register): Add special
handling for r0.
set_gdbarch_process_record.
Initialize `arm_swi_record' field.
* arm-tdep.c (arm_process_record): New function.
(deallocate_reg_mem): New function.
(decode_insn): New function.
(thumb_record_branch): New function.
(thumb_record_ldm_stm_swi(): New function.
(thumb_record_misc): New function.
(thumb_record_ld_st_stack): New function.
(thumb_record_ld_st_imm_offset): New function.
(thumb_record_ld_st_reg_offset(): New function.
(thumb_record_add_sub_cmp_mov): New function.
(thumb_record_shift_add_sub): New function.
(arm_record_coproc_data_proc): New function.
(arm_record_coproc): New function.
(arm_record_b_bl): New function.
(arm_record_ld_st_multiple): New function.
(arm_record_ld_st_reg_offset): New function.
(arm_record_ld_st_imm_offset): New function.
(arm_record_data_proc_imm): New function.
(arm_record_data_proc_misc_ld_str): New function.
(arm_record_extension_space): New function.
(arm_record_strx): New function.
(sbo_sbz): New function.
(struct insn_decode_record): New structure for arm insn record.
(REG_ALLOC): New macro for reg allocations.
(MEM_ALLOC): New macro for memory allocations.
* arm-tdep.h (struct gdbarch_tdep): New field 'arm_swi_record'
The common code has a sim_core_trans_addr() helper that only the m32r code
uses. Move the inline extern in the m32r code to the proper common header.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Similar to logic in the cris exp, attempt a simple compile and if it fails
(presumably due to the compiler being broken), skip all the related tests.
Fortunately, most tests (~600 out of ~800) are pure assembly, so people should
still get pretty good coverage.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* ldemul.c (before_allocation_default): Revert last change.
ldlang.c (lang_add_section): Likewise.
(strip_excluded_output_sections): Don't strip output sections with
user input sections when emitrelocations, unless all are SEC_EXCLUDE.
ld/testsuite/
* ld-powerpc/vxworks-relax.rd: Remove check on reloc section
file offset and reloc symbol indices.
Before POSIX standardized strsignal(), old systems would hide the
prototype unless the normal extension defines were enabled. So use
the AC_USE_SYSTEM_EXTENSIONS helper for that.
Then make sure we include string.h ourselves in nrun.c rather than
relying on implicit includes via other sim headers.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
The sim code gets the logic for SIM_AC_OPTION_WARNINGS from gdb, but
it hasn't been updated in a good long while. Sync with the latest
gdb code.
There is a sim specific change in here: we disable -Werror for now.
This is because all sim code atm contains warnings. Will probably
have to slowly add a white list of targets which can tolerate this
until everyone is updated.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
