2016-03-07 Jiong Wang <jiong.wang@arm.com>
bfd/
* elfnn-aarch64.c (elfNN_aarch64_check_relocs): Always create .got section
if the symbol "_GLOBAL_OFFSET_TABLE_" referenced.
ld/
* testsuite/ld-aarch64/implicit_got_section_1.s: New test source file.
* testsuite/ld-aarch64/implicit_got_section_1.d: New test expected result.
* testsuite/ld-aarch64/aarch64-elf.exp: Run new test.
For these three relocations, 17 bit signed value should be used, instead of
16 bit. The bitsize field is changed from 16 to 17, this field in aarch64
backend is used for overflow check only.
bfd/
2016-02-26 Renlin Li <renlin.li@arm.com>
* elfnn-aarch64.c (elfNN_aarch64_howto_table): Fix signed overflow
check for MOVW_SABS_G0, MOVW_SABS_G1, MOVW_SABS_G2.
ld/
2016-02-26 Renlin Li <renlin.li@arm.com>
* testsuite/ld-aarch64/aarch64-elf.exp: Run new testcases.
* testsuite/ld-aarch64/emit-relocs-270.d: Update to use new boundary.
* testsuite/ld-aarch64/emit-relocs-271.d: Likewise.
* testsuite/ld-aarch64/emit-relocs-272.d: Likewise.
* testsuite/ld-aarch64/emit-relocs-270-overflow.d: New.
* testsuite/ld-aarch64/emit-relocs-270-overflow.s: New.
* testsuite/ld-aarch64/emit-relocs-271-overflow.d: New.
* testsuite/ld-aarch64/emit-relocs-271-overflow.s: New.
* testsuite/ld-aarch64/emit-relocs-272-overflow.d: New.
* testsuite/ld-aarch64/emit-relocs-272-overflow.s: New.
bfd * elfnn-aarch64.c (elfNN_aarch64_relocate_section): Add a more
helpful warning message to explain why certain AArch64 relocs
might overflow.
ld * testsuite/ld-aarch64/reloc-overflow-bad.d: New test.
* testsuite/ld-aarch64/reloc-overflow-1.s: New source file.
* testsuite/ld-aarch64/reloc-overflow-2.s: New source file.
* testsuite/ld-aarch64/aarch64-elf.exp: Run the new test.
bfd * elfnn-aarch64.c (elfNN_aarch64_relocate_section): Add a more
helpful warning message to explain why certain AArch64 relocs
might overflow.
ld * testsuite/ld-aarch64/reloc-overflow-bad.d: New test.
* testsuite/ld-aarch64/reloc-overflow-1.s: New source file.
* testsuite/ld-aarch64/reloc-overflow-2.s: New source file.
* testsuite/ld-aarch64/aarch64-elf.exp: Run the new test.
As defined at AArch64 ELF Specification (4.6.7 Call and Jump
relocations), symbol with type of non STT_FUNC but in different input
section with relocation place should insert long branch veneer also.
Meanwhile the current long branch veneer infrastructure havn't considered
the situation where the branch destination is "sym_value + rela->addend".
This was OK because we only insert veneer for long call destination is
STT_FUNC symbol for which the addend is always zero. But as we relax the
support to other situations by this patch, we need to handle addend be
non-zero value. For example, for static function, relocation against
"local symbol" are turned into relocation against "section symbol + offset"
where there is a valid addend.
bfd/
* elfnn-aarch64.c (aarch64_type_of_stub): Allow insert long branch
veneer for sym_sec != input_sec.
(elfNN_aarch64_size_stub): Support STT_SECTION symbol.
(elfNN_aarch64_final_link_relocate): Take rela addend into account when
calculation destination.
ld/
* testsuite/ld-aarch64/farcall-section.d: Delete.
* testsuite/ld-aarch64/farcall-section.s: Delete.
* testsuite/ld-aarch64/farcall-b-section.d: New expectation file.
* testsuite/ld-aarch64/farcall-bl-section.d: Likewise.
* testsuite/ld-aarch64/farcall-b-section.s: New testcase.
* testsuite/ld-aarch64/farcall-bl-section.s: Likewise.
* testsuite/ld-aarch64/aarch64-elf.exp: Likewise.
bfd/
2015-10-02 Renlin Li <renlin.li@arm.com>
* elfnn-aarch64.c (IS_AARCH64_TLS_RELAX_RELOC): Add
TLSIE_MOVW_GOTTPREL_G1.
(aarch64_tls_transition_without_check): Add
TLSIE_MOVW_GOTTPREL_G1 to TLSLE_MOVW_TPREL_G2
transition for local symbol.
(elfNN_aarch64_tls_relax): Add a argument to pass tp offset.
Add TLSIE_MOVW_GOTTPREL_G1 relaxation.
(elfNN_aarch64_relocate_section): Call elfNN_aarch64_tls_relax
with new argument.
ld/testsuite/
2015-10-02 Renlin Li <renlin.li@arm.com>
* ld-aarch64/aarch64-elf.exp (tls-relax-large-le-ie): Run new test.
* ld-aarch64/tls-relax-large-ie-le.d: New.
* ld-aarch64/tls-relax-large-ie-le.s: New.
bfd/
2015-10-02 Renlin Li <renlin.li@arm.com>
* elfnn-aarch64.c(IS_AARCH64_TLS_RELAX_RELOC):
Add relaxation support for TLSGD_MOVW_G0_NC and TLSGD_MOVW_G1.
(aarch64_tls_transition_without_check): Likewise
(elfNN_aarch64_tls_relax): Likwise.
ld/testsuite/
2015-10-02 Renlin Li <renlin.li@arm.com>
* ld-aarch64/aarch64-elf.exp: run new test
* ld-aarch64/tls-relax-large-gd-ie.d: New.
* ld-aarch64/tls-relax-large-gd-ie.s: New.
* ld-aarch64/tls-relax-large-gd-le.d: New.
* ld-aarch64/tls-relax-large-gd-le.s: New.
This patch fixed those failures on elf configuration by:
* Improve the ILP32 target selector "aarch64_choose_ilp32_emul",
makes it more robust. Target triples copied from configure.tgt
* Updated emit-relocs-86/-overflow.d to use aarch64_choose_ilp32_emul
which is following what have done with emit-relocs-28.
* Those instruction encoding mismatch is because those encoding
contains pc-relative address. As for elf, we may have different
start address. relaxed encodind check, especially for
aarch64-farcall-b/bl-plt, as the main purpose of those check are
ELF text/data layout, we just want to make sure veneer to plt stub
is generated.
2015-08-12 Jiong Wang <jiong.wang@arm.com>
ld/testsuite/
* ld-aarch64/aarch64-elf.exp (aarch64_choose_ilp32_emul): Support all
four triple shapes: aarch64-*-linux*, aarch64-*-elf,
aarch64_be-*-linux*, aarch64_be-*-elf.
* ld-aarch64/emit-relocs-86.d: Use aarch64_choose_ilp32_emul.
* ld-aarch64/emit-relocs-86-overflow.d: Likewise.
* ld-aarch64/ld-aarch64/farcall-b-plt.d: Relax instrucion encoding
check when they reflect address.
* ld-aarch64/ld-aarch64/farcall-bl-plt.d: Likewise.
2015-08-11 Jiong Wang <jiong.wang@arm.com>
bfd/
* bfd/elfnn-aarch64.c (aarch64_type_of_stub): New parameter "sym_sec".
Loose the check for symbol from ABS section.
(elfNN_aarch64_size_stubs): Pass sym_sec.
ld/testsuite/
* ld-aarch64/farcall-b-defsym.s: New test.
* ld-aarch64/farcall-bl-defsym.s: Likewise.
* ld-aarch64/farcall-b-defsym.d: New expectation.
* ld-aarch64/farcall-bl-defsym.d: Likewise.
Emit *GLOB_DAT instead of *RELATIVE relocs for protected data
in shared objects.
This is needed for the fix of glibc bug 17711:
https://sourceware.org/bugzilla/show_bug.cgi?id=17711
bfd:
PR ld/18705
* elfnn-aarch64.c (elf_backend_extern_protected_data): Define.
ld/testsuite:
PR ld/18705
* ld-aarch64/protected-data.d: New.
* ld-aarch64/protected-data.s: New.
* ld-aarch64/aarch64-elf.exp: Add new test.
2015-06-23 Jiong Wang <jiong.wang@arm.com>
bfd/
* elfnn-aarch64.c (aarch64_readonly_dynrelocs): New function.
(elfNN_aarch64_size_dynamic_sections): Traverse hash table to check
relocations against read-only sections.
ld/testsuite/
* ld-aarch64/dt_textrel.s: New testcase.
* ld-aarch64/dt_textrel.d: New expectation file.
* ld-aarch64/aarch64-elf.exp: Run new testcase.
2015-06-17 Jiong Wang <jiong.wang@arm.com>
ld/testsuite/
* ld-aarch64/aarch64-elf.exp (aarch64_choose_ilp32_emul): New function.
* ld-aarch64/emit-relocs-28.d: Use aarch64_choose_ilp32_emul to choose
emulation mode.
When commit the following code for Matthew, I wrongly included my local changes. Revert it. Sorry.
commit a5932920ef
Author: Matthew Wahab <matthew.wahab@arm.com>
Date: Wed Jun 3 10:03:50 2015 +0100
BFD_RELOC_AARCH64_TLSLE_ADD_LO12 is used to generate simplest
one-instruction addressing for TLS LE model when tls size is smaller
4K. Linker need to make sure there is no TLS offset overflow.
2015-06-01 Jiong Wang <jiong.wang@arm.com>
bfd/
* elfnn-aarch64.c (elfNN_aarch64_howto_table): Set overflow type to
complain_overflow_unsigned for BFD_RELOC_AARCH64_TLSLE_ADD_LO12.
* elfxx-aarch64.c (_bfd_aarch64_elf_resolve_relocation): Don't use
PGOFF for BFD_RELOC_AARCH64_TLSLE_ADD_LO12, that will mask off all
potential high overflowed bits.
ld/testsuite/
* ld-aarch64/tprel_add_lo12_overflow.s: New testcase.
* ld-aarch64/tprel_add_lo12_overflow.d: Nex expectation file.
* ld-aarch64/aarch64-elf.exp: Run new testcase.
Some early revisions of the Cortex-A53 have an erratum (843419). The
details of the erratum are quite complex and involve dynamic
conditions. For the purposes of the workaround we have simplified the
static conditions to an ADRP in the last two instructions of a 4KByte
page, followed within four instructions by a load/store dependent on
the ADRP.
This patch adds support to conservatively scan for and workaround
Cortex A53 erratum 843419. There are two different workaround
strategies used. The first is to rewrite ADRP instructions which form
part of an erratum sequence with an ADR instruction. In situations
where the ADR provides insufficient offset the dependent load or store
instruction from the sequence is moved to a stub section and branches
are inserted from the original sequence to the relocated instruction
and back again.
Stub section sizes are rounded up to a multiple of 4096 in order to
ensure that the act of inserting work around stubs does not create
more errata sequences.
Workaround stubs are always inserted into the stub section associated
with the input section containing the erratum sequence. This ensures
that the fully relocated form of the veneered load store instruction
is available at the point in time when the stub section is written.
Ensure that injection of a stub section does not break a link where
there is an xpectation that flow of control can pass from one input
section to another simply by linking the input sections in series.
The solution here is to allow stub sections to be inserted after any
input section (existing behaviour), but inject an additional branch at
the start of each stub section such that control flow falling into the
stub section will branch over the stub section.
bfd/
PR gas/17843
* elfxx-aarch64.c (_bfd_aarch64_elf_put_addend): Expect
R_AARCH64_TLSLE_MOVW_TPREL_G0_NC and R_AARCH64_TLSLE_MOVW_TPREL_G1_NC
to be used with MOVK rather than MOVZ.
gas/
PR gas/17843
* config/tc-aarch64.c (process_movw_reloc_info): Allow
R_AARCH64_TLSLE_MOVW_TPREL_G0_NC and R_AARCH64_TLSLE_MOVW_TPREL_G1_NC
for MOVK.
gas/testsuite/
PR gas/17843
* gas/aarch64/tls.s, gas/aarch64/tls.d: Add test for
R_AARCH64_TLSLE_MOVW_TPREL_G0/R_AARCH64_TLSLE_MOVW_TPREL_G1_NC
sequence.
ld/testsuite/
PR gas/17843
* ld-aarch64/tlsle.s, ld-aarch64/tlsle.d: New test.
* ld-aarch64/aarch64-elf.exp: Run it.
