Commit graph

3626 commits

Author SHA1 Message Date
Joel Brobecker
bb9e16d4bb Fix latest sim/common/ChangeLog entry. 2015-06-09 14:29:09 -04:00
Joel Brobecker
f419f52b9b Remove unnecessary empty line in sim/common/ChangeLog 2015-06-09 14:27:58 -04:00
Mike Stump
509c2f329a Fix spelling mistakes in sim/common/sim-events.c error messages.
sim/common/ChangeLog:

        * sim-events.c (sim_events_schedule_after_signal): Fix spelling
        mistake in call to sim_engine_abort.
        (sim_events_schedule_after_signal): Likewise.
2015-06-09 14:27:46 -04:00
Mike Frysinger
296730a52b sim: erc32: restore attribution 2015-05-17 17:15:36 +08:00
Joel Brobecker
17d88f73c0 Switch erc32 simulator copyright headers to FSF.
Permission was granted by Jiri Gaisler, who has a copyright assignment
on file for GDB.

sim/erc32/ChangeLog:

        * configure.ac: Add copyright header.
        * erc32.c: Change copyright holder to FSF.  Reformat.
        * exec.c, float.c, func.c, interf.c, sis.c, sis.h: Likewise.
        * help.c, startsim: Add copyright header.
2015-05-08 07:23:15 -07:00
DJ Delorie
0952813b0b Make RL78 disassembler and simulator respect ISA for mul/div
[gas]
	* config/rl78-defs.h (rl78_isa_g10): New.
	(rl78_isa_g13): New.
	(rl78_isa_g14): New.
	* config/rl78-parse.y (ISA_G10): New.
	(ISA_G13): New.
	(ISA_G14): New.
	(MULHU, MULH, MULU, DIVHU, DIVWU, MACHU, MACH): Use them.
	* config/tc-rl78.c (rl78_isa_g10): New.
	(rl78_isa_g13): New.
	(rl78_isa_g14): New.

[gdb]
	* rl78-tdep.c (rl78_analyze_prologue): Pass RL78_ISA_DEFAULT to
	rl78_decode_opcode

[include]
	* dis-asm.h (print_insn_rl78_g10): New.
	(print_insn_rl78_g13): New.
	(print_insn_rl78_g14): New.
	(rl78_get_disassembler): New.
	* opcode/rl78.h (RL78_Dis_Isa): New.
	(rl78_decode_opcode): Add ISA parameter.

[opcodes]
	* disassemble.c (disassembler): Choose suitable disassembler based
	on E_ABI.
	* rl78-decode.opc (rl78_decode_opcode): Take ISA parameter.  Use
	it to decode mul/div insns.
	* rl78-decode.c: Regenerate.
	* rl78-dis.c (print_insn_rl78): Rename to...
	(print_insn_rl78_common): ...this, take ISA parameter.
	(print_insn_rl78): New.
	(print_insn_rl78_g10): New.
	(print_insn_rl78_g13): New.
	(print_insn_rl78_g14): New.
	(rl78_get_disassembler): New.

[sim]
	* rl78/cpu.c (g14_multiply): New.
	* rl78/cpu.h (g14_multiply): New.
	* rl78/load.c (rl78_load): Decode ISA completely.
	* rl78/main.c (main): Expand -M to include other ISAs.
	* rl78/rl78.c (decode_opcode): Decode based on ISA.
	* rl78/trace.c (rl78_disasm_fn): New.
	(sim_disasm_init): Reset it.
	(sim_disasm_one): Get correct disassembler for ISA.
2015-04-30 15:25:49 -04:00
Nick Clifton
0a13382c8e Fix problems in the sim sources discovered by running the cppcheck static analysis tool.
erc32	PR 18273
	* sis.c (main): Remove unreachable code.

m68hc11	* gencode.c (gen_fetch_operands): Remove unreachable code.

ppc	* hw_htab.c (htab_map_binary): Fix overlap check.

common	* sim-fpu.c (INLINE_SIM_FPU): Fix static analysis warning by
	increasing parenthesis around casts to signed values.
2015-04-29 16:02:02 +01:00
Senthil Kumar Selvaraj
180d40b903 sim: avr: Fix 'multiple definition of sim_{read,write}'
This patch does whatever was done in
https://sourceware.org/ml/gdb-patches/2015-04/msg00437.html to fix
broken gdb build for the AVR target.
2015-04-27 09:54:37 -04:00
Nick Clifton
de7669bfa5 Fix typos in sim sources exposed by static analysis.
bfin	PR 18273
	* bfin-sim.c (decode_dsp32alu_0): Remove spurious check for
	s == 1.

erc32	PR 18273
	* exec.c (add32): Fix typo in check for overflow.

igen	PR 18273
	* misc.c (a2i): Fix typos checking for uppercase letters.
2015-04-24 15:43:21 +01:00
Nick Clifton
63c72d1ae4 Fix typo in check for valid register number in RX sim.
PR sim/18273
	* reg.c (put_reg): Fix check for valid register number.
2015-04-24 15:31:36 +01:00
Mike Frysinger
43236bb255 sim: mcore: clean up printf warnings
These printf statements are showing "word" objects which are typedefed
from long, so make sure to use l with %x when printing them to avoid
warnings from gcc.
2015-04-21 03:10:16 -04:00
Mike Frysinger
f63036b811 sim: mcore: convert to common memory/verbose functions
Re-use the existing memory core that handles reads/writes.

The verbose command is converted to the common --verbose flag
since only a few call sites use it now.
2015-04-21 03:10:16 -04:00
Mike Frysinger
e53e5aab53 sim: mcore: drop watchpoint/dumpmem/clearstats support
In preparation for converting to the common memory framework, the custom
commands get in our way.  But when we realize that gdb support has been
dropped for mcore, it makes things a bit easier: the main runner does not
let you run arbitrary commands once simulation starts.

So lets disable watchpoint support until it can be converted to the common
watchpoint logic.  There's already an ifdef to let us do that.

We straight up drop support for the dumpmem command (no other sim supports
this, and if it's a feature people want, we can add a common func) and the
clearstats command (not a big deal -- just restart your simulation).

We leave in place the verbose check points as a follow up commit will cut
that over to common logic.
2015-04-21 03:10:16 -04:00
Mike Frysinger
767e68f1b9 sim: mcore: switch to common syscall handling
Now that libgloss has a header tracking the syscalls for this arch, we
can update the database to include it for the symbolic constants/maps.
Then we can switch the mcore syscall callbacks over to the common ones.
2015-04-21 03:10:16 -04:00
Mike Frysinger
248d23e82b sim: gennltvals.sh: handle split out newlib source tree
Since newlib no longer shares the same repo as binutils/gdb, we have to go
searching further afield to locate the sources.  We still look at the top
level for newlib, but if that is not found, we also try up one dir outside
of this source tree.  It sucks, but better than the status quo (no workie).
2015-04-21 03:10:16 -04:00
Jiri Gaisler
d3e9b40afb sim/erc32: Switched emulated memory to host endian order.
Change data ordering in emulated memory from target order (big endian)
to host order. Improves performance and simplifies most memory
operations. Requires some byte twisting during stores on little
endian hosts (intel). Also removed support for little-endian binaries.
2015-04-19 02:29:44 -04:00
Mike Frysinger
3ebe2863f7 sim: clean up duplicate sim-engine hooks
Now that we've unified sim-cpu, we can delete the duplicate sim-engine
hooks -- these targets defined these only because they didn't fully
implement the sim-cpu callbacks.
2015-04-18 04:40:27 -04:00
Mike Frysinger
e8d3a34fee sim: trim old USING_SIM_BASE_H define
This doesn't appear to have been used since 1998, but wasn't cleaned
up since.  So much for being "quick" ;).
2015-04-18 04:32:56 -04:00
Mike Frysinger
20bca71d82 sim: unify SIM_CPU definition
Since every target typedefs this the same way, move it to the common code.

We have to leave Blackfin behind here for now because of inter-dependencies
on types and headers: sim-base.h includes sim-model.h which needs types in
machs.h which needs types in bfim-sim.h which needs SIM_CPU.
2015-04-18 04:31:36 -04:00
Mike Frysinger
7e83aa92f2 sim: unify sim_cia definition
Almost every target defines sim_cia the same way -- either using the
address_word type directly, or a type of equivalent size.  The only
odd one out is sh64 (who has 32bit address_word and 64bit cia), and
even that case doesn't seem to make sense.  We'll put off clean up
though of sh64 and at least set up a sensible default for everyone.
2015-04-18 04:14:38 -04:00
Mike Frysinger
c85fc61074 sim: microblaze: switch to common memory functions
Re-use the existing memory core that handles reads/writes.

This drops support for the dumpmem command, but gdb itself has
support for dumping memory regions.

The verbose command is converted to the common --verbose flag
since only two call sites use it now.

Support for the clearstats command is dropped entirely, but no
other sim really does this, and the same thing can be done by
reloading.  If it's important (clearing cycle stats) to someone,
we can add a common function for it.
2015-04-17 03:15:43 -04:00
Mike Frysinger
034685f9ce sim: replace CIA_{GET,SET} with CPU_PC_{GET,SET}
The CIA_{GET,SET} macros serve the same function as CPU_PC_{GET,SET}
except the latter adds a layer of indirection via the sim state.  This
lets models set up different functions at runtime and doesn't reach so
directly into the arch-specific cpu state.

It also doesn't make sense to have two sets of macros that do exactly
the same thing, so lets standardize on the one that gets us more.
2015-04-17 02:44:30 -04:00
Mike Frysinger
27b97b40bc sim: arm/cr16/d10v/h8300/microblaze/sh: fill out sim-cpu pc fetch/store helpers
This makes the common sim-cpu logic work.
2015-04-17 02:22:16 -04:00
Mike Frysinger
4c0cab1e21 sim: avr/mcore/moxie: fill out sim-cpu pc fetch/store helpers
This makes the common sim-cpu logic work.
2015-04-16 02:13:50 -04:00
Mike Frysinger
78e9aa70fe sim: unify sim-cpu usage
Now that all the targets are utilizing CPU_PC_{FETCH,STORE}, and the
cpu state is multicore, and the STATE_CPU defines match, we can move
it all to the common code.
2015-04-15 02:19:52 -04:00
Mike Frysinger
f95f4ed2c4 sim: cris/frv/h8300/iq2000/lm32/m32r/sh64: standardize cpu state
This sets up the sim_state structure and the cpu member to match what we
do in most other sims, and what the common code suggests.  This is a step
to unifying on the sim-cpu.o object.
2015-04-15 01:25:32 -04:00
Mike Frysinger
887bddbcad sim: ppc: fix up version script
The common sim code has switched to using gdb directly; update the
ppc copy too.
2015-04-13 23:17:53 -04:00
Mike Frysinger
bf12d44ee0 sim: fix the PKGVERSION define
This should be SIM, not GDB.
2015-04-13 02:41:10 -04:00
Mike Frysinger
a542beff94 sim: options: add --version support
The old run frontend had a --version option, but the new common
sim-options file does not.  Restore support for that so we can
get version info out of `run` when using the new frontend.
2015-04-13 02:35:26 -04:00
Mike Frysinger
8c32ba2233 sim: switch to gdb version script
Since the local create-version.sh already points directly into the gdb
source tree, we might as well use the gdb script directly too.
2015-04-13 02:32:58 -04:00
Mike Frysinger
64f14c9707 sim: mn10300: convert to sim-cpu
Make cpu allocation fully dynamic so we can leverage the common
sim-cpu and its APIs.
2015-04-13 02:13:48 -04:00
Mike Frysinger
14c9ad2edb sim: v850: convert to sim-cpu
Make cpu allocation fully dynamic so we can leverage the common
sim-cpu and its APIs.
2015-04-13 02:11:50 -04:00
Mike Frysinger
7bebb329bb sim: mips: convert to sim-cpu
Make cpu allocation fully dynamic so we can leverage the common
sim-cpu and its APIs.
2015-04-13 02:09:55 -04:00
Mike Frysinger
bea3f671c5 sim: m68hc11: convert to sim-cpu
Make cpu allocation fully dynamic so we can leverage the common
sim-cpu and its APIs.
2015-04-13 02:07:23 -04:00
Mike Frysinger
8ac57fbde4 sim: mips: fix prototype warnings
Convert a bunch of old style prototypes and tweak various casts
to match the function signatures.
2015-04-13 02:01:11 -04:00
Mike Frysinger
65f9096890 sim: ft32: fix ft32_pc_get logic 2015-04-13 01:54:33 -04:00
Hans-Peter Nilsson
a9d9677441 Do unset_currtarget_info ldscript for all simulator testsuites.
sim/testsuite:
	* sim-defs.exp (sim_init): Unset target ldscript here.

sim/testsuite/sim/mips:
	* basic.exp: Don't unset target ldscript here.
2015-04-13 01:56:04 +02:00
Mike Frysinger
e787f858a4 sim: arm/mips: fix sim_read/sim_write linkage errors
With sim-hrw.o being built & linked in the common list, some people are
getting linking errors now for these targets.  Move the main objects that
provide these functions before the common list to avoid that.
2015-04-12 05:47:39 -04:00
Mike Frysinger
29f1a5934a sim: ft32: delete sim_read/sim_write funcs
The common sim-hrw.o provides both of these, so simply use them.
2015-04-12 05:13:23 -04:00
Mike Frysinger
122bbfb52a sim: move sim-engine.o/sim-hrw.o to the common list
This makes these two objects available to all sims by default.
2015-04-06 23:56:47 -04:00
Mike Frysinger
20cc975360 sim: moxie: fix running after nrun conversion
The nrun conversion was slightly incorrect in how it stopped when an
exception occurred.  We still set cpu.asregs.exception, but nothing
was checking it anymore.  Convert all of that to sim_engine_halt.

To keep things from regressing again, add a basic testsuite too.
2015-04-05 04:37:44 -04:00
Mike Frysinger
024305f7f2 sim: mn10300: add a basic testsuite 2015-04-05 03:52:08 -04:00
Mike Frysinger
aad84fa6ae sim: m68hc11: add a basic testsuite 2015-04-05 03:17:44 -04:00
Mike Frysinger
eed64ce675 sim: iq2000: add a basic testsuite 2015-04-05 02:28:44 -04:00
Mike Frysinger
e56dbbb92f sim: lm32: add a basic testsuite 2015-04-05 01:58:00 -04:00
Mike Frysinger
b366059a5b sim: d10v: fix signal updates
Way back in aba6488e0b, a bunch of signal
defines were changed to TARGET_SIGNAL_xxx.  For d10v, the transition was
incomplete which lead to sim_stop_reason using the new set but sim_resume
still using the old set.  Which meant in some cases, the sim would never
actually stop.

Convert all the remaining SIGxxx defines in here to TARGET_SIGNAL_xxx.
This has the nice side effect of fixing the testsuite.
2015-04-02 20:40:11 -04:00
H.J. Lu
7fed4b0be6 Regenerate configure in sim
* arm/configure: Regenerated.
	* avr/configure: Likewise.
	* bfin/configure: Likewise.
	* common/configure: Likewise.
	* cr16/configure: Likewise.
	* cris/configure: Likewise.
	* d10v/configure: Likewise.
	* erc32/configure: Likewise.
	* frv/configure: Likewise.
	* ft32/configure: Likewise.
	* h8300/configure: Likewise.
	* igen/configure: Likewise.
	* iq2000/configure: Likewise.
	* lm32/configure: Likewise.
	* m32c/configure: Likewise.
	* m32r/configure: Likewise.
	* m68hc11/configure: Likewise.
	* mcore/configure: Likewise.
	* microblaze/configure: Likewise.
	* mips/configure: Likewise.
	* mn10300/configure: Likewise.
	* moxie/configure: Likewise.
	* msp430/configure: Likewise.
	* ppc/configure: Likewise.
	* rl78/configure: Likewise.
	* rx/configure: Likewise.
	* sh/configure: Likewise.
	* sh64/configure: Likewise.
	* v850/configure: Likewise.
2015-04-02 05:43:07 -07:00
Mike Frysinger
1a8faa2aa6 sim: clean up SIM_EXTRA_OBJS references
This variable was deleted in previous commits and is not used anymore.
Prune any stray references to it.
2015-04-02 00:51:40 -04:00
H.J. Lu
79730a3b26 Fix sim build
* common/Make-common.in (CSEARCH): Remove $(ZLIBINC).
	(BFD_LIB): Remove $(ZLIB).
	(CONFIG_LIBS): Add $(ZLIB).
	* ppc/Makefile.in (ZLIBINC): Removed.
	(INCLUDES): Remove $(ZLIBINC).
	(BFD_LIB): Remove $(ZLIB).
2015-04-01 10:27:43 -07:00
H.J. Lu
0ceaf1ec96 Regenerate configure in sim
* arm/configure: Regenerated.
	* avr/configure: Likewise.
	* bfin/configure: Likewise.
	* common/configure: Likewise.
	* cr16/configure: Likewise.
	* cris/configure: Likewise.
	* d10v/configure: Likewise.
	* erc32/configure: Likewise.
	* frv/configure: Likewise.
	* ft32/configure: Likewise.
	* h8300/configure: Likewise.
	* igen/configure: Likewise.
	* iq2000/configure: Likewise.
	* lm32/configure: Likewise.
	* m32c/configure: Likewise.
	* m32r/configure: Likewise.
	* m68hc11/configure: Likewise.
	* mcore/configure: Likewise.
	* microblaze/configure: Likewise.
	* mips/configure: Likewise.
	* mn10300/configure: Likewise.
	* moxie/configure: Likewise.
	* msp430/configure: Likewise.
	* ppc/configure: Likewise.
	* rl78/configure: Likewise.
	* rx/configure: Likewise.
	* sh/configure: Likewise.
	* sh64/configure: Likewise.
	* v850/configure: Likewise.
2015-04-01 10:15:13 -07:00
Mike Frysinger
269e9c185f sim: m32c: enable warnings & clean up a bunch
This doesn't clean up all the warnings, just most of them.
The ones that are left will require some care to unravel.
2015-04-01 02:22:58 -04:00
Mike Frysinger
0fe84f3fbe sim: run: punt!
Now that all targets have been converted to nrun, we can finally punt
this old inconsistent interface.

A few stray references to the old run were sprinkled about; clean them
up in the process.

We leave behind the run(1) man page mostly so that we get it updated for
the new nrun interface.
2015-04-01 01:22:44 -04:00
Mike Frysinger
aadc9410ba sim: update zlib handling
With zlib being mandatory, and the updated m4 configs, we need to regen
and use the new settings w/bfd to avoid linkage errors.
2015-04-01 01:07:57 -04:00
Mike Frysinger
b38f7f340b sim: cr16/d10v: restore generated headers dep
While cleaning up stale make rules, one too many were deleted.  The
build system autogenerates static rules, but not generated files.
2015-03-31 01:59:44 -04:00
Mike Frysinger
5a394431de common: cgen-mem/cgen-ops: fix extern inline handling
With newer versions of gcc (5.x), the extern inline we're using with the
cgen-{mem,ops} modules no longer work.  Since this code really wants the
gnu inline semantics, use that attribute explicitly.
2015-03-31 01:58:01 -04:00
Mike Frysinger
2b6ca06237 sim: m68hc11: fix gcc-5 build error w/restrict keyword 2015-03-31 01:54:47 -04:00
Mike Frysinger
49d62f8925 sim: arm: convert to nrun
A lot of cpu state is stored in global variables, as is memory handling.
The sim_size support needs unwinding at some point.  But at least this
is an improvement on the status quo.
2015-03-30 12:58:24 -04:00
Mike Frysinger
dbf8e8afcd sim: arm: delete NEED_UI_LOOP_HOOK handling 2015-03-30 12:58:23 -04:00
Mike Frysinger
58b991b14e sim: arm: clean up misc warnings
Also delete a few unused funcs.
2015-03-30 12:58:23 -04:00
Mike Frysinger
c4c9c44f57 sim: arm: use common configure options
In preparation for converting to nrun, call the common functions that
are needed.  This doesn't produce any new warnings, and the generated
code should be the same.
2015-03-30 12:58:23 -04:00
Mike Frysinger
457983e3a3 sim: arm: move COPRO settings to the makefile
These values are the same all the time, so just list them directly in
the Makefile.
2015-03-30 03:06:34 -04:00
Mike Frysinger
99956be1d7 sim: d10v: add missing sim-main.h 2015-03-30 03:06:33 -04:00
Mike Frysinger
541ebcee67 sim: d10v: convert to nrun
A lot of cpu state is stored in global variables, as is memory handling.
The sim_size support needs unwinding at some point.  But at least this
is an improvement on the status quo.
2015-03-30 02:20:23 -04:00
Mike Frysinger
a87686e5aa sim: d10v: delete NEED_UI_LOOP_HOOK handling
This hook is used only when linked into gdb, and d10v doesn't have a gdb
port anymore.  Punt it.
2015-03-30 02:20:23 -04:00
Mike Frysinger
11558abc20 sim: d10v: clean up misc warnings 2015-03-30 02:20:23 -04:00
Mike Frysinger
ef9535c6bc sim: d10v: use common configure options
In preparation for converting to nrun, call the common functions that
are needed.  This doesn't produce any new warnings, and the generated
code should be the same.
2015-03-30 02:20:23 -04:00
Mike Frysinger
e8713c0f02 sim: d10v: link in missing testsuite
Looks like historical restructuring in this dir lost the d10v-elf subdir
and no one noticed in the meantime.  Re-add it to the testsuite.

There are some failures, but better some tests get run than none at all.
2015-03-30 01:06:57 -04:00
Mike Frysinger
247ac9ee6e sim: cr16: convert to nrun
A lot of cpu state is stored in global variables, as is memory handling.
The sim_size support needs unwinding at some point.  But at least this
is an improvement on the status quo.
2015-03-30 00:13:38 -04:00
Mike Frysinger
4b0cc5edf4 sim: cr16: delete NEED_UI_LOOP_HOOK handling
This hook is used only when linked into gdb, and cr16 doesn't have a gdb
port anymore.  Punt it.
2015-03-30 00:10:27 -04:00
Mike Frysinger
1e504675bd sim: cr16: delete dead code
This code is getting in the way of porting to nrun, so just drop it.
If anyone actually cares about this cpu, they can revive it.
2015-03-30 00:08:46 -04:00
Mike Frysinger
5aedb83b9c sim: cr16: clean up misc warnings 2015-03-29 22:41:14 -04:00
Mike Frysinger
ca968da465 sim: cr16: use common configure options
In preparation for converting to nrun, call the common functions that
are needed.  This doesn't produce any new warnings, and the generated
code should be the same.
2015-03-29 22:42:33 -04:00
Mike Frysinger
4daf7a7c3a sim: cr16: add _start symbol to tests [BZ #12385]
The current cr16 testsuite sets up _START, but the linker looks for the
_start symbol.  Add the latter as an alias to the former.
2015-03-29 21:02:03 -04:00
Mike Frysinger
2b4bc832a7 sim: microblaze: convert to nrun
This port already was storing its cpu state in the sim_cpu structure, so
converting it over was pretty easy.  It is allocating memory itself still,
but we'll fix that up in the future at some point.
2015-03-29 17:40:30 -04:00
Mike Frysinger
97eca187b3 sim: mcore/microblaze: delete dead code
The mcore port had a few structs/defines that were never used.

Similarly, the microblaze port, because it was copied from mcore, has
that same dead code, and more.  The watchpoint logic was never actually
used.  Punt it all.
2015-03-29 17:25:53 -04:00
Mike Frysinger
191ec03314 sim: microblaze: start a testsuite
Since the sim doesn't have any debug support in it, we can only exit
cleanly.  But this is still better than nothing.

Change the default microblaze sim to not dump the debug load output
when running.  No other does this, and it breaks the testsuite.
2015-03-29 16:45:49 -04:00
Mike Frysinger
744b9a190b sim; testsuite: allow tests to set no output
If a test doesn't write anything at all to stdout, the current test
framework can't support that.  Even if you put a blank output line:
	# output:
the setup happily clobbers that with a default pass/fail string.

Tweak the parsing logic so we only set the output to pass/fail when
the test has no output marker.
2015-03-29 16:41:59 -04:00
Mike Frysinger
92fc6153a6 sim: common: sim-arange: fix extern inline handling
With newer versions of gcc (5.x), the extern inline we're using with the
sim-arange module no longer works.  Since this code really wants the gnu
inline semantics, use that attribute explicitly.

Reported-by: DJ Delorie <dj@redhat.com>
Reported-by: Joel Sherrill <joel.sherrill@oarcorp.com>
2015-03-29 16:02:17 -04:00
Mike Frysinger
6dae8a88bf sim: testsuite: make subdir unconditional
Since the testsuite subdir has to handle dynamic arch values already,
there's no real value in requiring arches to opt in to it.  Most have
a testsuite now anyways, and we're requiring it in the future.
2015-03-29 11:51:13 -04:00
Mike Frysinger
3c0ae30962 sim: microblaze: use common configure options
In preparation for converting to nrun, call the common functions that
are needed.  This doesn't produce any new warnings, and the generated
code should be the same.
2015-03-29 11:51:13 -04:00
Mike Frysinger
ea6b7543b4 sim: mcore: convert to nrun
A lot of cpu state is stored in global variables, as is memory handling.
The sim_size support needs unwinding at some point.  But at least this
is an improvement on the status quo.
2015-03-29 04:14:27 -04:00
Mike Frysinger
525887679c sim: mcore: use common configure options
In preparation for converting to nrun, call the common functions that
are needed.  This doesn't produce any new warnings, and the generated
code should be the same.
2015-03-29 04:14:27 -04:00
Mike Frysinger
36cb69e0ed sim: mcore: add a basic testsuite 2015-03-29 04:14:27 -04:00
Mike Frysinger
aac18a6996 sim: mcore: drop sbrk support
The sbrk syscall assumes the sbrk region starts after the bss and the
current implementation requires a bss section to exist.  Since there
is no requirement for programs to have a bss in general, we want to
drop this check.  However, there is still the sbrk syscall that wants
to know about the region.

Since libgloss doesn't actually use the sbrk syscall (it implements
sbrk in its own way), and the sim really shouldn't enforce a specific
memory layout on programs, lets simply delete sbrk support.  Now it
always returns an error.
2015-03-29 04:14:27 -04:00
Mike Frysinger
4f5cce88bf sim: avr: fix _start testsuite symbol
Make sure we use the symbol the linker expects by default, and we export
it so it can be found.
2015-03-29 04:14:27 -04:00
Mike Frysinger
62454d3da2 sim: sh: convert to nrun
A lot of cpu state is stored in global variables, as is memory handling.
The sim_size support needs unwinding at some point.  But at least this
is an improvement on the status quo.
2015-03-28 17:45:31 -04:00
Mike Frysinger
5fa71a1b13 sim: sh: clean up some warnings
Mostly converting old style prototypes.  Also include a few missing
headers, and add static/casts where appropriate.
2015-03-28 17:45:31 -04:00
Mike Frysinger
02131c7ff6 sim: sh: fix broken handling in DSR reg
A missing */ caused a case statement to be incorrect masked out which
also hide an error where the wrong value was being checked.  Fix both.
2015-03-28 17:45:30 -04:00
Mike Frysinger
ed4d32c28a sim: sh: clean up gencode
The build line was missing the normal BUILD_xxx flags.  Once we added
that, we get warnings that weren't shown before.  As we fix those, we
notice that the -d option segfaults because it tries to write readonly
memory.  Fix that too as part of the const/prototype clean up.
2015-03-28 17:45:30 -04:00
Mike Frysinger
6d89786cb3 sim: sh: use common configure options
In preparation for converting to nrun, call the common functions that
are needed.  This also produces a bunch of warnings, but one thing at
a time.
2015-03-28 17:45:30 -04:00
Mike Frysinger
9943d3185a sim: avr: convert to nrun.o
Looks like a lot more work than actually was -- the main decode loop
was de-indented by dropping the loop as a step-once function.
2015-03-28 05:35:29 -04:00
Mike Frysinger
eca5fe422e sim: avr: start a basic testsuite
Just enough to know the sim isn't totally broken.
2015-03-28 04:28:46 -04:00
Jiri Gaisler
510d27512c sim/erc32: Fix a few compiler warnings 2015-03-28 03:05:35 -04:00
Jiri Gaisler
102b920e11 sim/erc32: Use memory_iread() function for instruction fetching.
Use separate memory_iread() function for instruction fetching.
Speeds up execution and allows addition of an MMU at a later stage.
2015-03-28 03:00:19 -04:00
Mike Frysinger
5831e29bc1 sim: erc32: strip paren from return statements 2015-03-28 02:57:08 -04:00
James Bowman
f46e4eb78b sim: ft32: new port
FT32 is a new high performance 32-bit RISC core developed by FTDI for
embedded applications.
2015-03-28 02:12:33 -04:00
Mike Frysinger
05f53ed611 sim: m68hc11/mips/mn10300/v850: add basic sim_pc_get
The previous profile change broke these sims that use sim-profile but
not sim-cpu (due to missing model support).  Add simple funcs until we
can convert these over properly.
2015-03-24 02:43:42 -04:00
Mike Frysinger
596f88276c sim: profile: disconnect from watchpoint core
The profile code was using STATE_WATCHPOINTS to get access to the PC, but
we already have a standard method for getting the pc, so switch to that.

This assumes that sizeof_pc is the same size as sim_cia, but we already
assume this in places by way of sim_pc_{get,set}, and this is how it's
documented in the sim-base.h API.
2015-03-24 01:24:10 -04:00
Mike Frysinger
1bf57e9a2e sim: moxie: clean up build time warnings 2015-03-24 01:14:28 -04:00
Mike Frysinger
cc8ab1ded5 sim: moxie: convert to nrun.o
This port already used a lot of common/ files, so cutting it over to
nrun.o and using a few more common objects is pretty straight forward.
2015-03-24 01:08:56 -04:00