darkkirb/old-cross-binutils
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278 commits

Author SHA1 Message Date
Jeff Law
18c97701b4 * v850-opc.c (v850_opcodes): Fix opcode numbers for "mov" 
with immediate operand, "movhi".  Tweak "ldsr".
More fixes.
 1996-08-23 20:27:25 +00:00
Jeff Law
fb6da8680e * v850-opc.c (v850_opcodes): Get ld.[bhw] and st.[bhw] 
correct.  Get sld.[bhw] and sst.[bhw] closer.
 1996-08-23 19:32:41 +00:00
Jeff Law
38c7a4504d * v850-opc.c (v850_operands): "not" is a two byte insn. 1996-08-23 19:12:05 +00:00
Jeff Law
6c1fc4d3fa * v850-opc.c (v850_opcodes): Correct bit pattern for setf. 1996-08-23 18:58:57 +00:00
Jeff Law
9ab069eadc * v850-opc.c (v850_operands): D16 inserts at offset 16! 1996-08-23 18:27:43 +00:00
Jeff Law
b1e897a97d * v850-opc.c (two): Get order of words correct. 1996-08-23 18:17:31 +00:00
Jeff Law
9ad8ddf1bd * v850-opc.c (v850_operands): I16 inserts at offset 16! 
Should get immediate 16bit operands into the right place
 1996-08-23 17:52:00 +00:00
Jeff Law
e41c99bd11 * v850-opc.c (v850_operands): Add "SR1" and "SR2" for system 
register source and destination operands.
        (v850_opcodes): Use SR1 and SR2 for "ldsr" and "stsr".
More parsing fixes.
 1996-08-23 17:35:11 +00:00
Jeff Law
c262d7d8f4 * v850-opc.c (v850_opcodes): Fix thinko in "jmp" opcode. Fix 
same thinko in "trap" opcode.
 1996-08-23 17:09:28 +00:00
Jeff Law
85b5201342 * v850-opc.c (v850_opcodes): Fix thinko in "jmp" opcode. 1996-08-23 17:07:21 +00:00
Jeff Law
280d40df39 * v850-opc.c (v850_opcodes): Add initializer for size field 
on all opcodes.
 1996-08-23 16:40:15 +00:00
Jeff Law
4be84c4951 * v850-opc.c (v850_operands): D6 -> DS7. References changed. 
Add D8 for 8-bit unsigned field in short load/store insns.
        (IF4A, IF4D): These both need two registers.
        (IF4C, IF4D): Define.  Use 8-bit unsigned field.
        (v850_opcodes): For "sld.h", "sld.w", "sst.h", "sst.w", use
        IF4C & IF4D.  For "trap" use I5U, not I5.  Add IF1 operand
        for "ldsr" and "stsr".
        * v850-opc.c (v850_operands): 3-bit immediate for bit insns
        is unsigned.
Fixing up the parser again.
 1996-08-23 15:41:30 +00:00
Jeff Law
3c72ab7035 * v850-opc.c (v850_operansd): 3-bit immediate for bit insns 
is unsigned.
 1996-08-23 06:56:44 +00:00
Jeff Law
cc6e50b5b2 * v850-opc.c (v850_opcodes): Correct short store half (sst.h) and 
short store word (sst.w).
 1996-08-23 06:27:37 +00:00
J.T. Conklin
69463cbb2b * v850-opc.c (v850_operands): Added insert and extract fields, 
pointers to functions that handle unusual operand encodings.
 1996-08-23 00:00:18 +00:00
Jeff Law
9c201b1fab * v850-opc.c (v850_opcodes): Enable "trap". 1996-08-22 23:08:03 +00:00
Jeff Law
0bdf3144c6 * v850-opc.c (v850_opcodes): Fix order of displacement 
and register for "set1", "clr1", "not1", and "tst1".
 1996-08-22 07:06:13 +00:00
Jeff Law
7c8157dd48 * v850-opc.c (v850_operands): Add "B3" support. 
(v850_opcodes): Fix and enable "set1", "clr1", "not1"
        and "tst1".
 1996-08-22 02:08:02 +00:00
Jeff Law
fed1d21fc0 * v850-ope.c ("jmp"): R1 is only operand. 1996-08-22 01:39:22 +00:00
Jeff Law
b10e29f4b8 * v850-opc.c: Close unterminated comment. 
Something -Wall caught.
 1996-08-22 00:46:47 +00:00
J.T. Conklin
6bc33c7fa5 * v850-opc.c: Add flags field to struct v850_operands, add move 
opcodes to opcode table.
 1996-08-22 00:35:28 +00:00
J.T. Conklin
6d1e1ee875 * Makefile.in (ALL_MACHINES): Add v850-opc.o. 
* configure: (bfd_v850v_arch) Add new case.
* configure.in: (bfd_v850_arch) Add new case.
* v850-opc.c: New file.
 1996-08-20 21:45:02 +00:00
David Edelsohn
5751b0d72d * sparc-dis.c (print_insn_sparc): Handle little endian sparcs. 1996-08-19 22:22:11 +00:00
Stan Shebs
a952ea1cb8 * mpw-make.sed: Update editing of include pathnames to be 
more general.
 1996-08-15 20:13:38 +00:00
Ian Lance Taylor
375d76efcc Wed Aug 14 17:00:04 1996 Richard Henderson <rth@tamu.edu> 
* alpha-opc.c (EV4EXTHWINDEX): Field width should be 8 not 5.
 1996-08-15 00:01:21 +00:00
Martin Hunt
ed36b6cd33 Mon Aug 12 14:30:37 1996 Martin M. Hunt <hunt@pizza.cygnus.com> 
* d10v-opc.c (d10v_opcodes): Minor fixes to addi and bl.l.
 1996-08-12 21:32:03 +00:00
Martin Hunt
cff827d7df Fri Aug 9 13:21:59 1996 Martin M. Hunt <hunt@pizza.cygnus.com> 
* d10v-opc.c (d10v_opcodes): Correct 'mv' unit entry to EITHER.
 1996-08-09 20:25:12 +00:00
Ian Lance Taylor
0f38eaa09f Thu Aug 8 12:43:52 1996 Klaus Kaempf <kkaempf@progis.de> 
* makefile.vms: Update for alpha-opc changes.
 1996-08-08 16:45:05 +00:00
Ian Lance Taylor
484c464505 * i386-dis.c (print_insn_i386): Actually return the correct value. 
(ONE, OP_ONE): #ifdef out; not used.
 1996-08-07 15:56:13 +00:00
Martin Hunt
c5e1996f55 Fri Aug 2 17:47:03 1996 Martin M. Hunt <hunt@pizza.cygnus.com> 
* d10v-opc.c (d10v_operands): Added 2 accumulator sub instructions.
	Changed subi operand type to treat 0 as 16.
 1996-08-03 00:49:00 +00:00
Ian Lance Taylor
82e8213e4e * m68k-opc.c: Add cpushl for the mcf5200. From Ken Rose 
<rose@netcom.com>.
 1996-07-31 20:22:50 +00:00
Jackie Smith Cashion
50569deeb5 Wed Jul 31 14:39:27 1996 James G. Smith <jsmith@cygnus.co.uk> 
* arm-opc.h: (arm_opcodes): Added halfword and sign-extension
 	memory transfer instructions. Add new format string entries %h and %s.
	* arm-dis.c: (print_insn_arm): Provide decoding of the new
	formats %h and %s.
 1996-07-31 13:43:51 +00:00
Martin Hunt
3dd5a8d337 Fri Jul 26 11:45:04 1996 Martin M. Hunt <hunt@pizza.cygnus.com> 
* d10v-opc.c (d10v_operands): Added UNUM4S; a 4-bit accumulator shift.
 	(d10v_opcodes): Modified accumulator shift instructions to use UNUM4S.
 1996-07-26 18:59:21 +00:00
Ian Lance Taylor
239ce44d9c * alpha-dis.c (print_insn_alpha_osf): Remove. 
(print_insn_alpha_vms): Remove.
	(print_insn_alpha): Make globally visible.  Chose the register
	names based on info->flavour.
	* disassemble.c: Always return print_insn_alpha for the alpha.
 1996-07-26 18:06:35 +00:00
Martin Hunt
ab0a229408 Thu Jul 25 15:24:17 1996 Martin M. Hunt <hunt@pizza.cygnus.com> 
* d10v-dis.c (dis_long): Handle unknown opcodes.
 1996-07-25 22:28:10 +00:00
Martin Hunt
0be715623f Thu Jul 25 12:08:09 1996 Martin M. Hunt <hunt@pizza.cygnus.com> 
* d10v-opc.c: Changes to support signed and unsigned numbers.
	All instructions with the same name that have long and short forms
	now end in ".l" or ".s".  Divs added.
	* d10v-dis.c: Changes to support signed and unsigned numbers.
 1996-07-25 19:16:34 +00:00
Martin Hunt
687c3cc863 start-sanitize-d10v 
Tue Jul 23 11:02:53 1996  Martin M. Hunt  <hunt@pizza.cygnus.com>

	* d10v-dis.c: Change all functions to use info->print_address_func.

end-sanitize-d10v
 1996-07-23 18:11:55 +00:00
Ian Lance Taylor
354447a435 Mon Jul 22 15:38:53 1996 Andreas Schwab <schwab@issan.informatik.uni-dortmund.de> 
* m68k-opc.c (m68k_opcodes): Make opcode masks for the ColdFire
 	move ccr/sr insns more strict so that the disassembler only
 	selects them when the addressing mode is data register.
 1996-07-22 19:49:24 +00:00
Martin Hunt
95e3e73328 start-sanitize-d10v 
Mon Jul 22 11:25:24 1996  Martin M. Hunt  <hunt@pizza.cygnus.com>
        * d10v-opc.c (pre_defined_registers):  Declare.
        * d10v-dis.c (print_operand): Now uses pre_defined_registers
        to pick a better name for the registers.

end-sanitize-d10v
 1996-07-22 18:57:20 +00:00
Ian Lance Taylor
e4024966b2 * sparc-opc.c: Fix opcode values for fpack16, and fpackfix. Fix 
operands for fexpand and fpmerge.  From Christian Kuehnke
	<Christian.Kuehnke@arbi.informatik.uni-oldenburg.de>.
 1996-07-22 17:58:19 +00:00
Ian Lance Taylor
e7bc7bc3fc Mon Jul 22 13:17:06 1996 Richard Henderson <rth@tamu.edu> 
* alpha-dis.c (print_insn_alpha): No longer the user-visible
	print routine.  Take new regnames and cpumask arguments.
	Kill the environment variable nonsense.
	(print_insn_alpha_osf): New function.  Do OSF/1 style regnames.
	(print_insn_alpha_vms): New function.  Do VMS style regnames.
	* disassemble.c (disassembler): Test bfd flavour to pick
	between OSF and VMS routines.  Default to OSF.
 1996-07-22 17:19:09 +00:00
Ian Lance Taylor
8ec904659e * configure.in: Call AC_SUBST (INSTALL_SHLIB). 
* configure: Rebuild.
	* Makefile.in (install): Use @INSTALL_SHLIB@.
 1996-07-18 21:20:15 +00:00
Martin Hunt
e3659cbf49 start-sanitize-d10v 
Wed Jul 17 14:39:05 1996  Martin M. Hunt  <hunt@pizza.cygnus.com>
        * configure: (bfd_d10v_arch) Add new case.
        * configure.in: (bfd_d10v_arch) Add new case.
        * d10v-dis.c: New file.
        * d10v-opc.c: New file.
        * disassemble.c (disassembler) Add entry for d10v.
end-sanitize-d10v
 1996-07-18 00:49:26 +00:00
J.T. Conklin
dec678d6ca Wed Jul 17 10:12:05 1996 J.T. Conklin <jtc@rtl.cygnus.com> 
* m68k-opc.c (m68k_opcodes): Fix bugs in coldfire insns relating
        to bcc, trapfl, subxl, and wddata discovered by Andreas Schwab.
 1996-07-17 17:18:13 +00:00
Stu Grossman
9498be1a05 oops! 1996-07-16 00:03:38 +00:00
Stu Grossman
be0c8b0508 * i386-dis.c (print_insn_i8086): New routine to disassemble using 
the 8086 instruction set.
	* i386-dis.c:  General cleanups.  Make most things static.  Add
	prototypes.  Get rid of static variables aflags and dflags.  Pass
	them as args (to almost everything).
 1996-07-12 17:15:38 +00:00
Jeff Law
3b2a7894d8 * h8300-dis.c (bfd_h8_disassemble): Handle macregs in ldmac insns. 
More HMSE.
 1996-07-11 19:06:21 +00:00
Jeff Law
8e9c1f74c9 * h8300-dis.c (bfd_h8_disassemble): Handle "ldm.l" and "stm.l". 
More disassembler fixes.  HMSE.
 1996-07-11 18:59:57 +00:00
Jeff Law
52aa53362e * h8300-dis.c (bfd_h8_disassemble): "abs" is implicitly two 
if the next arg is marked with SRC_IN_DST.  Gross.
Gross hack so that shift-by-two insns are disassembled correctly.
 1996-07-11 18:46:41 +00:00
Jeff Law
b3ef936e6b * h8300-dis.c (bfd_h8_disassemble): Print "exr" when 
we're looking for and find EXR.
So we disassemble andc/orc/xorc with exr correctly.
 1996-07-11 18:30:02 +00:00