(opcode_bits, opcode_hash_table, sparc64_p): New variables.
(opcodes_initialized): Renamed from opcodes_sorted.
(build_hash_table): New function.
(is_delayed_branch): Use hash table.
(print_insn): Renamed from print_insn_sparc, made static.
Build and use hash table.
(print_insn_sparc, print_insn_sparc64): New functions.
(compare_opcodes): If !sparc64, move sparc64 opcodes to end,
and vice-versa if sparc64.
* sparc-opc.c (all non-v9 insns): Use flag F_NOTV9 instead of F_ALIAS.
* mips-opc.c (L1): Define.
(mips_opcodes): Add R4010 instructions: flushi, flushd, flushid,
addciu, madd, maddu, ffc, ffs, msub, msubu, selsi, selsr, waiti,
and wb.
Tue Jul 11 11:49:49 1995 Ian Lance Taylor <ian@cygnus.com>
* mips-opc.c (mips_opcodes): For the move pseudo-op, prefer daddu
if ISA 3 and addu otherwise, replacing or, since some MIPS chips
have multiple add units but only a single logical unit.
bfd_vma to unsigned long, because _print_insn_mips expects an unsigned long,
and that might be fewer words of argument storage (e.g., if bfd_vma is long
long on a 32-bit machine).
(print_insn_big_mips): Likewise with bfd_getb32 value.
(_print_insn_mips): Now static.
Call arc_get_opcode_mach to map bfd mach number to opcode value.
(print_insn_*): Pass bfd mach number, not opcode version.
* arc-opc.c (arc_get_opcode_mach): New function.
* alpha-opc.h (OSF_ASMCODE): define print pal-code names as defined in App C of
the Alpha Architecture Reference Manual
* alpha-dis.c: cleaned up output print stylized code forms as defined in App
A.4.3 of the Alpha Architecture Reference Manual
(print_insn_arc_{host,graphics,audio}): Likewise.
(print_insn): Add prototype.
Delete "+ 4" addition to relative branch address.
(arc_get_disassembler): New arg `big_p'. Return little or big
print fn accordingly.
* arc-opc.c (arc_opcode_init_tables): Init arc_operand_map once.
(arc_opcode_supported): Use ARC_OPCODE_CPU to ignore byte order.
(arc_opval_supported): Likewise.
* disassemble.c (disassembler): Pass big endian flag to
arc_get_disassembler.
(UNSIGNED, SATURATION): New operands.
(mac, mul, mul64, mulu64): New insns.
(ext. asl, asr, lsr, ror): Only available on host and graphics cpus.
(padc, padd, pmov, pand, psbc, psub, swap): New insns.
(host,graphics,audio extended and auxiliary regs): Define.
(ss, sc, mh, ml): New suffixes.
(arc_opcode_supported, arc_opval_supported): New functions.
(insert_multshift, extract_multshift): Deleted.
New argument `cpu', pass it to arc_opcode_init_tables.
Document byte order dependencies. Ignore unsupported insns.
(arc_disassembler): New function.
(print_insn_arc_base, print_insn_arc_host, print_insn_arc_graphics,
print_insn_arc_audio): New functions.
<edelsohn@npac.syr.edu>.
(powerpc_operands): Add operands SPRBAT and SPRG. Split TBR out of
SPR.
(FXM_MASK): Define.
(insert_tbr): New static function.
(extract_tbr): New static function.
(XFXFXM_MASK, XFXM): Define.
(XSPRBAT_MASK, XSPRG_MASK): Define.
(powerpc_opcodes): Add instructions to access special registers by
name. Add mtcr and mftbu.
All uses changed.
(extraction fns): Insn argument now array of two words. Return pointer
to value's table entry. All uses changed.
(arc_opcode_lookup_suffix): Exported for arc-dis.c.
(insert_multshift, extract_multshift): New fns.
(arc_operands): Add support for cache bypass suffix. Add support for
predefined aux regs. Modifier bits moved to flags field.
(arc_opcodes): Likewise.
Add mul/mulu/shift insns. Syntax of zero/sign extension insns changed.
New insn rlc. Update to syntax in programmer's manual.
(arc_reg_names): Fix typo in lp_count. Add predefined aux regs.
(arc_suffixes): New synonyms lo,hs for cs,cc. New suffix for cache
bypass.
(arc_opcode_init_tables): New argument to indicate cpu type.
(insert_reg): Handle predefined aux regs.
(extract_reg): Likewise.
(lookup_register): New fn.
* arc-dis.c (arc_condition_codes): Deleted.
(print_insn_arc): Handle insns with 32 bit immediate constants better.
Clean up modifier handling. Handle predefined aux regs.
* ns32k-dis.c: Deleted all code in "#ifdef GDB".
(invalid_float): Enabled general version, doesn't require running
on ns32k host.
Sun Jul 10 00:27:47 1994 Ian Dall (dall@hfrd.dsto.gov.au)
* opcodes/ns32k-dis.c: Semi-new file. Had apparently been dropped
from distribution. A ns32k-dis.c from a previous distribution has
been brought up to date and supports the new interface.
* disaaemble.c: define ARCH_ns32k and add case bfd_arch_ns32k.
* configure.in: add bfd_ns32k_arch target support.
* Makefile.in: add ns32k-dis.o to ALL_MACHINES.
Add ns32k-dis.c to CFILES. Add dependencies for ns32k-dis.o.
removed, so don't initialize it. Set the PPC_OPERAND_SIGNED flag
instead. Add new operand SISIGNOPT.
(powerpc_opcodes): For lis, liu, addis, and cau use SISIGNOPT.
Based on patch from David Edelsohn (edelsohn@npac.syr.edu).
* ppc-dis.c (print_insn_powerpc): Check PPC_OPERAND_SIGNED rather
than signedp field.
(print_insn_m68k): If an instruction uses place 'i', it uses at
least four fixed bytes.
(print_insn_arg): Don't bump p by 2 for case 'I', place 'i'. For
extended float, convert to double using floatformat_to_double, not
ieee_extended_to_double, and fetch the data before converting it.
Floating point format for 'H' operand is backwards from normal
case (0 == double, 1 == single). For '4', '6', '7', '9', and '8'
operands (fmpyadd and fmpysub), handle bizarre register translation
correctly for single precision format.
single number giving a bitmask for the MB and ME fields of an M
form instruction. Change NB to accept 32, and turn it into 0;
also turn 0 into 32 when disassembling. Seperated SH from NB.
(insert_mbe, extract_mbe): New functions.
(insert_nb, extract_nb): New functions.
(SC_MASK): Mask out SA and LK bits.
(powerpc_opcodes): Change "cal" to use RT, D, RA rather than RT,
RA, SI. Change "liu" and "cau" to use UI rather than SI. Mark
"bctr" and "bctrl" as accepted by POWER. Change "rlwimi",
"rlimi", "rlwimi.", "rlimi.", "rlwinm", "rlinm", "rlwinm.",
"rlinm.", "rlmi", "rlmi.", "rlwnm", "rlnm", "rlwnm.", "rlnm." to
use MBE rather than MB. Add "mfmq" and "mtmq" POWER instructions.
(powerpc_macros): Define table of macro definitions.
(powerpc_num_macros): Define.
opcodes for POWER (RS/6000).
* ppc-dis.c: New file. PowerPC and Power (RS/6000) disassembler.
* Makefile.in (ALL_MACHINES): Add ppc-dis.o and ppc-opc.o.
(CFILES): Add ppc-dis.c.
(ppc-dis.o, ppc-opc.o): New targets.
* configure.in: Build ppc-dis.o and ppc-opc.o for bfd_rs6000_arch.
* mpw-config.in: New file, MPW version of configure.in.
* mpw-make.in: New file, MPW version of Makefile.in.
Mon Jan 3 12:54:35 1994 Stan Shebs (shebs@andros.cygnus.com)
* mpw-xconfig.in: New file, mpw x mips configuration bits.
than s,t. Change div macro to be d,v,t rather than d,s,t.
Likewise for divu, ddiv, ddivu. Added z,s,t case for drem, dremu,
rem and remu which generates only the corresponding div
instruction. This is for compatibility with the MIPS assembler,
which only generates the simple machine instruction when an
explicit destination of $0 is used.
* mips-dis.c (print_insn_arg): Handle 'z' (always register zero).
Change d,s,t form to d,v,t. Likewise for divu, ddiv and ddivu.
This is for compatibility with the MIPS assembler, which only
generates the simple machine instruction when an explicit
destination of $0 is used.
