* ppc-opc.c: Changes based on patch from David Edelsohn
<edelsohn@npac.syr.edu>. (powerpc_operands): Add operands SPRBAT and SPRG. Split TBR out of SPR. (FXM_MASK): Define. (insert_tbr): New static function. (extract_tbr): New static function. (XFXFXM_MASK, XFXM): Define. (XSPRBAT_MASK, XSPRG_MASK): Define. (powerpc_opcodes): Add instructions to access special registers by name. Add mtcr and mftbu.
This commit is contained in:
Ian Lance Taylor
parent
4b412ed189
commit
669124ef4f
2 changed files with 229 additions and 41 deletions
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@ -1,3 +1,22 @@
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Thu Jan 26 18:32:08 1995 Ian Lance Taylor <ian@cygnus.com>
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* ppc-opc.c: Changes based on patch from David Edelsohn
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<edelsohn@npac.syr.edu>.
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(powerpc_operands): Add operands SPRBAT and SPRG. Split TBR out of
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SPR.
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(FXM_MASK): Define.
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(insert_tbr): New static function.
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(extract_tbr): New static function.
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(XFXFXM_MASK, XFXM): Define.
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(XSPRBAT_MASK, XSPRG_MASK): Define.
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(powerpc_opcodes): Add instructions to access special registers by
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name. Add mtcr and mftbu.
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Tue Jan 17 10:56:43 1995 Ian Lance Taylor <ian@sanguine.cygnus.com>
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* mips-opc.c (P3): Define.
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(mips_opcodes): Add mad and madu.
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Sun Jan 15 16:32:59 1995 Steve Chamberlain <sac@splat>
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* configure.in: Add W65 support.
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@ -63,12 +63,17 @@ static unsigned long insert_nb PARAMS ((unsigned long, long, const char **));
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static long extract_nb PARAMS ((unsigned long, int *));
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static unsigned long insert_nsi PARAMS ((unsigned long, long, const char **));
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static long extract_nsi PARAMS ((unsigned long, int *));
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static unsigned long insert_ral PARAMS ((unsigned long, long, const char **));
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static unsigned long insert_ram PARAMS ((unsigned long, long, const char **));
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static unsigned long insert_ras PARAMS ((unsigned long, long, const char **));
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static unsigned long insert_rbs PARAMS ((unsigned long, long, const char **));
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static long extract_rbs PARAMS ((unsigned long, int *));
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static unsigned long insert_sh6 PARAMS ((unsigned long, long, const char **));
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static long extract_sh6 PARAMS ((unsigned long, int *));
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static unsigned long insert_spr PARAMS ((unsigned long, long, const char **));
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static long extract_spr PARAMS ((unsigned long, int *));
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static unsigned long insert_tbr PARAMS ((unsigned long, long, const char **));
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static long extract_tbr PARAMS ((unsigned long, int *));
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/* The operands table.
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@ -221,6 +226,7 @@ const struct powerpc_operand powerpc_operands[] =
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/* The FXM field in an XFX instruction. */
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#define FXM (FRS + 1)
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#define FXM_MASK (0xff << 12)
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{ 8, 12, 0, 0, 0 },
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/* The L field in a D or X form instruction. */
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@ -282,8 +288,25 @@ const struct powerpc_operand powerpc_operands[] =
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#define RA_MASK (0x1f << 16)
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{ 5, 16, 0, 0, PPC_OPERAND_GPR },
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/* The RA field in a D or X form instruction which is an updating
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load, which means that the RA field may not be zero and may not
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equal the RT field. */
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#define RAL (RA + 1)
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{ 5, 16, insert_ral, 0, PPC_OPERAND_GPR },
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/* The RA field in an lmw instruction, which has special value
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restrictions. */
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#define RAM (RAL + 1)
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{ 5, 16, insert_ram, 0, PPC_OPERAND_GPR },
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/* The RA field in a D or X form instruction which is an updating
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store or an updating floating point load, which means that the RA
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field may not be zero. */
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#define RAS (RAM + 1)
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{ 5, 16, insert_ras, 0, PPC_OPERAND_GPR },
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/* The RB field in an X, XO, M, or MDS form instruction. */
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#define RB (RA + 1)
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#define RB (RAS + 1)
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#define RB_MASK (0x1f << 11)
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{ 5, 11, 0, 0, PPC_OPERAND_GPR },
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@ -320,24 +343,37 @@ const struct powerpc_operand powerpc_operands[] =
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#define SISIGNOPT (SI + 1)
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{ 16, 0, 0, 0, PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
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/* The SPR or TBR field in an XFX form instruction. This is
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flipped--the lower 5 bits are stored in the upper 5 and vice-
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versa. */
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/* The SPR field in an XFX form instruction. This is flipped--the
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lower 5 bits are stored in the upper 5 and vice- versa. */
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#define SPR (SISIGNOPT + 1)
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#define TBR (SPR)
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#define SPR_MASK (0x3ff << 11)
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{ 10, 11, insert_spr, extract_spr, 0 },
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/* The BAT index number in an XFX form m[ft]ibat[lu] instruction. */
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#define SPRBAT (SPR + 1)
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#define SPRBAT_MASK (0x3 << 17)
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{ 2, 17, 0, 0, 0 },
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/* The SPRG register number in an XFX form m[ft]sprg instruction. */
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#define SPRG (SPRBAT + 1)
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#define SPRG_MASK (0x3 << 16)
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{ 2, 16, 0, 0, 0 },
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/* The SR field in an X form instruction. */
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#define SR (SPR + 1)
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#define SR (SPRG + 1)
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{ 4, 16, 0, 0, 0 },
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/* The SV field in a POWER SC form instruction. */
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#define SV (SR + 1)
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{ 14, 2, 0, 0, 0 },
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/* The TBR field in an XFX form instruction. This is like the SPR
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field, but it is optional. */
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#define TBR (SV + 1)
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{ 10, 11, insert_tbr, extract_tbr, PPC_OPERAND_OPTIONAL },
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/* The TO field in a D or X form instruction. */
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#define TO (SV + 1)
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#define TO (TBR + 1)
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#define TO_MASK (0x1f << 21)
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{ 5, 21, 0, 0, 0 },
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@ -808,6 +844,51 @@ extract_nsi (insn, invalid)
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return - (insn & 0xffff);
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}
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/* The RA field in a D or X form instruction which is an updating
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load, which means that the RA field may not be zero and may not
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equal the RT field. */
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static unsigned long
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insert_ral (insn, value, errmsg)
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unsigned long insn;
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long value;
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const char **errmsg;
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{
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if (value == 0
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|| value == ((insn >> 21) & 0x1f))
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*errmsg = "invalid register operand when updating";
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return insn | ((value & 0x1f) << 16);
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}
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/* The RA field in an lmw instruction, which has special value
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restrictions. */
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static unsigned long
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insert_ram (insn, value, errmsg)
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unsigned long insn;
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long value;
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const char **errmsg;
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{
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if (value >= ((insn >> 21) & 0x1f))
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*errmsg = "index register in load range";
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return insn | ((value & 0x1f) << 16);
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}
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/* The RA field in a D or X form instruction which is an updating
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store or an updating floating point load, which means that the RA
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field may not be zero. */
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static unsigned long
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insert_ras (insn, value, errmsg)
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unsigned long insn;
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long value;
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const char **errmsg;
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{
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if (value == 0)
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*errmsg = "invalid register operand when updating";
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return insn | ((value & 0x1f) << 16);
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}
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/* The RB field in an X form instruction when it must be the same as
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the RS field in the instruction. This is used for extended
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mnemonics like mr. This operand is marked FAKE. The insertion
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@ -856,9 +937,8 @@ extract_sh6 (insn, invalid)
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return ((insn >> 11) & 0x1f) | ((insn << 4) & 0x20);
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}
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/* The SPR or TBR field in an XFX form instruction. This is
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flipped--the lower 5 bits are stored in the upper 5 and vice-
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versa. */
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/* The SPR field in an XFX form instruction. This is flipped--the
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lower 5 bits are stored in the upper 5 and vice- versa. */
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static unsigned long
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insert_spr (insn, value, errmsg)
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@ -876,6 +956,40 @@ extract_spr (insn, invalid)
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{
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return ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
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}
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/* The TBR field in an XFX instruction. This is just like SPR, but it
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is optional. When TBR is omitted, it must be inserted as 268 (the
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magic number of the TB register). These functions treat 0
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(indicating an omitted optional operand) as 268. This means that
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``mftb 4,0'' is not handled correctly. This does not matter very
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much, since the architecture manual does not define mftb as
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accepting any values other than 268 or 269. */
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#define TB (268)
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static unsigned long
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insert_tbr (insn, value, errmsg)
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unsigned long insn;
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long value;
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const char **errmsg;
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{
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if (value == 0)
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value = TB;
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return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
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}
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static long
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extract_tbr (insn, invalid)
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unsigned long insn;
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int *invalid;
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{
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long ret;
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ret = ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
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if (ret == TB)
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ret = 0;
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return ret;
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}
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/* Macros used to form opcodes. */
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@ -1065,11 +1179,26 @@ extract_spr (insn, invalid)
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#define XS(op, xop, rc) (OP (op) | (((xop) & 0x1ff) << 2) | ((rc) & 1))
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#define XS_MASK XS (0x3f, 0x1ff, 1)
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/* A mask for the FXM version of an XFX form instruction. */
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#define XFXFXM_MASK (X_MASK | (1 << 20) | (1 << 11))
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/* An XFX form instruction with the FXM field filled in. */
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#define XFXM(op, xop, fxm) \
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(X ((op), (xop)) | (((fxm) & 0xff) << 12))
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/* An XFX form instruction with the SPR field filled in. */
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#define XSPR(op, xop, spr) \
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(X ((op), (xop)) | (((spr) & 0x1f) << 16) | (((spr) & 0x3e0) << 6))
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#define XSPR_MASK (X_MASK | SPR_MASK)
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/* An XFX form instruction with the SPR field filled in except for the
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SPRBAT field. */
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#define XSPRBAT_MASK (XSPR_MASK &~ SPRBAT_MASK)
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/* An XFX form instruction with the SPR field filled in except for the
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SPRG field. */
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#define XSPRG_MASK (XSPR_MASK &~ SPRG_MASK)
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/* The BO encodings used in extended conditional branch mnemonics. */
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#define BODNZF (0x0)
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#define BODNZFP (0x1)
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@ -1854,8 +1983,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{ "cmpw", XCMPL(31,0,0), XCMPL_MASK, PPC, { OBF, RA, RB } },
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{ "cmpd", XCMPL(31,0,1), XCMPL_MASK, PPC|B64, { OBF, RA, RB } },
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{ "cmp", X(31,0), XCMPL_MASK, POWER, { BF, RA, RB } },
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{ "cmp", X(31,0), XCMP_MASK, PPC, { BF, L, RA, RB } },
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{ "cmp", X(31,0), XCMPL_MASK, POWER, { BF, RA, RB } },
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{ "twlgt", XTO(31,4,TOLGT), XTO_MASK, PPC, { RA, RB } },
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{ "tlgt", XTO(31,4,TOLGT), XTO_MASK, POWER, { RA, RB } },
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@ -1947,8 +2076,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{ "cmplw", XCMPL(31,32,0), XCMPL_MASK, PPC, { OBF, RA, RB } },
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{ "cmpld", XCMPL(31,32,1), XCMPL_MASK, PPC|B64, { OBF, RA, RB } },
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{ "cmpl", X(31,32), XCMPL_MASK, POWER, { BF, RA, RB } },
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{ "cmpl", X(31,32), XCMP_MASK, PPC, { BF, L, RA, RB } },
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{ "cmpl", X(31,32), XCMPL_MASK, POWER, { BF, RA, RB } },
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{ "subf", XO(31,40,0,0), XO_MASK, PPC, { RT, RA, RB } },
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{ "sub", XO(31,40,0,0), XO_MASK, PPC, { RT, RB, RA } },
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@ -1959,11 +2088,11 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{ "subfo.", XO(31,40,1,1), XO_MASK, PPC, { RT, RA, RB } },
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{ "subo.", XO(31,40,1,1), XO_MASK, PPC, { RT, RB, RA } },
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{ "ldux", X(31,53), X_MASK, PPC|B64, { RT, RA, RB } },
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{ "ldux", X(31,53), X_MASK, PPC|B64, { RT, RAL, RB } },
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{ "dcbst", X(31,54), XRT_MASK, PPC, { RA, RB } },
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{ "lwzux", X(31,55), X_MASK, PPC, { RT, RA, RB } },
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{ "lwzux", X(31,55), X_MASK, PPC, { RT, RAL, RB } },
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{ "lux", X(31,55), X_MASK, POWER, { RT, RA, RB } },
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{ "cntlzd", XRC(31,58,0), XRB_MASK, PPC|B64, { RA, RS } },
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@ -2014,7 +2143,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{ "clf", X(31,118), XRB_MASK, POWER, { RT, RA } },
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{ "lbzux", X(31,119), X_MASK, PPC|POWER, { RT, RA, RB } },
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{ "lbzux", X(31,119), X_MASK, PPC|POWER, { RT, RAL, RB } },
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{ "not", XRC(31,124,0), X_MASK, PPC|POWER, { RA, RS, RBS } },
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{ "nor", XRC(31,124,0), X_MASK, PPC|POWER, { RA, RS, RB } },
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@ -2039,7 +2168,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{ "addeo.", XO(31,138,1,1), XO_MASK, PPC, { RT, RA, RB } },
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{ "aeo.", XO(31,138,1,1), XO_MASK, POWER, { RT, RA, RB } },
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{ "mtcrf", X(31,144), X_MASK|(1<<20)|(1<<11), PPC|POWER, { FXM, RS } },
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{ "mtcr", XFXM(31,144,0xff), XFXFXM_MASK|FXM_MASK, PPC|POWER, { RS }},
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{ "mtcrf", X(31,144), XFXFXM_MASK, PPC|POWER, { FXM, RS } },
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{ "mtmsr", X(31,146), XRARB_MASK, PPC|POWER, { RS } },
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@ -2056,9 +2186,9 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{ "sle", XRC(31,153,0), X_MASK, POWER|M601, { RA, RS, RB } },
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{ "sle.", XRC(31,153,1), X_MASK, POWER|M601, { RA, RS, RB } },
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{ "stdux", X(31,181), X_MASK, PPC|B64, { RS, RA, RB } },
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{ "stdux", X(31,181), X_MASK, PPC|B64, { RS, RAS, RB } },
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{ "stwux", X(31,183), X_MASK, PPC, { RS, RA, RB } },
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{ "stwux", X(31,183), X_MASK, PPC, { RS, RAS, RB } },
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{ "stux", X(31,183), X_MASK, POWER, { RS, RA, RB } },
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{ "sliq", XRC(31,184,0), X_MASK, POWER|M601, { RA, RS, SH } },
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@ -2131,7 +2261,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{ "dcbtst", X(31,246), XRT_MASK, PPC, { RA, RB } },
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{ "stbux", X(31,247), X_MASK, PPC|POWER, { RS, RA, RB } },
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{ "stbux", X(31,247), X_MASK, PPC|POWER, { RS, RAS, RB } },
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{ "slliq", XRC(31,248,0), X_MASK, POWER|M601, { RA, RS, SH } },
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{ "slliq.", XRC(31,248,1), X_MASK, POWER|M601, { RA, RS, SH } },
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@ -2165,7 +2295,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{ "eciwx", X(31,310), X_MASK, PPC, { RT, RA, RB } },
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{ "lhzux", X(31,311), X_MASK, PPC|POWER, { RT, RA, RB } },
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{ "lhzux", X(31,311), X_MASK, PPC|POWER, { RT, RAL, RB } },
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{ "xor", XRC(31,316,0), X_MASK, PPC|POWER, { RA, RS, RB } },
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{ "xor.", XRC(31,316,1), X_MASK, PPC|POWER, { RA, RS, RB } },
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@ -2177,8 +2307,27 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{ "mfmq", XSPR(31,339,0), XSPR_MASK, POWER|M601, { RT } },
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{ "mfxer", XSPR(31,339,1), XSPR_MASK, PPC|POWER, { RT } },
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{ "mfrtcu", XSPR(31,339,4), XSPR_MASK, PPC|POWER, { RT } },
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{ "mfrtcl", XSPR(31,339,5), XSPR_MASK, PPC|POWER, { RT } },
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{ "mfdec", XSPR(31,339,6), XSPR_MASK, POWER|M601, { RT } },
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{ "mflr", XSPR(31,339,8), XSPR_MASK, PPC|POWER, { RT } },
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{ "mfctr", XSPR(31,339,9), XSPR_MASK, PPC|POWER, { RT } },
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{ "mftid", XSPR(31,339,17), XSPR_MASK, POWER, { RT } },
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{ "mfdsisr", XSPR(31,339,18), XSPR_MASK, PPC|POWER, { RT } },
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{ "mfdar", XSPR(31,339,19), XSPR_MASK, PPC|POWER, { RT } },
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{ "mfdec", XSPR(31,339,22), XSPR_MASK, PPC, { RT } },
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{ "mfsdr0", XSPR(31,339,24), XSPR_MASK, POWER, { RT } },
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{ "mfsdr1", XSPR(31,339,25), XSPR_MASK, PPC|POWER, { RT } },
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{ "mfsrr0", XSPR(31,339,26), XSPR_MASK, PPC|POWER, { RT } },
|
||||
{ "mfsrr1", XSPR(31,339,27), XSPR_MASK, PPC|POWER, { RT } },
|
||||
{ "mfsprg", XSPR(31,339,272), XSPRG_MASK, PPC, { RT, SPRG } },
|
||||
{ "mfasr", XSPR(31,339,280), XSPR_MASK, PPC|B64, { RT } },
|
||||
{ "mfear", XSPR(31,339,282), XSPR_MASK, PPC, { RT } },
|
||||
{ "mfpvr", XSPR(31,339,287), XSPR_MASK, PPC, { RT } },
|
||||
{ "mfibatu", XSPR(31,339,528), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
|
||||
{ "mfibatl", XSPR(31,339,529), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
|
||||
{ "mfdbatu", XSPR(31,339,536), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
|
||||
{ "mfdbatl", XSPR(31,339,537), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
|
||||
{ "mfspr", X(31,339), X_MASK, PPC|POWER, { RT, SPR } },
|
||||
|
||||
{ "lwax", X(31,341), X_MASK, PPC|B64, { RT, RA, RB } },
|
||||
|
|
@ -2197,11 +2346,12 @@ const struct powerpc_opcode powerpc_opcodes[] = {
|
|||
|
||||
{ "tlbia", X(31,370), 0xffffffff, PPC, { 0 } },
|
||||
|
||||
{ "mftbu", XSPR(31,371,269), XSPR_MASK, PPC, { RT } },
|
||||
{ "mftb", X(31,371), X_MASK, PPC, { RT, TBR } },
|
||||
|
||||
{ "lwaux", X(31,373), X_MASK, PPC|B64, { RT, RA, RB } },
|
||||
{ "lwaux", X(31,373), X_MASK, PPC|B64, { RT, RAL, RB } },
|
||||
|
||||
{ "lhaux", X(31,375), X_MASK, PPC|POWER, { RT, RA, RB } },
|
||||
{ "lhaux", X(31,375), X_MASK, PPC|POWER, { RT, RAL, RB } },
|
||||
|
||||
{ "sthx", X(31,407), X_MASK, PPC|POWER, { RS, RA, RB } },
|
||||
|
||||
|
|
@ -2223,7 +2373,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
|
|||
|
||||
{ "ecowx", X(31,438), X_MASK, PPC, { RT, RA, RB } },
|
||||
|
||||
{ "sthux", X(31,439), X_MASK, PPC|POWER, { RS, RA, RB } },
|
||||
{ "sthux", X(31,439), X_MASK, PPC|POWER, { RS, RAS, RB } },
|
||||
|
||||
{ "mr", XRC(31,444,0), X_MASK, PPC|POWER, { RA, RS, RBS } },
|
||||
{ "or", XRC(31,444,0), X_MASK, PPC|POWER, { RA, RS, RB } },
|
||||
|
|
@ -2244,6 +2394,25 @@ const struct powerpc_opcode powerpc_opcodes[] = {
|
|||
{ "mtxer", XSPR(31,467,1), XSPR_MASK, PPC|POWER, { RS } },
|
||||
{ "mtlr", XSPR(31,467,8), XSPR_MASK, PPC|POWER, { RS } },
|
||||
{ "mtctr", XSPR(31,467,9), XSPR_MASK, PPC|POWER, { RS } },
|
||||
{ "mttid", XSPR(31,467,17), XSPR_MASK, POWER, { RS } },
|
||||
{ "mtdsisr", XSPR(31,467,18), XSPR_MASK, PPC|POWER, { RS } },
|
||||
{ "mtdar", XSPR(31,467,19), XSPR_MASK, PPC|POWER, { RS } },
|
||||
{ "mtrtcu", XSPR(31,467,20), XSPR_MASK, PPC|POWER, { RS } },
|
||||
{ "mtrtcl", XSPR(31,467,21), XSPR_MASK, PPC|POWER, { RS } },
|
||||
{ "mtdec", XSPR(31,467,22), XSPR_MASK, PPC|POWER, { RS } },
|
||||
{ "mtsdr0", XSPR(31,467,24), XSPR_MASK, POWER, { RS } },
|
||||
{ "mtsdr1", XSPR(31,467,25), XSPR_MASK, PPC|POWER, { RS } },
|
||||
{ "mtsrr0", XSPR(31,467,26), XSPR_MASK, PPC|POWER, { RS } },
|
||||
{ "mtsrr1", XSPR(31,467,27), XSPR_MASK, PPC|POWER, { RS } },
|
||||
{ "mtsprg", XSPR(31,467,272), XSPRG_MASK, PPC, { SPRG, RS } },
|
||||
{ "mtasr", XSPR(31,467,280), XSPR_MASK, PPC|B64, { RS } },
|
||||
{ "mtear", XSPR(31,467,282), XSPR_MASK, PPC, { RS } },
|
||||
{ "mttbl", XSPR(31,467,284), XSPR_MASK, PPC, { RS } },
|
||||
{ "mttbu", XSPR(31,467,285), XSPR_MASK, PPC, { RS } },
|
||||
{ "mtibatu", XSPR(31,467,528), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
|
||||
{ "mtibatl", XSPR(31,467,529), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
|
||||
{ "mtdbatu", XSPR(31,467,536), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
|
||||
{ "mtdbatl", XSPR(31,467,537), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
|
||||
{ "mtspr", X(31,467), X_MASK, PPC|POWER, { SPR, RS } },
|
||||
|
||||
{ "dcbi", X(31,470), XRT_MASK, PPC, { RA, RB } },
|
||||
|
|
@ -2298,7 +2467,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
|
|||
|
||||
{ "tlbsync", X(31,566), 0xffffffff, PPC, { 0 } },
|
||||
|
||||
{ "lfsux", X(31,567), X_MASK, PPC|POWER, { FRT, RA, RB } },
|
||||
{ "lfsux", X(31,567), X_MASK, PPC|POWER, { FRT, RAS, RB } },
|
||||
|
||||
{ "mfsr", X(31,595), XRB_MASK|(1<<20), PPC|POWER|B32, { RT, SR } },
|
||||
|
||||
|
|
@ -2314,7 +2483,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
|
|||
|
||||
{ "dclst", X(31,630), XRB_MASK, POWER, { RS, RA } },
|
||||
|
||||
{ "lfdux", X(31,631), X_MASK, PPC|POWER, { FRT, RA, RB } },
|
||||
{ "lfdux", X(31,631), X_MASK, PPC|POWER, { FRT, RAS, RB } },
|
||||
|
||||
{ "mfsrin", X(31,659), XRA_MASK, PPC|B32, { RT, RB } },
|
||||
|
||||
|
|
@ -2332,7 +2501,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
|
|||
{ "sre", XRC(31,665,0), X_MASK, POWER|M601, { RA, RS, RB } },
|
||||
{ "sre.", XRC(31,665,1), X_MASK, POWER|M601, { RA, RS, RB } },
|
||||
|
||||
{ "stfsux", X(31,695), X_MASK, PPC|POWER, { FRS, RA, RB } },
|
||||
{ "stfsux", X(31,695), X_MASK, PPC|POWER, { FRS, RAS, RB } },
|
||||
|
||||
{ "sriq", XRC(31,696,0), X_MASK, POWER|M601, { RA, RS, SH } },
|
||||
{ "sriq.", XRC(31,696,1), X_MASK, POWER|M601, { RA, RS, SH } },
|
||||
|
|
@ -2348,7 +2517,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
|
|||
{ "sreq", XRC(31,729,0), X_MASK, POWER|M601, { RA, RS, RB } },
|
||||
{ "sreq.", XRC(31,729,1), X_MASK, POWER|M601, { RA, RS, RB } },
|
||||
|
||||
{ "stfdux", X(31,759), X_MASK, PPC|POWER, { FRS, RA, RB } },
|
||||
{ "stfdux", X(31,759), X_MASK, PPC|POWER, { FRS, RAS, RB } },
|
||||
|
||||
{ "srliq", XRC(31,760,0), X_MASK, POWER|M601, { RA, RS, SH } },
|
||||
{ "srliq.", XRC(31,760,1), X_MASK, POWER|M601, { RA, RS, SH } },
|
||||
|
|
@ -2404,36 +2573,36 @@ const struct powerpc_opcode powerpc_opcodes[] = {
|
|||
{ "lwz", OP(32), OP_MASK, PPC, { RT, D, RA } },
|
||||
{ "l", OP(32), OP_MASK, POWER, { RT, D, RA } },
|
||||
|
||||
{ "lwzu", OP(33), OP_MASK, PPC, { RT, D, RA } },
|
||||
{ "lwzu", OP(33), OP_MASK, PPC, { RT, D, RAL } },
|
||||
{ "lu", OP(33), OP_MASK, POWER, { RT, D, RA } },
|
||||
|
||||
{ "lbz", OP(34), OP_MASK, PPC|POWER, { RT, D, RA } },
|
||||
|
||||
{ "lbzu", OP(35), OP_MASK, PPC|POWER, { RT, D, RA } },
|
||||
{ "lbzu", OP(35), OP_MASK, PPC|POWER, { RT, D, RAL } },
|
||||
|
||||
{ "stw", OP(36), OP_MASK, PPC, { RS, D, RA } },
|
||||
{ "st", OP(36), OP_MASK, POWER, { RS, D, RA } },
|
||||
|
||||
{ "stwu", OP(37), OP_MASK, PPC, { RS, D, RA } },
|
||||
{ "stwu", OP(37), OP_MASK, PPC, { RS, D, RAS } },
|
||||
{ "stu", OP(37), OP_MASK, POWER, { RS, D, RA } },
|
||||
|
||||
{ "stb", OP(38), OP_MASK, PPC|POWER, { RS, D, RA } },
|
||||
|
||||
{ "stbu", OP(39), OP_MASK, PPC|POWER, { RS, D, RA } },
|
||||
{ "stbu", OP(39), OP_MASK, PPC|POWER, { RS, D, RAS } },
|
||||
|
||||
{ "lhz", OP(40), OP_MASK, PPC|POWER, { RT, D, RA } },
|
||||
|
||||
{ "lhzu", OP(41), OP_MASK, PPC|POWER, { RT, D, RA } },
|
||||
{ "lhzu", OP(41), OP_MASK, PPC|POWER, { RT, D, RAL } },
|
||||
|
||||
{ "lha", OP(42), OP_MASK, PPC|POWER, { RT, D, RA } },
|
||||
|
||||
{ "lhau", OP(43), OP_MASK, PPC|POWER, { RT, D, RA } },
|
||||
{ "lhau", OP(43), OP_MASK, PPC|POWER, { RT, D, RAL } },
|
||||
|
||||
{ "sth", OP(44), OP_MASK, PPC|POWER, { RS, D, RA } },
|
||||
|
||||
{ "sthu", OP(45), OP_MASK, PPC|POWER, { RS, D, RA } },
|
||||
{ "sthu", OP(45), OP_MASK, PPC|POWER, { RS, D, RAS } },
|
||||
|
||||
{ "lmw", OP(46), OP_MASK, PPC, { RT, D, RA } },
|
||||
{ "lmw", OP(46), OP_MASK, PPC, { RT, D, RAM } },
|
||||
{ "lm", OP(46), OP_MASK, POWER, { RT, D, RA } },
|
||||
|
||||
{ "stmw", OP(47), OP_MASK, PPC, { RS, D, RA } },
|
||||
|
|
@ -2441,19 +2610,19 @@ const struct powerpc_opcode powerpc_opcodes[] = {
|
|||
|
||||
{ "lfs", OP(48), OP_MASK, PPC|POWER, { FRT, D, RA } },
|
||||
|
||||
{ "lfsu", OP(49), OP_MASK, PPC|POWER, { FRT, D, RA } },
|
||||
{ "lfsu", OP(49), OP_MASK, PPC|POWER, { FRT, D, RAS } },
|
||||
|
||||
{ "lfd", OP(50), OP_MASK, PPC|POWER, { FRT, D, RA } },
|
||||
|
||||
{ "lfdu", OP(51), OP_MASK, PPC|POWER, { FRT, D, RA } },
|
||||
{ "lfdu", OP(51), OP_MASK, PPC|POWER, { FRT, D, RAS } },
|
||||
|
||||
{ "stfs", OP(52), OP_MASK, PPC|POWER, { FRS, D, RA } },
|
||||
|
||||
{ "stfsu", OP(53), OP_MASK, PPC|POWER, { FRS, D, RA } },
|
||||
{ "stfsu", OP(53), OP_MASK, PPC|POWER, { FRS, D, RAS } },
|
||||
|
||||
{ "stfd", OP(54), OP_MASK, PPC|POWER, { FRS, D, RA } },
|
||||
|
||||
{ "stfdu", OP(55), OP_MASK, PPC|POWER, { FRS, D, RA } },
|
||||
{ "stfdu", OP(55), OP_MASK, PPC|POWER, { FRS, D, RAS } },
|
||||
|
||||
{ "lfq", OP(56), OP_MASK, POWER2, { FRT, D, RA } },
|
||||
|
||||
|
|
@ -2461,7 +2630,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
|
|||
|
||||
{ "ld", DSO(58,0), DS_MASK, PPC|B64, { RT, DS, RA } },
|
||||
|
||||
{ "ldu", DSO(58,1), DS_MASK, PPC|B64, { RT, DS, RA } },
|
||||
{ "ldu", DSO(58,1), DS_MASK, PPC|B64, { RT, DS, RAL } },
|
||||
|
||||
{ "lwa", DSO(58,2), DS_MASK, PPC|B64, { RT, DS, RA } },
|
||||
|
||||
|
|
@ -2501,7 +2670,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
|
|||
|
||||
{ "std", DSO(62,0), DS_MASK, PPC|B64, { RS, DS, RA } },
|
||||
|
||||
{ "stdu", DSO(62,1), DS_MASK, PPC|B64, { RS, DS, RA } },
|
||||
{ "stdu", DSO(62,1), DS_MASK, PPC|B64, { RS, DS, RAS } },
|
||||
|
||||
{ "fcmpu", X(63,0), X_MASK|(3<<21), PPC|POWER, { BF, FRA, FRB } },
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue