opcodes:
* sh-opc.h (sh_nibble_type): Remove DISP_8 and DISP_4.
Split IMM_[48]{,BY[24]} into IMM[01]_[48]{,BY[24]}. Add REPEAT.
(sh_arg_type): Add A_PC.
(sh_table): Update entries using immediates. Add repeat.
* sh-dis.c (print_insn_shx): Remove DISP_8 and DISP_4.
Split IMM_[48]{,BY[24]} into IMM[01]_[48]{,BY[24]}. Add REPEAT.
gas:
* config/tc-sh.c (immediate): Delete.
(sh_operand_info): Add immediate member.
(parse_reg): Use A_PC for pc.
(parse_exp): Add second argument 'op'. All callers changed.
(parse_at): Expect pc to be coded as A_PC.
Use immediate field in *op.
(insert): Add fourth argument 'op'. All callers changed.
(build_relax): Add second argument 'op'. All callers changed.
(insert_loop_bounds): New function.
(build_Mytes): Remove DISP_4.
Split IMM_[48]{,BY[24]} into IMM[01]_[48]{,BY[24]}. Add REPEAT.
(assemble_ppi): Use immediate field in *operand.
(sh_force_relocation): Handle BFD_RELOC_SH_LOOP_{START,END}.
(md_apply_fix): Likewise.
(tc_gen_reloc): Likewise. Check for a pcrel BFD_RELOC_SH_LABEL.
include/coff:
* sh.h (R_SH_LOOP_START, R_SH_LOOP_END): Define.
include/elf:
* sh.h (R_SH_LOOP_START, R_SH_LOOP_END): New RELOC_NUMBERs.
bfd:
* reloc.c (_bfd_relocate_contents): Add BFD_RELOC_SH_LOOP_START and
BFD_RELOC_SH_LOOP_END.
* elf32-sh.c (sh_elf_howto_tab): Change special_func to
sh_elf_ignore_reloc for all entries that sh_elf_reloc used to ignore.
Add entries for R_SH_LOOP_START and R_SH_LOOP_END.
(sh_elf_reloc_loop): New function.
(sh_elf_reloc): No need to test for always-to-be-ignored relocs
any more.
(sh_rel): Add entries for BFD_RELOC_SH_LOOP_{START,END}.
(sh_elf_relocate_section): Handle BFD_RELOC_SH_LOOP_{START,END}.
* bfd-in2.h, libbfd.h: Regenerate.
BFD_RELOC_16 to switch for extended relocs.
(MY_swap_ext_reloc_in): New.
(MY_swap_ext_reloc_out): New.
(NAME(aout,slurp_reloc_table)): Use MY_swap_ext_reloc_in rather
than NAME(aout,swap_ext_reloc_in) for extended relocs.
(NAME(aout,squirt_out_relocs)): Similarly use
MY_swap_ext_reloc_out.
(aout_link_reloc_link_order): Use MY_put_ext_reloc if defined.
HOWTO references to bfd_elf_generic_reloc, that have
partial_inplace == true, now use the new function. The function
is based on the recent rewrite of m32r_elf_lo16_reloc(), and
extends its fixes to the R_M32R_{16,24,32} relocs.
The new logic in m32r_elf_lo16_reloc() has been removed, and
it instead calls the new routine to obtain that functionality.
complain_overflow_bitfield doesn't complain) from -2**(n-1)..2**n-1 to
-2**n..2**n. This might mean that some reloc overflows are no longer
caught, but it solves the address wrap problem for 16-bit relocs
nicely. In any case, ports that rely on complain_overflow_bitfield
for reloc overflow checking were not getting a very good check
previously. A bitfield range in a machine instruction is typically
either the signed or unsigned n bit numbers, not the overlap of these
two ranges.
* elf32-mips.c (mips_elf_next_relocation): Rename from
mips_elf_next_lo16_relocation, and generalize to look
for any relocation type.
(elf_mips_howto_table): Make R_MIPS_PC16 pcrel_offset.
(elf_mips_gnu_rel_hi16): Howto for R_MIPS_GNU_REL_HI16.
(elf_mips_gnu_rel_lo16): Howto for R_MIPS_GNU_REL_LO16.
(elf_mips_gnu_rel16_s2): Howto for R_MIPS_GNU_REL16_S2.
(elf_mips_gnu_pcrel64): Howto for R_MIPS_PC64.
(elf_mips_gnu_pcrel32): Howto for R_MIPS_PC32.
(bfd_elf32_bfd_reloc_type_lookup): Add new relocs.
(mips_rtype_to_howto): Likewise.
(mips_elf_calculate_relocation): Handle new relocs.
(_bfd_mips_elf_relocate_section): REL_HI16/REL_LO16 relocs
are paired. The addend for R_MIPS_GNU_REL16_S2
is shifted right two bits.
In gas/:
* config/tc-mips.c (mips_ip): Don't put stuff in .rodata
when embedded-pic.
* config/tc-mips.c (SWITCH_TABLE): The ELF embedded-pic
implementation doesn't have special handling for switch
statements.
(macro_build): Allow for code in sections other than .text.
(macro): Likewise.
(mips_ip): Likewise.
(md_apply_fix): Do pc-relative relocation madness for MIPS ELF.
Don't perform relocs if we will be outputting them.
(tc_gen_reloc): For ELF, just use fx_addnumber for pc-relative
relocations. Allow BFD_RELOC_16_PCREL_S2 relocs when
embedded-pic.
In gas/testsuite/:
* gas/mips/empic.d: New file.
* gas/mips/empic.s: New file.
* gas/mips/mips16-e.d: New file.
* gas/mips/mips16-e.s: New file.
* gas/mips/mips16-f.d: New file.
* gas/mips/mips16-f.s: New file.
* gas/mips/mips.exp: Add empic, mips16-e. Add mips16-f as an
expected failure.
In include/elf:
* mips.h: Add R_MIPS_GNU_REL_HI16, R_MIPS_GNU_REL_LO16,
R_MIPS_GNU_REL16_S2, R_MIPS_PC64 and R_MIPS_PC32 relocation
numbers.
* elf32-sparc.c (elf32_sparc_merge_private_bfd_data): Don't bump
architecture if the object causing the bump is dynamic.
* elf64-sparc.c (sparc64_elf_merge_private_bfd_data): Likewise,
and also don't it for memory ordering.
(sparc64_elf_write_relocs): Take src_rela out of the loop.
secondary_def.
(som_bfd_derive_misc_symbol_info): Initialize
secondary_def.
(som_build_and_write_symbol_table): Keep track
of secondary_def field.
(som_slurp_symbol_table): Set BSF_WEAK symbol flag
if secondary_def field is set.
(som_bfd_ar_write_symbol_stuff): Initialize
secondary_def.
Reinstate bits of sh4 support that got accidentally deleted.
Add sh-dsp support.
bfd:
* archures.c (bfd_mach_sh2, bfd_mach_sh_dsp): New macros.
(bfd_mach_sh3_dsp): Likewise.
(bfd_mach_sh4): Reinstate.
(bfd_default_scan): Recognize 7410, 7708, 7729 and 7750.
* bfd-in2.h: Regenerate.
* coff-sh.c (struct sh_opcode): flags is no longer short.
(USESAS, USESAS_REG, USESR8, SETSAS, SETSAS_REG): New macros.
(sh_opcode41, sh_opcode42): Integrate as sh_opcode41.
(sh_opcode01, sh_opcode02, sh_opcode40): Add sh-dsp opcodes.
(sh_opcode41, sh_opcode4, sh_opcode80): Likewise.
(sh_opcodes): No longer const.
(sh_dsp_opcodef0, sh_dsp_opcodef): New arrays.
(sh_insn_uses_reg): Check for USESAS and USESR8.
(sh_insn_sets_reg, sh_insns_conflict): Check for SETSAS.
(_bfd_sh_align_load_span): Return early for SH4.
Modify sh_opcodes lookup table for sh-dsp / sh3-dsp.
Take into account that field b of a parallel processing insn
could be mistaken for a separate insn.
* cpu-sh.c (arch_info_struct): New array elements for
sh2, sh-dsp and sh3-dsp.
Reinstate element for sh4.
(SH2_NEXT, SH_DSP_NEXT, SH3_DSP_NEXT): New macros.
(SH4_NEXT): Reinstate.
(SH3_NEXT, SH3E_NEXT): Adjust.
* elf-bfd.h (_sh_elf_set_mach_from_flags): Declare.
* elf32-sh.c (sh_elf_set_private_flags): New function.
(sh_elf_copy_private_data, sh_elf_set_mach_from_flags): Likewise.
(sh_elf_merge_private_data): New function.
(elf_backend_object_p, bfd_elf32_bfd_set_private_bfd_flags): Define.
(bfd_elf32_bfd_copy_private_bfd_data): Define.
(bfd_elf32_bfd_merge_private_bfd_data): Change to
sh_elf_merge_private_data.
gas:
* config/tc-sh.c ("elf/sh.h"): Include.
(sh_dsp, valid_arch, reg_x, reg_y, reg_efg): New static variables.
(md.begin): Initialize target_arch.
Only include opcodes in has table that match selected architecture.
(parse_reg): Recognize register names for sh-dsp.
(parse_at): Recognize post-modify addressing.
(get_operands): The leading space is now optional.
(get_specific): Remove FDREG_N support. Add support for sh-dsp
arguments. Update valid_arch.
(build_Mytes): Add support for SDT_REG_N.
(find_cooked_opcode): New function, broken out of md_assemble.
(assemble_ppi, sh_elf_final_processing): New functions.
(md_assemble): Use find_cooked_opcode and assemble_ppi.
(md_longopts, md_parse_option): New option: -dsp.
* config/tc-sh.h (elf_tc_final_processing): Define.
(sh_elf_final_processing): Declare.
include/elf:
* sh.h: (EF_SH_MACH_MASK, EF_SH_UNKNOWN, EF_SH1, EF_SH2): New macros.
(EF_SH3, EF_SH_HAS_DSP, EF_SH_DSP, EF_SH3_DSP): Likewise.
(EF_SH_HAS_FP, EF_SH3E, EF_SH4, EF_SH_MERGE_MACH): Likewise.
opcodes:
* sh-dis.c (print_movxy, print_insn_ddt, print_dsp_reg): New functions.
(print_insn_ppi): Likewise.
(print_insn_shx): Use info->mach to select appropriate insn set.
Add support for sh-dsp. Remove FD_REG_N support.
* sh-opc.h (sh_nibble_type): Add new values for sh-dsp support.
(sh_arg_type): Likewise. Remove FD_REG_N.
(sh_dsp_reg_nums): New enum.
(arch_sh1, arch_sh2, arch_sh3, arch_sh3e, arch_sh4): New macros.
(arch_sh_dsp, arch_sh3_dsp, arch_sh1_up, arch_sh2_up): Likewise.
(arch_sh3_up, arch_sh3e_up, arch_sh4_up, arch_sh_dsp_up): Likewise.
(arch_sh3_dsp_up): Likewise.
(sh_opcode_info): New field: arch.
(sh_table): Split up insn with FD_REG_N into ones with F_REG_N and
D_REG_N. Fill in arch field. Add sh-dsp insns.
hide_symbol members.
(elf_link_hash_copy_indirect): New.
(elf_link_hash_hide_symbol): New.
* elflink.h (elf_link_add_object_symbols): Break out copy from
indirect new new symbol to elf.c.
(elf_link_assign_sym_version): Break out privatization of
non-exported symbol to elf.c.
* elf.c (_bfd_elf_link_hash_copy_indirect): New.
(_bfd_elf_link_hash_hide_symbol): New.
(_bfd_elf_link_hash_table_init): Init copy_indirect and hide_symbol.
If it passed as non-NULL, use it to check whether any input BFD
has an input section which uses this output section. Change all
callers.
* bfd-in2.h: Rebuild.
* bfd-in.h: Move declarations of bfd_get_elf_phdr_upper_bound and
bfd_get_elf_phdrs in from bfd-in2.h, correcting patch of
1999-11-29.
* bfd-in2.h: Rebuild.
same register:
* coff-sh.c (USES1_REG, USES2_REG, SETS1_REG, SETS2_REG,
USESF1_REG, USESF2_REG, SETSF1_REG, SETSF2_REG): New macros.
* (sh_insn_sets_reg, sh_insn_sets_freg): New prototypes.
* (sh_insn_sets_reg, sh_insn_uses_or_sets_reg, sh_insns_sets_freg,
sh_insns_uses_or_sets_freg): New functions.
* (sh_insn_uses_reg, sh_insn_uses_freg): Use new macros.
* (sh_insns_conflict): Use new functions and new macros to
detect conflicts when two instructions both set same integer registers,
both set same fp register, and both set special register.
Change LD for ELF so that archive elements whoes archive map contains a
reference to a common symbol will get linkled in.
Add new field to bfd_target structure and initialise it for all bfd targets.
relocs also need the GP value.
(_bfd_mips_elf_relocate_section): Handle unpaired LO16 relocs
properly. Handle sign-extension for R_MIPS_64 correctly. Correct
the GP value for R_MIPS_LITERAL relocs too. Handle
R_MIPS_64 relocs properly on big-endian MIPS.
(mips_elf_sign_extend): Behave properly with 'long long'.
(mips_elf_highest): Correct typo.
* targets.c (cisco_core_vec): Replaced with two new vecs ...
(cisco_core_big_vec): Add new bigendian vec.
(cisco_core_little_vec): Add new little endian vec.
* cisco-core.c (CRASH_INFO): Fixed offset replaced with ...
(crash_info_locs): Add array of possible offsets.
(MASK_ADDR): Mask to apply to crash info offset.
(crashinfo_external): Add textbase, database, bssbase and
turn into a typedef.
(cisco_core_file_validate): Renamed from cisco_core_file_p.
Many small changes to account for additional hardware versions.
Pick a reasonable size for ".reg" section. Add a ".crash"
section to allow access to crashinfo_external struct.
(cisco_core_file_p): New version of this function that
iterates over crash_info_locs, calling cisco_core_file_validate.
(cisco_core_vec): Old big endian only vec replaced with ...
(cisco_core_big_vec): Add big endian version.
(cisco_core_little_vec): Add little endian version.
* configure.in (cisco_core_vec): Split to two new vectors ...
(cisco_core_big_vec): New target vector.
(cisco_core_little_vec): New target vector.
* configure: Regenerate.
* config.bfd (targ): For m68*-*-aout* targ, change cisco_core_vec
to cisco_core_big_vec in targ_selvecs.
