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More tests.

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Have sld check verify that the processor is a v850eq.
This commit is contained in:
Andrew Cagney 1997-09-19 06:40:11 +00:00
parent a276b6f057
commit f4822f1e6e
9 changed files with 255 additions and 16 deletions
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4
sim/testsuite/v850eq-elf/Makefile.in
View file

@ -86,8 +86,12 @@ TESTS= \
t-bsh.ok \
t-bsw.ok \
t-callt.ok \
t-cmov.ok \
t-ctret.ok \
t-hsw.ok \
t-jarl.ok \
t-jmp.ok \
t-jr.ok \
t-ldsr.ok \
t-sld.ok \
t-sxb.ok \

10
sim/testsuite/v850eq-elf/t-b.s Normal file
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@ -0,0 +1,10 @@
.include "t-macros.i"
start
load r2 0x11223344
test_bsw:
bsw r2, r3
check1 r3 0x44332211
exit0

32
sim/testsuite/v850eq-elf/t-cmov.s Normal file
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@ -0,0 +1,32 @@
.include "t-macros.i"
start
load r2 2
load r3 3
load r4 4
cmp r2, r3
test_cmov1:
cmov ne, r2, r3, r4
check1x 1 r4 2
load r4 4
cmp r2, r3
test_cmov2:
cmov ne, 2, r3, r4
check1x 2 r4 2
load r4 4
cmp r2, r3
test_cmov3:
cmov e, r2, r3, r4
check1x 3 r4 3
load r4 4
cmp r2, r3
test_cmov4:
cmov e, 2, r3, r4
check1x 4 r4 3
exit0

70
sim/testsuite/v850eq-elf/t-jarl.s Normal file
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@ -0,0 +1,70 @@
.include "t-macros.i"
start
jarl l1, r1
d1:
exit47
exit47
exit47
exit47
exit47
exit47
exit47
exit47
exit47
exit47
exit47
l5: jarl l6, r6
d6:
l6: # check
check1x 1 r1 d1
check1x 2 r2 d2
check1x 3 r3 d3
check1x 4 r4 d4
check1x 5 r5 d5
check1x 6 r6 d6
exit0
exit47
exit47
l2: jarl l3, r3
d3:
exit47
exit47
exit47
exit47
exit47
exit47
exit47
exit47
exit47
exit47
exit47
l1: jarl l2, r2
d2:
exit47
exit47
l4: jarl l5, r5
d5:
exit47
exit47
l3: jarl l4, r4
d4:
exit47
exit47
exit47
exit47
exit47
exit47
exit47
exit47

20
sim/testsuite/v850eq-elf/t-jmp.s Normal file
View file

@ -0,0 +1,20 @@
.include "t-macros.i"
start
load r2 test_jmp1
add 1, r2 # misalign
jmp [r2]
test_jmp:
exit47
exit47
exit47
exit47
exit47
exit47
exit47
exit47
test_jmp1:
exit0

59
sim/testsuite/v850eq-elf/t-jr.s Normal file
View file

@ -0,0 +1,59 @@
.include "t-macros.i"
start
jr l1
exit47
exit47
exit47
exit47
exit47
exit47
exit47
exit47
exit47
exit47
exit47
l5: jr l6
l6: exit0
exit47
exit47
l2: jr l3
exit47
exit47
exit47
exit47
exit47
exit47
exit47
exit47
exit47
exit47
exit47
l1: jr l2
exit47
exit47
l4: jr l5
exit47
exit47
l3: jr l4
exit47
exit47
exit47
exit47
exit47
exit47
exit47
exit47

27
sim/testsuite/v850eq-elf/t-macros.i
View file

@ -35,3 +35,30 @@ _start:
exit47
1:
.endm
.macro check1x sts reg val
jr 1f
.align 2
1: jarl 2f, r1
.long \val
2: ld.w 0[r1], r1
cmp r1, \reg
be 1f
mov 1, r6
addi \sts, r0, r7
trap 31
1:
.endm
# definitions of various PSW bits
PSW_US = 0x100
PSW_NP = 0x80
PSW_EP = 0x40
PSW_ID = 0x20
PSW_SAT = 0x10
PSW_CY = 0x8
PSW_OV = 0x4
PSW_S = 0x2
PSW_Z = 0x1

47
sim/testsuite/v850eq-elf/t-sld.s
View file

@ -2,56 +2,73 @@
start
# ensure that the US bit is clear
load r2 0xff
# US bit in the PSW
load r2 PSW_US
stsr psw, r3
or r2, r3
ldsr r3, psw
# check that the bit really was set
stsr psw, r3
and r2, r3
ldsr r3, psw
check1x 1 r3 PSW_US
# put something into EP
load ep ep_base
test_sldb1:
sld.b 0[ep], r4
check1 r4 0xffffff80
check1x 2 r4 0xffffff80
test_sldbu1:
sld.bu 0[ep], r4
check1 r4, 0x80
check1x 3 r4, 0x80
test_sldh1:
sld.h 0[ep], r4
check1 r4 0xffff8080
check1x 4 r4 0xffff8080
test_sldhu1:
sld.hu 0[ep], r4
check1 r4, 0x8080
check1x 5 r4, 0x8080
test_sldw1:
sld.w 0[ep], r4
check1x 5 r4, 0x80808080
# Now set the US bit
load r2 0x100
# Now clear the US bit - switch signed/unsigned
load r2 PSW_US
not r2, r2
stsr psw, r3
or r2, r3
and r2, r3
ldsr r3, psw
test_sldb2:
sld.b 0[ep], r4
check1 r4, 0x80
check1x 6 r4, 0x80
test_sldbu2:
sld.bu 0[ep], r4
check1 r4 0xffffff80
check1x 7 r4 0xffffff80
test_sldh2:
sld.h 0[ep], r4
check1 r4, 0x8080
check1x 8 r4, 0x8080
test_sldhu2:
sld.hu 0[ep], r4
check1 r4 0xffff8080
check1x 9 r4 0xffff8080
test_sldw2:
sld.w 0[ep], r4
check1x 5 r4, 0x80808080
exit0
.align 2
ep_base:
.short 0x8080
.long 0x80808080