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003-09-03 Dave Brolley <brolley@redhat.com>

Browse source 
* cpu.h, model.c, sem.c, decode.h, decode.c: Regenerated.
This commit is contained in:
Dave Brolley 2003-09-03 23:12:21 +00:00
parent ecd51ad39f
commit d03ea14fb1
6 changed files with 354 additions and 38 deletions
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4
sim/frv/ChangeLog
View file

@ -1,3 +1,7 @@
2003-09-03 Dave Brolley <brolley@redhat.com>
* cpu.h, model.c, sem.c, decode.h, decode.c: Regenerated.
2003-08-29 Dave Brolley <brolley@redhat.com> 2003-08-29 Dave Brolley <brolley@redhat.com>
* Makefile.in (stamp-arch): Copy frv.cpu from $(srcdir)../../cpu * Makefile.in (stamp-arch): Copy frv.cpu from $(srcdir)../../cpu

27
sim/frv/cpu.h
View file

@ -393,10 +393,6 @@ union sem_fields {
struct { /* */ struct { /* */
IADDR i_label24; IADDR i_label24;
} sfmt_call; } sfmt_call;
struct { /* */
UINT f_A;
UINT f_ACC40Sk;
} sfmt_mclracc;
struct { /* */ struct { /* */
INT f_u12; INT f_u12;
UINT f_FRk; UINT f_FRk;
@ -4196,7 +4192,7 @@ struct scache {
f_ope4 = EXTRACT_LSB0_UINT (insn, 32, 7, 2); \ f_ope4 = EXTRACT_LSB0_UINT (insn, 32, 7, 2); \
f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \ f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
#define EXTRACT_IFMT_MCLRACC_VARS \ #define EXTRACT_IFMT_MNOP_VARS \
UINT f_pack; \ UINT f_pack; \
UINT f_ACC40Sk; \ UINT f_ACC40Sk; \
UINT f_op; \ UINT f_op; \
@ -4205,7 +4201,26 @@ struct scache {
UINT f_ope1; \ UINT f_ope1; \
UINT f_FRj_null; \ UINT f_FRj_null; \
unsigned int length; unsigned int length;
#define EXTRACT_IFMT_MCLRACC_CODE \ #define EXTRACT_IFMT_MNOP_CODE \
length = 4; \
f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
f_ACC40Sk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \
f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
f_A = EXTRACT_LSB0_UINT (insn, 32, 17, 1); \
f_misc_null_10 = EXTRACT_LSB0_UINT (insn, 32, 16, 5); \
f_ope1 = EXTRACT_LSB0_UINT (insn, 32, 11, 6); \
f_FRj_null = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
#define EXTRACT_IFMT_MCLRACC_0_VARS \
UINT f_pack; \
UINT f_ACC40Sk; \
UINT f_op; \
UINT f_A; \
UINT f_misc_null_10; \
UINT f_ope1; \
UINT f_FRj_null; \
unsigned int length;
#define EXTRACT_IFMT_MCLRACC_0_CODE \
length = 4; \ length = 4; \
f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
f_ACC40Sk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \ f_ACC40Sk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \

95
sim/frv/decode.c
View file

@ -776,7 +776,9 @@ static const struct insn_sem frvbf_insn_sem[] =
{ FRV_INSN_CMHTOB, FRVBF_INSN_CMHTOB, FRVBF_SFMT_CMHTOB }, { FRV_INSN_CMHTOB, FRVBF_INSN_CMHTOB, FRVBF_SFMT_CMHTOB },
{ FRV_INSN_MBTOHE, FRVBF_INSN_MBTOHE, FRVBF_SFMT_MBTOHE }, { FRV_INSN_MBTOHE, FRVBF_INSN_MBTOHE, FRVBF_SFMT_MBTOHE },
{ FRV_INSN_CMBTOHE, FRVBF_INSN_CMBTOHE, FRVBF_SFMT_CMBTOHE }, { FRV_INSN_CMBTOHE, FRVBF_INSN_CMBTOHE, FRVBF_SFMT_CMBTOHE },
{ FRV_INSN_MCLRACC, FRVBF_INSN_MCLRACC, FRVBF_SFMT_MCLRACC }, { FRV_INSN_MNOP, FRVBF_INSN_MNOP, FRVBF_SFMT_REI },
{ FRV_INSN_MCLRACC_0, FRVBF_INSN_MCLRACC_0, FRVBF_SFMT_MCLRACC_0 },
{ FRV_INSN_MCLRACC_1, FRVBF_INSN_MCLRACC_1, FRVBF_SFMT_MCLRACC_0 },
{ FRV_INSN_MRDACC, FRVBF_INSN_MRDACC, FRVBF_SFMT_MRDACC }, { FRV_INSN_MRDACC, FRVBF_INSN_MRDACC, FRVBF_SFMT_MRDACC },
{ FRV_INSN_MRDACCG, FRVBF_INSN_MRDACCG, FRVBF_SFMT_MRDACCG }, { FRV_INSN_MRDACCG, FRVBF_INSN_MRDACCG, FRVBF_SFMT_MRDACCG },
{ FRV_INSN_MWTACC, FRVBF_INSN_MWTACC, FRVBF_SFMT_MWTACC }, { FRV_INSN_MWTACC, FRVBF_INSN_MWTACC, FRVBF_SFMT_MWTACC },
@ -2142,7 +2144,87 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc,
case 56 : itype = FRVBF_INSN_MBTOH; goto extract_sfmt_mbtoh; case 56 : itype = FRVBF_INSN_MBTOH; goto extract_sfmt_mbtoh;
case 57 : itype = FRVBF_INSN_MHTOB; goto extract_sfmt_mhtob; case 57 : itype = FRVBF_INSN_MHTOB; goto extract_sfmt_mhtob;
case 58 : itype = FRVBF_INSN_MBTOHE; goto extract_sfmt_mbtohe; case 58 : itype = FRVBF_INSN_MBTOHE; goto extract_sfmt_mbtohe;
case 59 : itype = FRVBF_INSN_MCLRACC; goto extract_sfmt_mclracc; case 59 :
{
unsigned int val = (((insn >> 17) & (1 << 0)));
switch (val)
{
case 0 : itype = FRVBF_INSN_MCLRACC_0; goto extract_sfmt_mclracc_0;
case 1 :
{
unsigned int val = (((insn >> 25) & (63 << 0)));
switch (val)
{
case 0 : /* fall through */
case 1 : /* fall through */
case 2 : /* fall through */
case 3 : /* fall through */
case 4 : /* fall through */
case 5 : /* fall through */
case 6 : /* fall through */
case 7 : /* fall through */
case 8 : /* fall through */
case 9 : /* fall through */
case 10 : /* fall through */
case 11 : /* fall through */
case 12 : /* fall through */
case 13 : /* fall through */
case 14 : /* fall through */
case 15 : /* fall through */
case 16 : /* fall through */
case 17 : /* fall through */
case 18 : /* fall through */
case 19 : /* fall through */
case 20 : /* fall through */
case 21 : /* fall through */
case 22 : /* fall through */
case 23 : /* fall through */
case 24 : /* fall through */
case 25 : /* fall through */
case 26 : /* fall through */
case 27 : /* fall through */
case 28 : /* fall through */
case 29 : /* fall through */
case 30 : /* fall through */
case 31 : /* fall through */
case 32 : /* fall through */
case 33 : /* fall through */
case 34 : /* fall through */
case 35 : /* fall through */
case 36 : /* fall through */
case 37 : /* fall through */
case 38 : /* fall through */
case 39 : /* fall through */
case 40 : /* fall through */
case 41 : /* fall through */
case 42 : /* fall through */
case 43 : /* fall through */
case 44 : /* fall through */
case 45 : /* fall through */
case 46 : /* fall through */
case 47 : /* fall through */
case 48 : /* fall through */
case 49 : /* fall through */
case 50 : /* fall through */
case 51 : /* fall through */
case 52 : /* fall through */
case 53 : /* fall through */
case 54 : /* fall through */
case 55 : /* fall through */
case 56 : /* fall through */
case 57 : /* fall through */
case 58 : /* fall through */
case 59 : /* fall through */
case 60 : /* fall through */
case 61 : /* fall through */
case 62 : itype = FRVBF_INSN_MCLRACC_1; goto extract_sfmt_mclracc_0;
case 63 : itype = FRVBF_INSN_MNOP; goto extract_sfmt_rei;
default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
}
}
default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
}
}
case 60 : itype = FRVBF_INSN_MRDACC; goto extract_sfmt_mrdacc; case 60 : itype = FRVBF_INSN_MRDACC; goto extract_sfmt_mrdacc;
case 61 : itype = FRVBF_INSN_MWTACC; goto extract_sfmt_mwtacc; case 61 : itype = FRVBF_INSN_MWTACC; goto extract_sfmt_mwtacc;
case 62 : itype = FRVBF_INSN_MRDACCG; goto extract_sfmt_mrdaccg; case 62 : itype = FRVBF_INSN_MRDACCG; goto extract_sfmt_mrdaccg;
@ -10755,21 +10837,18 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc,
return idesc; return idesc;
} }
extract_sfmt_mclracc: extract_sfmt_mclracc_0:
{ {
const IDESC *idesc = &frvbf_insn_data[itype]; const IDESC *idesc = &frvbf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn; CGEN_INSN_INT insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_mclracc.f #define FLD(f) abuf->fields.sfmt_mdasaccs.f
UINT f_ACC40Sk; UINT f_ACC40Sk;
UINT f_A;
f_ACC40Sk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); f_ACC40Sk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
f_A = EXTRACT_LSB0_UINT (insn, 32, 17, 1);
/* Record the fields for the semantic handler. */ /* Record the fields for the semantic handler. */
FLD (f_A) = f_A;
FLD (f_ACC40Sk) = f_ACC40Sk; FLD (f_ACC40Sk) = f_ACC40Sk;
TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mclracc", "f_A 0x%x", 'x', f_A, "f_ACC40Sk 0x%x", 'x', f_ACC40Sk, (char *) 0)); TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mclracc_0", "f_ACC40Sk 0x%x", 'x', f_ACC40Sk, (char *) 0));
#undef FLD #undef FLD
return idesc; return idesc;

8
sim/frv/decode.h
View file

@ -218,9 +218,9 @@ typedef enum frvbf_insn_type {
, FRVBF_INSN_MEXPDHD, FRVBF_INSN_CMEXPDHD, FRVBF_INSN_MPACKH, FRVBF_INSN_MDPACKH , FRVBF_INSN_MEXPDHD, FRVBF_INSN_CMEXPDHD, FRVBF_INSN_MPACKH, FRVBF_INSN_MDPACKH
, FRVBF_INSN_MUNPACKH, FRVBF_INSN_MDUNPACKH, FRVBF_INSN_MBTOH, FRVBF_INSN_CMBTOH , FRVBF_INSN_MUNPACKH, FRVBF_INSN_MDUNPACKH, FRVBF_INSN_MBTOH, FRVBF_INSN_CMBTOH
, FRVBF_INSN_MHTOB, FRVBF_INSN_CMHTOB, FRVBF_INSN_MBTOHE, FRVBF_INSN_CMBTOHE , FRVBF_INSN_MHTOB, FRVBF_INSN_CMHTOB, FRVBF_INSN_MBTOHE, FRVBF_INSN_CMBTOHE
, FRVBF_INSN_MCLRACC, FRVBF_INSN_MRDACC, FRVBF_INSN_MRDACCG, FRVBF_INSN_MWTACC , FRVBF_INSN_MNOP, FRVBF_INSN_MCLRACC_0, FRVBF_INSN_MCLRACC_1, FRVBF_INSN_MRDACC
, FRVBF_INSN_MWTACCG, FRVBF_INSN_MCOP1, FRVBF_INSN_MCOP2, FRVBF_INSN_FNOP , FRVBF_INSN_MRDACCG, FRVBF_INSN_MWTACC, FRVBF_INSN_MWTACCG, FRVBF_INSN_MCOP1
, FRVBF_INSN__MAX , FRVBF_INSN_MCOP2, FRVBF_INSN_FNOP, FRVBF_INSN__MAX
} FRVBF_INSN_TYPE; } FRVBF_INSN_TYPE;
/* Enum declaration for semantic formats in cpu family frvbf. */ /* Enum declaration for semantic formats in cpu family frvbf. */
@ -288,7 +288,7 @@ typedef enum frvbf_sfmt_type {
, FRVBF_SFMT_MQCPXRS, FRVBF_SFMT_MEXPDHW, FRVBF_SFMT_CMEXPDHW, FRVBF_SFMT_MEXPDHD , FRVBF_SFMT_MQCPXRS, FRVBF_SFMT_MEXPDHW, FRVBF_SFMT_CMEXPDHW, FRVBF_SFMT_MEXPDHD
, FRVBF_SFMT_CMEXPDHD, FRVBF_SFMT_MPACKH, FRVBF_SFMT_MDPACKH, FRVBF_SFMT_MUNPACKH , FRVBF_SFMT_CMEXPDHD, FRVBF_SFMT_MPACKH, FRVBF_SFMT_MDPACKH, FRVBF_SFMT_MUNPACKH
, FRVBF_SFMT_MDUNPACKH, FRVBF_SFMT_MBTOH, FRVBF_SFMT_CMBTOH, FRVBF_SFMT_MHTOB , FRVBF_SFMT_MDUNPACKH, FRVBF_SFMT_MBTOH, FRVBF_SFMT_CMBTOH, FRVBF_SFMT_MHTOB
, FRVBF_SFMT_CMHTOB, FRVBF_SFMT_MBTOHE, FRVBF_SFMT_CMBTOHE, FRVBF_SFMT_MCLRACC , FRVBF_SFMT_CMHTOB, FRVBF_SFMT_MBTOHE, FRVBF_SFMT_CMBTOHE, FRVBF_SFMT_MCLRACC_0
, FRVBF_SFMT_MRDACC, FRVBF_SFMT_MRDACCG, FRVBF_SFMT_MWTACC, FRVBF_SFMT_MWTACCG , FRVBF_SFMT_MRDACC, FRVBF_SFMT_MRDACCG, FRVBF_SFMT_MWTACC, FRVBF_SFMT_MWTACCG
} FRVBF_SFMT_TYPE; } FRVBF_SFMT_TYPE;

212
sim/frv/model.c
View file

@ -11715,9 +11715,41 @@ model_frv_cmbtohe (SIM_CPU *current_cpu, void *sem_arg)
} }
static int static int
model_frv_mclracc (SIM_CPU *current_cpu, void *sem_arg) model_frv_mnop (SIM_CPU *current_cpu, void *sem_arg)
{ {
#define FLD(f) abuf->fields.sfmt_mclracc.f #define FLD(f) abuf->fields.fmt_empty.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
}
return cycles;
#undef FLD
}
static int
model_frv_mclracc_0 (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_mdasaccs.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
}
return cycles;
#undef FLD
}
static int
model_frv_mclracc_1 (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_mdasaccs.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc; const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0; int cycles = 0;
@ -29014,9 +29046,49 @@ model_fr500_cmbtohe (SIM_CPU *current_cpu, void *sem_arg)
} }
static int static int
model_fr500_mclracc (SIM_CPU *current_cpu, void *sem_arg) model_fr500_mnop (SIM_CPU *current_cpu, void *sem_arg)
{ {
#define FLD(f) abuf->fields.sfmt_mclracc.f #define FLD(f) abuf->fields.fmt_empty.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced);
}
return cycles;
#undef FLD
}
static int
model_fr500_mclracc_0 (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_mdasaccs.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
INT in_FRinti = -1;
INT in_FRintj = -1;
INT in_ACC40Si = -1;
INT in_ACCGi = -1;
INT out_FRintk = -1;
INT out_ACC40Sk = -1;
INT out_ACC40Uk = -1;
INT out_ACCGk = -1;
cycles += frvbf_model_fr500_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, in_ACC40Si, in_ACCGi, out_FRintk, out_ACC40Sk, out_ACC40Uk, out_ACCGk);
}
return cycles;
#undef FLD
}
static int
model_fr500_mclracc_1 (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_mdasaccs.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc; const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0; int cycles = 0;
@ -40878,9 +40950,41 @@ model_tomcat_cmbtohe (SIM_CPU *current_cpu, void *sem_arg)
} }
static int static int
model_tomcat_mclracc (SIM_CPU *current_cpu, void *sem_arg) model_tomcat_mnop (SIM_CPU *current_cpu, void *sem_arg)
{ {
#define FLD(f) abuf->fields.sfmt_mclracc.f #define FLD(f) abuf->fields.fmt_empty.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
}
return cycles;
#undef FLD
}
static int
model_tomcat_mclracc_0 (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_mdasaccs.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
}
return cycles;
#undef FLD
}
static int
model_tomcat_mclracc_1 (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_mdasaccs.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc; const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0; int cycles = 0;
@ -56783,9 +56887,45 @@ model_fr400_cmbtohe (SIM_CPU *current_cpu, void *sem_arg)
} }
static int static int
model_fr400_mclracc (SIM_CPU *current_cpu, void *sem_arg) model_fr400_mnop (SIM_CPU *current_cpu, void *sem_arg)
{ {
#define FLD(f) abuf->fields.sfmt_mclracc.f #define FLD(f) abuf->fields.fmt_empty.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
}
return cycles;
#undef FLD
}
static int
model_fr400_mclracc_0 (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_mdasaccs.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
INT in_ACC40Si = -1;
INT in_FRintj = -1;
INT out_ACC40Sk = -1;
INT out_FRintk = -1;
cycles += frvbf_model_fr400_u_media_4 (current_cpu, idesc, 0, referenced, in_ACC40Si, in_FRintj, out_ACC40Sk, out_FRintk);
}
return cycles;
#undef FLD
}
static int
model_fr400_mclracc_1 (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_mdasaccs.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc; const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0; int cycles = 0;
@ -68625,9 +68765,41 @@ model_simple_cmbtohe (SIM_CPU *current_cpu, void *sem_arg)
} }
static int static int
model_simple_mclracc (SIM_CPU *current_cpu, void *sem_arg) model_simple_mnop (SIM_CPU *current_cpu, void *sem_arg)
{ {
#define FLD(f) abuf->fields.sfmt_mclracc.f #define FLD(f) abuf->fields.fmt_empty.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
}
return cycles;
#undef FLD
}
static int
model_simple_mclracc_0 (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_mdasaccs.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
}
return cycles;
#undef FLD
}
static int
model_simple_mclracc_1 (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_mdasaccs.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc; const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0; int cycles = 0;
@ -69494,7 +69666,9 @@ static const INSN_TIMING frv_timing[] = {
{ FRVBF_INSN_CMHTOB, model_frv_cmhtob, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, { FRVBF_INSN_CMHTOB, model_frv_cmhtob, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_MBTOHE, model_frv_mbtohe, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, { FRVBF_INSN_MBTOHE, model_frv_mbtohe, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_CMBTOHE, model_frv_cmbtohe, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, { FRVBF_INSN_CMBTOHE, model_frv_cmbtohe, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_MCLRACC, model_frv_mclracc, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, { FRVBF_INSN_MNOP, model_frv_mnop, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_MCLRACC_0, model_frv_mclracc_0, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_MCLRACC_1, model_frv_mclracc_1, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_MRDACC, model_frv_mrdacc, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, { FRVBF_INSN_MRDACC, model_frv_mrdacc, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_MRDACCG, model_frv_mrdaccg, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, { FRVBF_INSN_MRDACCG, model_frv_mrdaccg, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_MWTACC, model_frv_mwtacc, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, { FRVBF_INSN_MWTACC, model_frv_mwtacc, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
@ -70243,7 +70417,9 @@ static const INSN_TIMING fr500_timing[] = {
{ FRVBF_INSN_CMHTOB, model_fr500_cmhtob, { { (int) UNIT_FR500_U_MEDIA_DUAL_HTOB, 1, 1 } } }, { FRVBF_INSN_CMHTOB, model_fr500_cmhtob, { { (int) UNIT_FR500_U_MEDIA_DUAL_HTOB, 1, 1 } } },
{ FRVBF_INSN_MBTOHE, model_fr500_mbtohe, { { (int) UNIT_FR500_U_MEDIA_DUAL_BTOHE, 1, 1 } } }, { FRVBF_INSN_MBTOHE, model_fr500_mbtohe, { { (int) UNIT_FR500_U_MEDIA_DUAL_BTOHE, 1, 1 } } },
{ FRVBF_INSN_CMBTOHE, model_fr500_cmbtohe, { { (int) UNIT_FR500_U_MEDIA_DUAL_BTOHE, 1, 1 } } }, { FRVBF_INSN_CMBTOHE, model_fr500_cmbtohe, { { (int) UNIT_FR500_U_MEDIA_DUAL_BTOHE, 1, 1 } } },
{ FRVBF_INSN_MCLRACC, model_fr500_mclracc, { { (int) UNIT_FR500_U_MEDIA, 1, 1 } } }, { FRVBF_INSN_MNOP, model_fr500_mnop, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_MCLRACC_0, model_fr500_mclracc_0, { { (int) UNIT_FR500_U_MEDIA, 1, 1 } } },
{ FRVBF_INSN_MCLRACC_1, model_fr500_mclracc_1, { { (int) UNIT_FR500_U_MEDIA, 1, 1 } } },
{ FRVBF_INSN_MRDACC, model_fr500_mrdacc, { { (int) UNIT_FR500_U_MEDIA, 1, 1 } } }, { FRVBF_INSN_MRDACC, model_fr500_mrdacc, { { (int) UNIT_FR500_U_MEDIA, 1, 1 } } },
{ FRVBF_INSN_MRDACCG, model_fr500_mrdaccg, { { (int) UNIT_FR500_U_MEDIA, 1, 1 } } }, { FRVBF_INSN_MRDACCG, model_fr500_mrdaccg, { { (int) UNIT_FR500_U_MEDIA, 1, 1 } } },
{ FRVBF_INSN_MWTACC, model_fr500_mwtacc, { { (int) UNIT_FR500_U_MEDIA, 1, 1 } } }, { FRVBF_INSN_MWTACC, model_fr500_mwtacc, { { (int) UNIT_FR500_U_MEDIA, 1, 1 } } },
@ -70992,7 +71168,9 @@ static const INSN_TIMING tomcat_timing[] = {
{ FRVBF_INSN_CMHTOB, model_tomcat_cmhtob, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, { FRVBF_INSN_CMHTOB, model_tomcat_cmhtob, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_MBTOHE, model_tomcat_mbtohe, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, { FRVBF_INSN_MBTOHE, model_tomcat_mbtohe, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_CMBTOHE, model_tomcat_cmbtohe, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, { FRVBF_INSN_CMBTOHE, model_tomcat_cmbtohe, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_MCLRACC, model_tomcat_mclracc, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, { FRVBF_INSN_MNOP, model_tomcat_mnop, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_MCLRACC_0, model_tomcat_mclracc_0, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_MCLRACC_1, model_tomcat_mclracc_1, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_MRDACC, model_tomcat_mrdacc, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, { FRVBF_INSN_MRDACC, model_tomcat_mrdacc, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_MRDACCG, model_tomcat_mrdaccg, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, { FRVBF_INSN_MRDACCG, model_tomcat_mrdaccg, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_MWTACC, model_tomcat_mwtacc, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, { FRVBF_INSN_MWTACC, model_tomcat_mwtacc, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
@ -71741,7 +71919,9 @@ static const INSN_TIMING fr400_timing[] = {
{ FRVBF_INSN_CMHTOB, model_fr400_cmhtob, { { (int) UNIT_FR400_U_MEDIA_DUAL_HTOB, 1, 1 } } }, { FRVBF_INSN_CMHTOB, model_fr400_cmhtob, { { (int) UNIT_FR400_U_MEDIA_DUAL_HTOB, 1, 1 } } },
{ FRVBF_INSN_MBTOHE, model_fr400_mbtohe, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, { FRVBF_INSN_MBTOHE, model_fr400_mbtohe, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_CMBTOHE, model_fr400_cmbtohe, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, { FRVBF_INSN_CMBTOHE, model_fr400_cmbtohe, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_MCLRACC, model_fr400_mclracc, { { (int) UNIT_FR400_U_MEDIA_4, 1, 1 } } }, { FRVBF_INSN_MNOP, model_fr400_mnop, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_MCLRACC_0, model_fr400_mclracc_0, { { (int) UNIT_FR400_U_MEDIA_4, 1, 1 } } },
{ FRVBF_INSN_MCLRACC_1, model_fr400_mclracc_1, { { (int) UNIT_FR400_U_MEDIA_4, 1, 1 } } },
{ FRVBF_INSN_MRDACC, model_fr400_mrdacc, { { (int) UNIT_FR400_U_MEDIA_4, 1, 1 } } }, { FRVBF_INSN_MRDACC, model_fr400_mrdacc, { { (int) UNIT_FR400_U_MEDIA_4, 1, 1 } } },
{ FRVBF_INSN_MRDACCG, model_fr400_mrdaccg, { { (int) UNIT_FR400_U_MEDIA_4_ACCG, 1, 1 } } }, { FRVBF_INSN_MRDACCG, model_fr400_mrdaccg, { { (int) UNIT_FR400_U_MEDIA_4_ACCG, 1, 1 } } },
{ FRVBF_INSN_MWTACC, model_fr400_mwtacc, { { (int) UNIT_FR400_U_MEDIA_4, 1, 1 } } }, { FRVBF_INSN_MWTACC, model_fr400_mwtacc, { { (int) UNIT_FR400_U_MEDIA_4, 1, 1 } } },
@ -72490,7 +72670,9 @@ static const INSN_TIMING simple_timing[] = {
{ FRVBF_INSN_CMHTOB, model_simple_cmhtob, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, { FRVBF_INSN_CMHTOB, model_simple_cmhtob, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_MBTOHE, model_simple_mbtohe, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, { FRVBF_INSN_MBTOHE, model_simple_mbtohe, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_CMBTOHE, model_simple_cmbtohe, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, { FRVBF_INSN_CMBTOHE, model_simple_cmbtohe, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_MCLRACC, model_simple_mclracc, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, { FRVBF_INSN_MNOP, model_simple_mnop, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_MCLRACC_0, model_simple_mclracc_0, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_MCLRACC_1, model_simple_mclracc_1, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_MRDACC, model_simple_mrdacc, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, { FRVBF_INSN_MRDACC, model_simple_mrdacc, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_MRDACCG, model_simple_mrdaccg, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, { FRVBF_INSN_MRDACCG, model_simple_mrdaccg, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_MWTACC, model_simple_mwtacc, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, { FRVBF_INSN_MWTACC, model_simple_mwtacc, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },

46
sim/frv/sem.c
View file

@ -27646,18 +27646,52 @@ if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
#undef FLD #undef FLD
} }
/* mclracc: mclracc$pack $ACC40Sk,$A */ /* mnop: mnop$pack */
static SEM_PC static SEM_PC
SEM_FN_NAME (frvbf,mclracc) (SIM_CPU *current_cpu, SEM_ARG sem_arg) SEM_FN_NAME (frvbf,mnop) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{ {
#define FLD(f) abuf->fields.sfmt_mclracc.f #define FLD(f) abuf->fields.fmt_empty.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg); ARGBUF *abuf = SEM_ARGBUF (sem_arg);
int UNUSED written = 0; int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr; IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
frvbf_clear_accumulators (current_cpu, FLD (f_ACC40Sk), FLD (f_A)); ((void) 0); /*nop*/
return vpc;
#undef FLD
}
/* mclracc-0: mclracc$pack $ACC40Sk,$A0 */
static SEM_PC
SEM_FN_NAME (frvbf,mclracc_0) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
#define FLD(f) abuf->fields.sfmt_mdasaccs.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
frvbf_clear_accumulators (current_cpu, FLD (f_ACC40Sk), 0);
return vpc;
#undef FLD
}
/* mclracc-1: mclracc$pack $ACC40Sk,$A1 */
static SEM_PC
SEM_FN_NAME (frvbf,mclracc_1) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
#define FLD(f) abuf->fields.sfmt_mdasaccs.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
frvbf_clear_accumulators (current_cpu, FLD (f_ACC40Sk), 1);
return vpc; return vpc;
#undef FLD #undef FLD
@ -28537,7 +28571,9 @@ static const struct sem_fn_desc sem_fns[] = {
{ FRVBF_INSN_CMHTOB, SEM_FN_NAME (frvbf,cmhtob) }, { FRVBF_INSN_CMHTOB, SEM_FN_NAME (frvbf,cmhtob) },
{ FRVBF_INSN_MBTOHE, SEM_FN_NAME (frvbf,mbtohe) }, { FRVBF_INSN_MBTOHE, SEM_FN_NAME (frvbf,mbtohe) },
{ FRVBF_INSN_CMBTOHE, SEM_FN_NAME (frvbf,cmbtohe) }, { FRVBF_INSN_CMBTOHE, SEM_FN_NAME (frvbf,cmbtohe) },
{ FRVBF_INSN_MCLRACC, SEM_FN_NAME (frvbf,mclracc) }, { FRVBF_INSN_MNOP, SEM_FN_NAME (frvbf,mnop) },
{ FRVBF_INSN_MCLRACC_0, SEM_FN_NAME (frvbf,mclracc_0) },
{ FRVBF_INSN_MCLRACC_1, SEM_FN_NAME (frvbf,mclracc_1) },
{ FRVBF_INSN_MRDACC, SEM_FN_NAME (frvbf,mrdacc) }, { FRVBF_INSN_MRDACC, SEM_FN_NAME (frvbf,mrdacc) },
{ FRVBF_INSN_MRDACCG, SEM_FN_NAME (frvbf,mrdaccg) }, { FRVBF_INSN_MRDACCG, SEM_FN_NAME (frvbf,mrdaccg) },
{ FRVBF_INSN_MWTACC, SEM_FN_NAME (frvbf,mwtacc) }, { FRVBF_INSN_MWTACC, SEM_FN_NAME (frvbf,mwtacc) },