darkkirb/old-cross-binutils
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity

2003-09-03 Dave Brolley <brolley@redhat.com>

Browse source 
* frv-*: Regenerated.
This commit is contained in:
Dave Brolley 2003-09-03 23:09:56 +00:00
parent 8caa9169eb
commit ecd51ad39f
8 changed files with 443 additions and 319 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

4
opcodes/ChangeLog
View file

@ -1,3 +1,7 @@
2003-09-03 Dave Brolley <brolley@redhat.com>
* frv-*: Regenerated.
2003-09-02 Alan Modra <amodra@bigpond.net.au>
* ppc-opc.c (powerpc_opcodes): Combine identical PPC403/BOOKE entries.

56
opcodes/frv-asm.c
View file

@ -66,6 +66,12 @@ static const char * parse_u12
PARAMS ((CGEN_CPU_DESC, const char **, int, long *));
static const char * parse_even_register
PARAMS ((CGEN_CPU_DESC, const char **, CGEN_KEYWORD *, long *));
static const char * parse_A0
PARAMS ((CGEN_CPU_DESC, const char **, int, long *));
static const char * parse_A1
PARAMS ((CGEN_CPU_DESC, const char **, int, long *));
static const char * parse_A
PARAMS ((CGEN_CPU_DESC, const char **, int, long *, long));
static const char *
parse_ulo16 (cd, strp, opindex, valuep)
@ -348,6 +354,49 @@ parse_u12 (cd, strp, opindex, valuep)
}
}
static const char *
parse_A (cd, strp, opindex, valuep, A)
CGEN_CPU_DESC cd;
const char **strp;
int opindex;
long *valuep;
long A;
{
const char *errmsg;
if (**strp == '#')
++*strp;
errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, valuep);
if (errmsg)
return errmsg;
if (*valuep != A)
return "Value of A operand must be 0 or 1";
return NULL;
}
static const char *
parse_A0 (cd, strp, opindex, valuep)
CGEN_CPU_DESC cd;
const char **strp;
int opindex;
long *valuep;
{
return parse_A (cd, strp, opindex, valuep, 0);
}
static const char *
parse_A1 (cd, strp, opindex, valuep)
CGEN_CPU_DESC cd;
const char **strp;
int opindex;
long *valuep;
{
return parse_A (cd, strp, opindex, valuep, 1);
}
static const char *
parse_even_register (cd, strP, tableP, valueP)
CGEN_CPU_DESC cd;
@ -399,8 +448,11 @@ frv_cgen_parse_operand (cd, opindex, strp, fields)
switch (opindex)
{
case FRV_OPERAND_A :
errmsg = cgen_parse_unsigned_integer (cd, strp, FRV_OPERAND_A, &fields->f_A);
case FRV_OPERAND_A0 :
errmsg = parse_A0 (cd, strp, FRV_OPERAND_A0, &fields->f_A);
break;
case FRV_OPERAND_A1 :
errmsg = parse_A1 (cd, strp, FRV_OPERAND_A1, &fields->f_A);
break;
case FRV_OPERAND_ACC40SI :
errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_acc_names, & fields->f_ACC40Si);

544
opcodes/frv-desc.c
View file

File diff suppressed because it is too large Load diff

24
opcodes/frv-desc.h
View file

@ -541,9 +541,11 @@ typedef enum isa_attr {
/* Enum declaration for parallel execution pipeline selection. */
typedef enum unit_attr {
UNIT_NIL, UNIT_I0, UNIT_I1, UNIT_I01
, UNIT_FM0, UNIT_FM1, UNIT_FM01, UNIT_B0
, UNIT_B1, UNIT_B01, UNIT_C, UNIT_MULT_DIV
, UNIT_LOAD, UNIT_NUM_UNITS
, UNIT_IALL, UNIT_FM0, UNIT_FM1, UNIT_FM01
, UNIT_FMALL, UNIT_FMLOW, UNIT_B0, UNIT_B1
, UNIT_B01, UNIT_C, UNIT_MULT_DIV, UNIT_LOAD
, UNIT_STORE, UNIT_SCAN, UNIT_DCPL, UNIT_MDUALACC
, UNIT_MCLRACC_1, UNIT_NUM_UNITS
} UNIT_ATTR;
/* Enum declaration for fr400 major insn categories. */
@ -676,17 +678,17 @@ typedef enum cgen_operand_type {
, FRV_OPERAND_U16, FRV_OPERAND_S16, FRV_OPERAND_S6, FRV_OPERAND_S6_1
, FRV_OPERAND_U6, FRV_OPERAND_S5, FRV_OPERAND_COND, FRV_OPERAND_CCOND
, FRV_OPERAND_HINT, FRV_OPERAND_HINT_TAKEN, FRV_OPERAND_HINT_NOT_TAKEN, FRV_OPERAND_LI
, FRV_OPERAND_LOCK, FRV_OPERAND_DEBUG, FRV_OPERAND_A, FRV_OPERAND_AE
, FRV_OPERAND_LABEL16, FRV_OPERAND_LABEL24, FRV_OPERAND_FRINTIEVEN, FRV_OPERAND_FRINTJEVEN
, FRV_OPERAND_FRINTKEVEN, FRV_OPERAND_D12, FRV_OPERAND_S12, FRV_OPERAND_U12
, FRV_OPERAND_SPR, FRV_OPERAND_ULO16, FRV_OPERAND_SLO16, FRV_OPERAND_UHI16
, FRV_OPERAND_PSR_ESR, FRV_OPERAND_PSR_S, FRV_OPERAND_PSR_PS, FRV_OPERAND_PSR_ET
, FRV_OPERAND_BPSR_BS, FRV_OPERAND_BPSR_BET, FRV_OPERAND_TBR_TBA, FRV_OPERAND_TBR_TT
, FRV_OPERAND_MAX
, FRV_OPERAND_LOCK, FRV_OPERAND_DEBUG, FRV_OPERAND_AE, FRV_OPERAND_LABEL16
, FRV_OPERAND_LABEL24, FRV_OPERAND_A0, FRV_OPERAND_A1, FRV_OPERAND_FRINTIEVEN
, FRV_OPERAND_FRINTJEVEN, FRV_OPERAND_FRINTKEVEN, FRV_OPERAND_D12, FRV_OPERAND_S12
, FRV_OPERAND_U12, FRV_OPERAND_SPR, FRV_OPERAND_ULO16, FRV_OPERAND_SLO16
, FRV_OPERAND_UHI16, FRV_OPERAND_PSR_ESR, FRV_OPERAND_PSR_S, FRV_OPERAND_PSR_PS
, FRV_OPERAND_PSR_ET, FRV_OPERAND_BPSR_BS, FRV_OPERAND_BPSR_BET, FRV_OPERAND_TBR_TBA
, FRV_OPERAND_TBR_TT, FRV_OPERAND_MAX
} CGEN_OPERAND_TYPE;
/* Number of operands types. */
#define MAX_OPERANDS 80
#define MAX_OPERANDS 81
/* Maximum number of operands referenced by any insn. */
#define MAX_OPERAND_INSTANCES 8

7
opcodes/frv-dis.c
View file

@ -151,8 +151,11 @@ frv_cgen_print_operand (cd, opindex, xinfo, fields, attrs, pc, length)
switch (opindex)
{
case FRV_OPERAND_A :
print_normal (cd, info, fields->f_A, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
case FRV_OPERAND_A0 :
print_normal (cd, info, fields->f_A, 0, pc, length);
break;
case FRV_OPERAND_A1 :
print_normal (cd, info, fields->f_A, 0, pc, length);
break;
case FRV_OPERAND_ACC40SI :
print_keyword (cd, info, & frv_cgen_opval_acc_names, fields->f_ACC40Si, 0);

30
opcodes/frv-ibld.c
View file

@ -571,7 +571,10 @@ frv_cgen_insert_operand (cd, opindex, fields, buffer, pc)
switch (opindex)
{
case FRV_OPERAND_A :
case FRV_OPERAND_A0 :
errmsg = insert_normal (cd, fields->f_A, 0, 0, 17, 1, 32, total_length, buffer);
break;
case FRV_OPERAND_A1 :
errmsg = insert_normal (cd, fields->f_A, 0, 0, 17, 1, 32, total_length, buffer);
break;
case FRV_OPERAND_ACC40SI :
@ -870,7 +873,10 @@ frv_cgen_extract_operand (cd, opindex, ex_info, insn_value, fields, pc)
switch (opindex)
{
case FRV_OPERAND_A :
case FRV_OPERAND_A0 :
length = extract_normal (cd, ex_info, insn_value, 0, 0, 17, 1, 32, total_length, pc, & fields->f_A);
break;
case FRV_OPERAND_A1 :
length = extract_normal (cd, ex_info, insn_value, 0, 0, 17, 1, 32, total_length, pc, & fields->f_A);
break;
case FRV_OPERAND_ACC40SI :
@ -1158,7 +1164,10 @@ frv_cgen_get_int_operand (cd, opindex, fields)
switch (opindex)
{
case FRV_OPERAND_A :
case FRV_OPERAND_A0 :
value = fields->f_A;
break;
case FRV_OPERAND_A1 :
value = fields->f_A;
break;
case FRV_OPERAND_ACC40SI :
@ -1392,7 +1401,10 @@ frv_cgen_get_vma_operand (cd, opindex, fields)
switch (opindex)
{
case FRV_OPERAND_A :
case FRV_OPERAND_A0 :
value = fields->f_A;
break;
case FRV_OPERAND_A1 :
value = fields->f_A;
break;
case FRV_OPERAND_ACC40SI :
@ -1635,7 +1647,10 @@ frv_cgen_set_int_operand (cd, opindex, fields, value)
{
switch (opindex)
{
case FRV_OPERAND_A :
case FRV_OPERAND_A0 :
fields->f_A = value;
break;
case FRV_OPERAND_A1 :
fields->f_A = value;
break;
case FRV_OPERAND_ACC40SI :
@ -1866,7 +1881,10 @@ frv_cgen_set_vma_operand (cd, opindex, fields, value)
{
switch (opindex)
{
case FRV_OPERAND_A :
case FRV_OPERAND_A0 :
fields->f_A = value;
break;
case FRV_OPERAND_A1 :
fields->f_A = value;
break;
case FRV_OPERAND_ACC40SI :

90
opcodes/frv-opc.c
View file

@ -141,7 +141,7 @@ frv_is_media_insn (const CGEN_INSN *insn)
/* This table represents the allowable packing for vliw insns for the fr400.
The fr400 has only 2 vliw slots. Represent this by not allowing any insns
in slots 2 and 3.
in the extra slots.
Subsets of any given row are also allowed. */
static VLIW_COMBO fr400_allowed_vliw[] =
{
@ -184,15 +184,23 @@ static CGEN_ATTR_VALUE_TYPE fr400_unit_mapping[] =
/* I0 */ UNIT_I0,
/* I1 */ UNIT_I1,
/* I01 */ UNIT_I01,
/* IALL */ UNIT_I01, /* only I0 and I1 units */
/* FM0 */ UNIT_FM0,
/* FM1 */ UNIT_FM1,
/* FM01 */ UNIT_FM01,
/* FMALL */ UNIT_FM01,/* Only F0,F1,M0,M1 units */
/* FMLOW */ UNIT_FM0, /* Only F0,M0 units */
/* B0 */ UNIT_B0, /* branches only in B0 unit. */
/* B1 */ UNIT_B0,
/* B01 */ UNIT_B0,
/* C */ UNIT_C,
/* MULT-DIV */ UNIT_I0, /* multiply and divide only in I0 unit. */
/* LOAD */ UNIT_I0 /* load only in I0 unit. */
/* MULT-DIV */ UNIT_I0, /* multiply and divide only in I0 unit. */
/* LOAD */ UNIT_I0, /* load only in I0 unit. */
/* STORE */ UNIT_I0, /* store only in I0 unit. */
/* SCAN */ UNIT_I0, /* scan only in I0 unit. */
/* DCPL */ UNIT_C, /* dcpl only in C unit. */
/* MDUALACC */ UNIT_FM0, /* media dual acc insn only in FM0 unit. */
/* MCLRACC-1*/ UNIT_FM0 /* mclracc,A==1 insn only in FM0 unit. */
};
static CGEN_ATTR_VALUE_TYPE fr500_unit_mapping[] =
@ -202,15 +210,23 @@ static CGEN_ATTR_VALUE_TYPE fr500_unit_mapping[] =
/* I0 */ UNIT_I0,
/* I1 */ UNIT_I1,
/* I01 */ UNIT_I01,
/* IALL */ UNIT_I01, /* only I0 and I1 units */
/* FM0 */ UNIT_FM0,
/* FM1 */ UNIT_FM1,
/* FM01 */ UNIT_FM01,
/* FMALL */ UNIT_FM01,/* Only F0,F1,M0,M1 units */
/* FMLOW */ UNIT_FM0, /* Only F0,M0 units */
/* B0 */ UNIT_B0,
/* B1 */ UNIT_B1,
/* B01 */ UNIT_B01,
/* C */ UNIT_C,
/* MULT-DIV */ UNIT_I01, /* multiply and divide in I0 or I1 unit. */
/* LOAD */ UNIT_I01 /* load in I0 or I1 unit. */
/* LOAD */ UNIT_I01, /* load in I0 or I1 unit. */
/* STORE */ UNIT_I0, /* store only in I0 unit. */
/* SCAN */ UNIT_I01, /* scan in I0 or I1 unit. */
/* DCPL */ UNIT_C, /* dcpl only in C unit. */
/* MDUALACC */ UNIT_FM0, /* media dual acc insn only in FM0 unit. */
/* MCLRACC-1*/ UNIT_FM01 /* mclracc,A==1 in FM0 or FM1 unit. */
};
void
@ -493,10 +509,15 @@ frv_vliw_add_insn (FRV_VLIW *vliw, const CGEN_INSN *insn)
if (unit == UNIT_NIL)
abort (); /* no UNIT specified for this insn in frv.cpu */
if (vliw->mach == bfd_mach_fr400)
major = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR400_MAJOR);
else
major = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR500_MAJOR);
switch (vliw->mach)
{
case bfd_mach_fr400:
major = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR400_MAJOR);
break;
default:
major = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR500_MAJOR);
break;
}
if (index <= 0)
{
@ -1133,8 +1154,12 @@ static const CGEN_IFMT ifmt_cmbtohe = {
32, 32, 0x1fff0c0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_FRI_NULL) }, { F (F_CCI) }, { F (F_COND) }, { F (F_OPE4) }, { F (F_FRJ) }, { 0 } }
};
static const CGEN_IFMT ifmt_mclracc = {
32, 32, 0x1fdffff, { { F (F_PACK) }, { F (F_ACC40SK) }, { F (F_OP) }, { F (F_A) }, { F (F_MISC_NULL_10) }, { F (F_OPE1) }, { F (F_FRJ_NULL) }, { 0 } }
static const CGEN_IFMT ifmt_mnop = {
32, 32, 0x7fffffff, { { F (F_PACK) }, { F (F_ACC40SK) }, { F (F_OP) }, { F (F_A) }, { F (F_MISC_NULL_10) }, { F (F_OPE1) }, { F (F_FRJ_NULL) }, { 0 } }
};
static const CGEN_IFMT ifmt_mclracc_0 = {
32, 32, 0x1ffffff, { { F (F_PACK) }, { F (F_ACC40SK) }, { F (F_OP) }, { F (F_A) }, { F (F_MISC_NULL_10) }, { F (F_OPE1) }, { F (F_FRJ_NULL) }, { 0 } }
};
static const CGEN_IFMT ifmt_mrdacc = {
@ -5560,11 +5585,23 @@ static const CGEN_OPCODE frv_cgen_insn_opcode_table[MAX_INSNS] =
{ { MNEM, OP (PACK), ' ', OP (FRINTJ), ',', OP (FRINTK), ',', OP (CCI), ',', OP (COND), 0 } },
& ifmt_cmbtohe, { 0x1dc0080 }
},
/* mclracc$pack $ACC40Sk,$A */
/* mnop$pack */
{
{ 0, 0, 0, 0 },
{ { MNEM, OP (PACK), ' ', OP (ACC40SK), ',', OP (A), 0 } },
& ifmt_mclracc, { 0x1ec0ec0 }
{ { MNEM, OP (PACK), 0 } },
& ifmt_mnop, { 0x7fee0ec0 }
},
/* mclracc$pack $ACC40Sk,$A0 */
{
{ 0, 0, 0, 0 },
{ { MNEM, OP (PACK), ' ', OP (ACC40SK), ',', OP (A0), 0 } },
& ifmt_mclracc_0, { 0x1ec0ec0 }
},
/* mclracc$pack $ACC40Sk,$A1 */
{
{ 0, 0, 0, 0 },
{ { MNEM, OP (PACK), ' ', OP (ACC40SK), ',', OP (A1), 0 } },
& ifmt_mclracc_0, { 0x1ee0ec0 }
},
/* mrdacc$pack $ACC40Si,$FRintk */
{
@ -5626,10 +5663,6 @@ static const CGEN_IFMT ifmt_nop = {
32, 32, 0x7fffffff, { { F (F_PACK) }, { F (F_GRK) }, { F (F_OP) }, { F (F_GRI) }, { F (F_D12) }, { 0 } }
};
static const CGEN_IFMT ifmt_mnop = {
32, 32, 0x7fffffff, { { F (F_PACK) }, { F (F_ACC40SK) }, { F (F_OP) }, { F (F_A) }, { F (F_MISC_NULL_10) }, { F (F_OPE1) }, { F (F_FRJ_NULL) }, { 0 } }
};
static const CGEN_IFMT ifmt_ret = {
32, 32, 0x7fffffff, { { F (F_PACK) }, { F (F_INT_CC) }, { F (F_ICCI_2_NULL) }, { F (F_OP) }, { F (F_HINT) }, { F (F_OPE3) }, { F (F_CCOND_NULL) }, { F (F_S12_NULL) }, { 0 } }
};
@ -5678,12 +5711,7 @@ static const CGEN_IBASE frv_cgen_macro_insn_table[] =
/* nop$pack */
{
-1, "nop", "nop", 32,
{ 0|A(ALIAS), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
},
/* mnop$pack */
{
-1, "mnop", "mnop", 32,
{ 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_M_3 } }
{ 0|A(ALIAS), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
},
/* ret$pack */
{
@ -5693,27 +5721,27 @@ static const CGEN_IBASE frv_cgen_macro_insn_table[] =
/* cmp$pack $GRi,$GRj,$ICCi_1 */
{
-1, "cmp", "cmp", 32,
{ 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
{ 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
},
/* cmpi$pack $GRi,$s10,$ICCi_1 */
{
-1, "cmpi", "cmpi", 32,
{ 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
{ 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
},
/* ccmp$pack $GRi,$GRj,$CCi,$cond */
{
-1, "ccmp", "ccmp", 32,
{ 0|A(CONDITIONAL)|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
{ 0|A(CONDITIONAL)|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
},
/* mov$pack $GRi,$GRk */
{
-1, "mov", "mov", 32,
{ 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
{ 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
},
/* cmov$pack $GRi,$GRk,$CCi,$cond */
{
-1, "cmov", "cmov", 32,
{ 0|A(CONDITIONAL)|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
{ 0|A(CONDITIONAL)|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
},
};
@ -5727,12 +5755,6 @@ static const CGEN_OPCODE frv_cgen_macro_insn_opcode_table[] =
{ { MNEM, OP (PACK), 0 } },
& ifmt_nop, { 0x880000 }
},
/* mnop$pack */
{
{ 0, 0, 0, 0 },
{ { MNEM, OP (PACK), 0 } },
& ifmt_mnop, { 0x7fee0ec0 }
},
/* ret$pack */
{
{ 0, 0, 0, 0 },

7
opcodes/frv-opc.h
View file

@ -244,9 +244,10 @@ typedef enum cgen_insn_type {
, FRV_INSN_MQCPXIU, FRV_INSN_MEXPDHW, FRV_INSN_CMEXPDHW, FRV_INSN_MEXPDHD
, FRV_INSN_CMEXPDHD, FRV_INSN_MPACKH, FRV_INSN_MDPACKH, FRV_INSN_MUNPACKH
, FRV_INSN_MDUNPACKH, FRV_INSN_MBTOH, FRV_INSN_CMBTOH, FRV_INSN_MHTOB
, FRV_INSN_CMHTOB, FRV_INSN_MBTOHE, FRV_INSN_CMBTOHE, FRV_INSN_MCLRACC
, FRV_INSN_MRDACC, FRV_INSN_MRDACCG, FRV_INSN_MWTACC, FRV_INSN_MWTACCG
, FRV_INSN_MCOP1, FRV_INSN_MCOP2, FRV_INSN_FNOP
, FRV_INSN_CMHTOB, FRV_INSN_MBTOHE, FRV_INSN_CMBTOHE, FRV_INSN_MNOP
, FRV_INSN_MCLRACC_0, FRV_INSN_MCLRACC_1, FRV_INSN_MRDACC, FRV_INSN_MRDACCG
, FRV_INSN_MWTACC, FRV_INSN_MWTACCG, FRV_INSN_MCOP1, FRV_INSN_MCOP2
, FRV_INSN_FNOP
} CGEN_INSN_TYPE;
/* Index of `invalid' insn place holder. */