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(profile_print_core): Simplify by calling sim_core_map_to_str.

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* sim-core.h (sim_core_map_to_str): Declare.
	* sim-core.c (sim_core_map_to_str): Make non-static.
This commit is contained in:
Doug Evans 1998-02-25 07:36:23 +00:00
parent 3910fb4a51
commit 751197f231
3 changed files with 51 additions and 44 deletions
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2
sim/common/sim-core.c
View file

@ -127,7 +127,7 @@ sim_core_signal (SIM_DESC sd,
#endif #endif
STATIC_INLINE_SIM_CORE\ EXTERN_SIM_CORE\
(const char *) (const char *)
sim_core_map_to_str (sim_core_maps map) sim_core_map_to_str (sim_core_maps map)
{ {

78
sim/common/sim-core.h
View file

@ -138,6 +138,13 @@ EXTERN_SIM_CORE\
void *optional_buffer); void *optional_buffer);
/* Utility to return the name of a map. */
EXTERN_SIM_CORE\
(const char *) sim_core_map_to_str
(sim_core_maps);
/* Delete a memory space within the core. /* Delete a memory space within the core.
*/ */
@ -240,38 +247,45 @@ EXTERN_SIM_CORE\
order (including xor endian). Should the transfer fail, the order (including xor endian). Should the transfer fail, the
operation shall abort (no return). operation shall abort (no return).
The aligned alternative makes the assumption that that the address ALIGNED assumes yhat the specified ADDRESS is correctly alligned
is N byte aligned (no alignment checks are made). for an N byte transfer (no alignment checks are made). Passing an
incorrectly aligned ADDRESS is erroneous.
The unaligned alternative checks the address for correct byte UNALIGNED checks/modifies the ADDRESS according to the requirements
alignment. Action, as defined by WITH_ALIGNMENT, being taken of an N byte transfer. Action, as defined by WITH_ALIGNMENT, being
should the check fail. taken should the check fail.
MISSALIGNED transfers the data regardless.
Misaligned xor-endian accesses are broken into a sequence of Misaligned xor-endian accesses are broken into a sequence of
transfers each <= WITH_XOR_ENDIAN bytes */ transfers each <= WITH_XOR_ENDIAN bytes */
#define DECLARE_SIM_CORE_WRITE_N(ALIGNMENT,N) \ #define DECLARE_SIM_CORE_WRITE_N(ALIGNMENT,N,M) \
INLINE_SIM_CORE\ INLINE_SIM_CORE\
(void) sim_core_write_##ALIGNMENT##_##N \ (void) sim_core_write_##ALIGNMENT##_##N \
(sim_cpu *cpu, \ (sim_cpu *cpu, \
sim_cia cia, \ sim_cia cia, \
sim_core_maps map, \ sim_core_maps map, \
address_word addr, \ address_word addr, \
unsigned_##N val); unsigned_##M val);
DECLARE_SIM_CORE_WRITE_N(aligned,1) DECLARE_SIM_CORE_WRITE_N(aligned,1,1)
DECLARE_SIM_CORE_WRITE_N(aligned,2) DECLARE_SIM_CORE_WRITE_N(aligned,2,2)
DECLARE_SIM_CORE_WRITE_N(aligned,4) DECLARE_SIM_CORE_WRITE_N(aligned,4,4)
DECLARE_SIM_CORE_WRITE_N(aligned,8) DECLARE_SIM_CORE_WRITE_N(aligned,8,8)
DECLARE_SIM_CORE_WRITE_N(aligned,16) DECLARE_SIM_CORE_WRITE_N(aligned,16,16)
DECLARE_SIM_CORE_WRITE_N(unaligned,1) #define sim_core_write_unaligned_1 sim_core_write_aligned_1
DECLARE_SIM_CORE_WRITE_N(unaligned,2) DECLARE_SIM_CORE_WRITE_N(unaligned,2,2)
DECLARE_SIM_CORE_WRITE_N(unaligned,4) DECLARE_SIM_CORE_WRITE_N(unaligned,4,4)
DECLARE_SIM_CORE_WRITE_N(unaligned,8) DECLARE_SIM_CORE_WRITE_N(unaligned,8,8)
DECLARE_SIM_CORE_WRITE_N(unaligned,16) DECLARE_SIM_CORE_WRITE_N(unaligned,16,16)
DECLARE_SIM_CORE_WRITE_N(misaligned,3,4)
DECLARE_SIM_CORE_WRITE_N(misaligned,5,8)
DECLARE_SIM_CORE_WRITE_N(misaligned,6,8)
DECLARE_SIM_CORE_WRITE_N(misaligned,7,8)
#define sim_core_write_1 sim_core_write_aligned_1 #define sim_core_write_1 sim_core_write_aligned_1
#define sim_core_write_2 sim_core_write_aligned_2 #define sim_core_write_2 sim_core_write_aligned_2
@ -286,25 +300,31 @@ DECLARE_SIM_CORE_WRITE_N(unaligned,16)
#undef DECLARE_SIM_CORE_WRITE_N #undef DECLARE_SIM_CORE_WRITE_N
#define DECLARE_SIM_CORE_READ_N(ALIGNMENT,N) \ #define DECLARE_SIM_CORE_READ_N(ALIGNMENT,N,M) \
INLINE_SIM_CORE\ INLINE_SIM_CORE\
(unsigned_##N) sim_core_read_##ALIGNMENT##_##N \ (unsigned_##M) sim_core_read_##ALIGNMENT##_##N \
(sim_cpu *cpu, \ (sim_cpu *cpu, \
sim_cia cia, \ sim_cia cia, \
sim_core_maps map, \ sim_core_maps map, \
address_word addr); address_word addr);
DECLARE_SIM_CORE_READ_N(aligned,1) DECLARE_SIM_CORE_READ_N(aligned,1,1)
DECLARE_SIM_CORE_READ_N(aligned,2) DECLARE_SIM_CORE_READ_N(aligned,2,2)
DECLARE_SIM_CORE_READ_N(aligned,4) DECLARE_SIM_CORE_READ_N(aligned,4,4)
DECLARE_SIM_CORE_READ_N(aligned,8) DECLARE_SIM_CORE_READ_N(aligned,8,8)
DECLARE_SIM_CORE_READ_N(aligned,16) DECLARE_SIM_CORE_READ_N(aligned,16,16)
#define sim_core_read_unaligned_1 sim_core_read_aligned_1
DECLARE_SIM_CORE_READ_N(unaligned,2,2)
DECLARE_SIM_CORE_READ_N(unaligned,4,4)
DECLARE_SIM_CORE_READ_N(unaligned,8,8)
DECLARE_SIM_CORE_READ_N(unaligned,16,16)
DECLARE_SIM_CORE_READ_N(misaligned,3,4)
DECLARE_SIM_CORE_READ_N(misaligned,5,8)
DECLARE_SIM_CORE_READ_N(misaligned,6,8)
DECLARE_SIM_CORE_READ_N(misaligned,7,8)
DECLARE_SIM_CORE_READ_N(unaligned,1)
DECLARE_SIM_CORE_READ_N(unaligned,2)
DECLARE_SIM_CORE_READ_N(unaligned,4)
DECLARE_SIM_CORE_READ_N(unaligned,8)
DECLARE_SIM_CORE_READ_N(unaligned,16)
#define sim_core_read_1 sim_core_read_aligned_1 #define sim_core_read_1 sim_core_read_aligned_1
#define sim_core_read_2 sim_core_read_aligned_2 #define sim_core_read_2 sim_core_read_aligned_2

15
sim/common/sim-profile.c
View file

@ -711,20 +711,7 @@ profile_print_core (sim_cpu *cpu, int verbose)
{ {
if (PROFILE_CORE_COUNT (data) [map] != 0) if (PROFILE_CORE_COUNT (data) [map] != 0)
{ {
switch (map) sim_io_printf (sd, "%10s:", sim_core_map_to_str (map));
{
case sim_core_read_map:
sim_io_printf (sd, " read:");
break;
case sim_core_write_map:
sim_io_printf (sd, " write:");
break;
case sim_core_execute_map:
sim_io_printf (sd, " exec:");
break;
case nr_sim_core_maps:
; /* ignore */
}
sim_io_printf (sd, "%*s: ", sim_io_printf (sd, "%*s: ",
max_val < 10000 ? 5 : 10, max_val < 10000 ? 5 : 10,
COMMAS (PROFILE_CORE_COUNT (data) [map])); COMMAS (PROFILE_CORE_COUNT (data) [map]));