1996-11-27 16:25:03 +00:00
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Wed Nov 27 09:20:42 1996 Jeffrey A Law (law@cygnus.com)
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1996-11-27 17:19:44 +00:00
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* simops.c: Implement remaining 4 byte instructions.
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* simops.c: Implement remaining 3 byte instructions.
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1996-11-27 16:51:30 +00:00
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1996-11-27 16:25:03 +00:00
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* simops.c: Implement remaining 2 byte instructions. Call
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abort for instructions we're not implementing now.
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1996-11-26 22:58:24 +00:00
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Tue Nov 26 15:43:41 1996 Jeffrey A Law (law@cygnus.com)
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1996-11-27 07:20:36 +00:00
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* simops.c: Implement lots of random instructions.
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1996-11-27 05:29:49 +00:00
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* simops.c: Implement "movm" and "bCC" insns.
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1996-11-27 00:53:25 +00:00
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* mn10300_sim.h (_state): Add another register (MDR).
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(REG_MDR): Define.
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* simops.c: Implement "cmp", "calls", "rets", "jmp" and
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a few additional random insns.
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1996-11-26 22:58:24 +00:00
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* mn10300_sim.h (PSW_*): Define for CC status tracking.
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(REG_D0, REG_A0, REG_SP): Define.
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* simops.c: Implement "add", "addc" and a few other random
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instructions.
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1996-11-26 20:40:19 +00:00
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* gencode.c, interp.c: Snapshot current simulator code.
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1996-11-25 19:52:08 +00:00
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Mon Nov 25 12:46:38 1996 Jeffrey A Law (law@cygnus.com)
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* Makefile.in, config.in, configure, configure.in: New files.
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* gencode.c, interp.c, mn10300_sim.h, simops.c: New files.
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