2011-11-02 03:09:11 +00:00
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2011-11-01 DJ Delorie <dj@redhat.com>
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* Makefile.am (TARGET_LIBOPCODES_CFILES): Add rl78-decode.c and
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rl78-dis.c.
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(MAINTAINERCLEANFILES): Add rl78-decode.c.
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(rl78-decode.c): New rule, built from rl78-decode.opc and opc2c.
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* Makefile.in: Regenerate.
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* configure.in: Add bfd_rl78_arch case.
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* configure: Regenerate.
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* disassemble.c: Define ARCH_rl78.
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(disassembler): Add ARCH_rl78 case.
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* rl78-decode.c: New file.
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* rl78-decode.opc: New file.
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* rl78-dis.c: New file.
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opcodes/
* ppc-opc.c (powerpc_opcodes) <drrndq, drrndq., dtstexq, dctqpq,
dctqpq., dctfixq, dctfixq., dxexq, dxexq., dtstsfq, dcffixq, dcffixq.,
diexq, diexq.>: Use FRT, FRA, FRB and FRBp repsectively on DFP quad
instructions.
2011-10-27 15:44:01 +00:00
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2011-10-27 Peter Bergner <bergner@vnet.ibm.com>
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* ppc-opc.c (powerpc_opcodes) <drrndq, drrndq., dtstexq, dctqpq,
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dctqpq., dctfixq, dctfixq., dxexq, dxexq., dtstsfq, dcffixq, dcffixq.,
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diexq, diexq.>: Use FRT, FRA, FRB and FRBp repsectively on DFP quad
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instructions.
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2011-10-26 14:46:00 +00:00
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2011-10-26 Nick Clifton <nickc@redhat.com>
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PR binutils/13348
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* i386-dis.c (print_insn): Fix testing of array subscript.
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2011-10-26 12:14:17 +00:00
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2011-10-26 Joern Rennecke <joern.rennecke@embecosm.com>
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* disassemble.c (ARCH_epiphany): Move into alphasorted spot.
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2011-10-26 12:46:04 +00:00
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* epiphany-asm.c, epiphany-opc.h: Regenerate.
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bfd:
* Makefile.am (ALL_MACHINES): Add cpu-epiphany.lo .
(ALL_MACHINES_CFILES): Add cpu-epiphany.c .
(BFD32_BACKENDS): Add elf32-epiphany.lo .
(BFD32_BACKENDS_CFILES): Add elf32-epiphany.c .
* Makefile.in, bfd-in2.h, configure, libbfd.h: Regenerate.
* archures.c (bfd_arch_epiphany): Add.
(bfd_mach_epiphany16, bfd_mach_epiphany32): Define.
(bfd_epiphany_arch): Declare.
(bfd_archures_list): Add &bfd_epiphany_arch.
* config.bfd (epiphany-*-elf): New target case.
* configure.in (bfd_elf32_epiphany_vec): New target vector case.
* reloc.c (BFD_RELOC_EPIPHANY_SIMM8): New relocation.
(BFD_RELOC_EPIPHANY_SIMM24, BFD_RELOC_EPIPHANY_HIGH): Likewise.
(BFD_RELOC_EPIPHANY_LOW, BFD_RELOC_EPIPHANY_SIMM11): Likewise.
(BFD_RELOC_EPIPHANY_IMM11, BFD_RELOC_EPIPHANY_IMM8): Likewise.
* targets.c (bfd_elf32_epiphany_vec): Declare.
(_bfd_target_vector): Add bfd_elf32_epiphany_vec.
* po/SRC-POTFILES.in, po/bfd.pot: Regenerate.
* cpu-epiphany.c, elf32-epiphany.c: New files.
binutils:
* readelf.c (include "elf/epiphany.h")
(guess_is_rela, dump_relocation): Handle EM_ADAPTEVA_EPIPHANY.
(get_machine_name, is_32bit_abs_reloc, is_32bit_pcrel_reloc): Likewise.
(is_16bit_abs_reloc, is_none_reloc): Likewise.
* po/binutils.pot: Regenerate.
cpu:
* cpu/epiphany.cpu, cpu/epiphany.opc: New files.
gas:
* NEWS: Mention addition of Adapteva Epiphany support.
* config/tc-epiphany.c, config/tc-epiphany.h: New files.
* Makefile.am (TARGET_CPU_CFILES): Add config/tc-epiphany.c .
(TARGET_CPU_HFILES): Add config/tc-epiphany.h .
* Makefile.in, configure, doc/Makefile.in, po/POTFILES.in: Regenerate.
* configure.in: Also set using_cgen for epiphany.
* configure.tgt: Handle epiphany.
* doc/Makefile.am (CPU_DOCS): Add c-epiphany.texi .
* doc/all.texi: Set EPIPHANY.
* doc/as.texinfo: Add EPIPHANY-specific text.
* doc/c-epiphany.texi: New file.
* po/gas.pot: Regenerate.
gas/testsuite:
* gas/epiphany: New directory.
include:
* dis-asm.h (print_insn_epiphany): Declare.
* elf/epiphany.h: New file.
* elf/common.h (EM_ADAPTEVA_EPIPHANY): Define.
ld:
* NEWS: Mention addition of Adapteva Epiphany support.
* Makefile.am (ALL_EMULATION_SOURCES): Add eelf32epiphany.c .
(eelf32epiphany.c): New rule.
* Makefile.in: Regenerate.
* configure.tgt: Handle epiphany-*-elf.
* po/ld.pot: Regenerate.
* testsuite/ld-srec/srec.exp: xfail epiphany.
* emulparams/elf32epiphany.sh: New file.
opcodes:
* Makefile.am (HFILES): Add epiphany-desc.h and epiphany-opc.h .
(TARGET_LIBOPCODES_CFILES): Add epiphany-asm.c, epiphany-desc.c,
epiphany-dis.c, epiphany-ibld.c and epiphany-opc.c .
(CLEANFILES): Add stamp-epiphany.
(EPIPHANY_DEPS): Set. Make CGEN-generated Epiphany files depend on it.
(stamp-epiphany): New rule.
* Makefile.in, configure, po/POTFILES.in, po/opcodes.pot: Regenerate.
* configure.in: Handle bfd_epiphany_arch.
* disassemble.c (ARCH_epiphany): Define.
(disassembler): Handle bfd_arch_epiphany.
* epiphany-asm.c, epiphany-desc.c, epiphany-desc.h: New files.
* epiphany-dis.c, epiphany-ibld.c, epiphany-opc.c: Likewise.
* epiphany-opc.h: Likewise.
2011-10-25 11:18:16 +00:00
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2011-10-25 Joern Rennecke <joern.rennecke@embecosm.com>
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* Makefile.am (HFILES): Add epiphany-desc.h and epiphany-opc.h .
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(TARGET_LIBOPCODES_CFILES): Add epiphany-asm.c, epiphany-desc.c,
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epiphany-dis.c, epiphany-ibld.c and epiphany-opc.c .
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(CLEANFILES): Add stamp-epiphany.
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(EPIPHANY_DEPS): Set. Make CGEN-generated Epiphany files depend on it.
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(stamp-epiphany): New rule.
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* configure.in: Handle bfd_epiphany_arch.
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* disassemble.c (ARCH_epiphany): Define.
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(disassembler): Handle bfd_arch_epiphany.
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* epiphany-asm.c: New file.
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* epiphany-desc.c: New file.
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* epiphany-desc.h: New file.
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* epiphany-dis.c: New file.
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* epiphany-ibld.c: New file.
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* epiphany-opc.c: New file.
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* epiphany-opc.h: New file.
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* Makefile.in: Regenerate.
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* configure: Regenerate.
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* po/POTFILES.in: Regenerate.
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* po/opcodes.pot: Regenerate.
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2011-10-24 16:36:51 +00:00
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2011-10-24 Julian Brown <julian@codesourcery.com>
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* m68k-opc.c (m68k_opcodes): Fix entries for ColdFire moveml.
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2011-10-21 12:50:30 +00:00
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2011-10-21 Jan Glauber <jang@linux.vnet.ibm.com>
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* s390-opc.txt: Add CPUMF instructions.
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2011-10-18 14:41:55 +00:00
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2011-10-18 Jie Zhang <jie@codesourcery.com>
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Julian Brown <julian@codesourcery.com>
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* arm-dis.c (print_insn_arm): Explicitly specify rotation if needed.
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2011-10-10 16:12:24 +00:00
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2011-10-10 Nick Clifton <nickc@redhat.com>
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* po/es.po: Updated Spanish translation.
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* po/fi.po: Updated Finnish translation.
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gas/testsuite/
2011-09-28 Jan Beulich <jbeulich@suse.com>
* gas/ppc/476.s: Fix lswi first operand.
* gas/ppc/476.d: Adjust expected output.
* gas/ppc/a2.s: Fix lswi first operand.
* gas/ppc/a2.d: Adjust expected output.
* gas/ppc/power6.s: Fix lfdpx first operand.
* gas/ppc/power6.d: Adjust expected output.
opcodes/
2011-09-28 Jan Beulich <jbeulich@suse.com>
* ppc-opc.c (insert_nbi, insert_rbx, FRAp, FRBp, FRSp, FRTp, NBI, RAX,
RBX): New.
(insert_bo, insert_boe): Reject bcctr with bit 2 in bo unset.
(powerpc_opcodes): Use RAX for second and RBXC for third operand of
lswx. Use NBI for third operand of lswi. Use FRTp for first operand of
lfdp and lfdpx. Use FRSp for first operand of stfdp and stfdpx, and
mark them as invalid on POWER7. Use FRTp, FRAp, and FRBp repsectively
on DFP quad instructions.
2011-10-06 09:22:58 +00:00
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2011-09-28 Jan Beulich <jbeulich@suse.com>
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* ppc-opc.c (insert_nbi, insert_rbx, FRAp, FRBp, FRSp, FRTp, NBI, RAX,
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RBX): New.
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(insert_bo, insert_boe): Reject bcctr with bit 2 in bo unset.
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(powerpc_opcodes): Use RAX for second and RBXC for third operand of
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lswx. Use NBI for third operand of lswi. Use FRTp for first operand of
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lfdp and lfdpx. Use FRSp for first operand of stfdp and stfdpx, and
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mark them as invalid on POWER7. Use FRTp, FRAp, and FRBp repsectively
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on DFP quad instructions.
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2011-09-27 04:30:32 +00:00
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2011-09-27 David S. Miller <davem@davemloft.net>
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* sparc-opc.c (sparc_opcodes): Fix random instruction to write
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to a float instead of an integer register.
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2011-09-26 09:19:24 +00:00
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2011-09-26 David S. Miller <davem@davemloft.net>
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* sparc-opc.c (sparc_opcodes): Add integer multiply-add
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instructions.
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Annotate sparc objects with cpu hardware capabilities used.
bfd/
* elfxx-sparc.c (_bfd_sparc_elf_merge_private_bfd_data): New.
* elfxx-sparc.h: Declare it.
* elf32-sparc.c (elf32_sparc_merge_private_bfd_data): Call it.
* elf64-sparc.c (elf64_sparc_merge_private_bfd_data): Likewise.
binutils/
* readelf.c (display_sparc_hwcaps): New.
(display_sparc_gnu_attribute): New.
(process_sparc_specific): New.
(process_arch_specific): When EM_SPARC, EM_SPARC32PLUS,
or EM_SPARCV9 invoke process_sparc_specific.
gas/
* config/tc-sparc.c (hwcap_seen): New bitmask, defined when
not TE_SOLARIS.
(sparc_ip): When not TE_SOLARIS, accumulate hwcap bits from
sparc_opcode->flags of instruction into hwcap_seen.
(sparc_md_end): Create Tag_GNU_Sparc_HWCAPS attribute if
hwcap_seen is non-zero and not TE_SOLARIS.
gas/testsuite/
* gas/sparc/hpcvis3.s: Update for fixed fchksum16 mnemonic.
* gas/sparc/hpcvis3.d: Likewise.
include/elf/
* sparc.h (Tag_GNU_Sparc_HWCAPS): New object attribute.
(ELF_SPARC_HWCAP_*): New HWCAPS bitmask values.
include/opcode/
* sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int.
(F_MUL32, F_DIV32, F_FSMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits.
opcodes/
* sparc-opc.c (sparc_opcodes): Annotate table with HWCAP flag
bits. Fix "fchksm16" mnemonic.
2011-09-21 20:49:16 +00:00
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2011-09-21 David S. Miller <davem@davemloft.net>
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* sparc-opc.c (sparc_opcodes): Annotate table with HWCAP flag
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bits. Fix "fchksm16" mnemonic.
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opcodes/
The changes below bring 'mov' and 'ticc' instructions into line
with the V8 SPARC Architecture Manual.
* sparc-opc.c (sparc_opcodes): Add entry for 'ticc imm + regrs1'.
* sparc-opc.c (sparc_opcodes): Add alias entries for
'mov regrs2,%asrX'; 'mov regrs2,%y'; 'mov regrs2,%prs';
'mov regrs2,%wim' and 'mov regrs2,%tbr'.
* sparc-opc.c (sparc_opcodes): Move/Change entries for
'mov imm,%asrX'; 'mov imm,%y'; 'mov imm,%prs'; 'mov imm,%wim'
and 'mov imm,%tbr'.
* sparc-opc.c (sparc_opcodes): Add wr alias entries to match above
mov aliases.
gas/testsuite/
* gas/sparc/ticc-imm-reg.[sd]: New test.
* gas/sparc/v8-movwr-imm.[sd]: New test.
* gas/sparc/sparc.exp: Run new tests.
2011-09-08 19:01:11 +00:00
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2011-09-08 Mark Fortescue <mark@mtfhpc.demon.co.uk>
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The changes below bring 'mov' and 'ticc' instructions into line
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with the V8 SPARC Architecture Manual.
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* sparc-opc.c (sparc_opcodes): Add entry for 'ticc imm + regrs1'.
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* sparc-opc.c (sparc_opcodes): Add alias entries for
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'mov regrs2,%asrX'; 'mov regrs2,%y'; 'mov regrs2,%prs';
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'mov regrs2,%wim' and 'mov regrs2,%tbr'.
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* sparc-opc.c (sparc_opcodes): Move/Change entries for
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'mov imm,%asrX'; 'mov imm,%y'; 'mov imm,%prs'; 'mov imm,%wim'
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and 'mov imm,%tbr'.
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* sparc-opc.c (sparc_opcodes): Add wr alias entries to match above
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mov aliases.
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2011-09-08 19:03:17 +00:00
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* sparc-opc.c (sparc_opcodes): Add entry for 'save simm13,regrs1,regrd'
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This has been reported as being accepted by the Sun assmebler.
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2011-09-08 16:40:47 +00:00
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2011-09-08 David S. Miller <davem@davemloft.net>
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* sparc-opc.c (pdistn): Destination is integer not float register.
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2011-09-07 20:56:09 +00:00
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2011-09-07 Andreas Schwab <schwab@linux-m68k.org>
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2011-09-10 08:13:45 +00:00
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PR gas/13145
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2011-09-07 20:56:09 +00:00
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* m68k-opc.c: Use "y" in moveml pattern for mcfisa_a.
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2011-08-26 15:15:52 +00:00
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2011-08-26 Nick Clifton <nickc@redhat.com>
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* po/es.po: Updated Spanish translation.
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2011-08-22 15:25:07 +00:00
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2011-08-22 Nick Clifton <nickc@redhat.com>
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* Makefile.am (CPUDIR): Redfine to point to top level cpu
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directory.
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(stamp-frv): Use CPUDIR.
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(stamp-iq2000): Likewise.
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(stamp-lm32): Likewise.
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(stamp-m32c): Likewise.
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(stamp-mt): Likewise.
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(stamp-xc16x): Likewise.
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* Makefile.in: Regenerate.
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gas/
* config/tc-mips.c (mips_set_options): Add ase_mcu.
(mips_opts): Initialise ase_mcu to -1.
(ISA_SUPPORTS_MCU_ASE): New macro.
(MIPS_CPU_ASE_MCU): Likewise.
(is_opcode_valid): Handle MCU.
(macro_build, macro): Likewise.
(validate_mips_insn, validate_micromips_insn): Likewise.
(mips_ip): Likewise.
(options): Add OPTION_MCU and OPTION_NO_MCU.
(md_longopts): Add mmcu and mno-mcu.
(md_parse_option): Handle OPTION_MCU and OPTION_NO_MCU.
(mips_after_parse_args): Handle MCU.
(s_mipsset): Likewise.
(md_show_usage): Handle MCU options.
* doc/as.texinfo: Document -mmcu and -mno-mcu options.
* doc/c-mips.texi: Likewise, and document ".set mcu" and
".set nomcu" directives.
gas/testsuite/
* gas/mips/micromips@mcu.d: New test.
* gas/mips/mcu.d: Likewise.
* gas/mips/mcu.s: New test source.
* gas/mips/mips.exp: Run the new tests.
include/opcode/
* mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros.
(OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine.
(INSN_ASE_MASK): Add the MCU bit.
(INSN_MCU): New macro.
(M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values.
(MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros.
opcodes/
* mips-dis.c (mips_arch_choices): Enable MCU for "mips32r2"
and "mips64r2".
(print_insn_args, print_insn_micromips): Handle MCU.
* micromips-opc.c (MC): New macro.
(micromips_opcodes): Add "aclr", "aset" and "iret".
* mips-opc.c (MC): New macro.
(mips_builtin_opcodes): Add "aclr", "aset" and "iret".
2011-08-09 15:20:03 +00:00
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2011-08-09 Chao-ying Fu <fu@mips.com>
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Maciej W. Rozycki <macro@codesourcery.com>
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* mips-dis.c (mips_arch_choices): Enable MCU for "mips32r2"
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and "mips64r2".
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(print_insn_args, print_insn_micromips): Handle MCU.
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* micromips-opc.c (MC): New macro.
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(micromips_opcodes): Add "aclr", "aset" and "iret".
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* mips-opc.c (MC): New macro.
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(mips_builtin_opcodes): Add "aclr", "aset" and "iret".
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include/opcode/
* mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros.
(INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise.
(INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise.
(INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise.
(INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise.
(INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise.
(INSN2_READ_GPR_MMN): Likewise.
(INSN2_READ_FPR_D): Change the bit used.
(INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise.
(INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise.
(INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise.
(INSN2_COND_BRANCH): Likewise.
(INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros.
(INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise.
(INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise.
(INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise.
(INSN2_MOD_GPR_MN): Likewise.
gas/
* config/tc-mips.c (gpr_mod_mask): Remove INSN2_MOD_GPR_MB,
INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG,
INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MM,
INSN2_MOD_GPR_MN, INSN2_MOD_GPR_MP and INSN2_MOD_GPR_MQ opcode
register use checks.
(gpr_read_mask): Add INSN2_READ_GPR_MC, INSN2_READ_GPR_ME
INSN2_READ_GPR_MG, INSN2_READ_GPR_MJ, INSN2_READ_GPR_MMN,
INSN2_READ_GPR_MP and INSN2_READ_GPR_MQ opcode register use
checks.
(gpr_write_mask): Replace INSN2_WRITE_GPR_S opcode register
use flag with INSN_WRITE_GPR_S. Add INSN2_WRITE_GPR_MB,
INSN2_WRITE_GPR_MHI, INSN2_WRITE_GPR_MJ and INSN2_WRITE_GPR_MP
opcode register use checks.
(can_swap_branch_p): Enable microMIPS branch swapping.
(append_insn): Likewise.
gas/testsuite/
* gas/mips/micromips.d: Update according to changes to enable
microMIPS branch swapping.
* gas/mips/micromips-trap.d: Likewise.
* gas/mips/micromips@jal-svr4pic.d: Likewise.
* gas/mips/micromips@loc-swap.d: Likewise.
* gas/mips/micromips@loc-swap-dis.d: Likewise.
opcodes/
* micromips-opc.c (MOD_mb, MOD_mc, MOD_md): Remove macros.
(MOD_me, MOD_mf, MOD_mg, MOD_mhi, MOD_mj, MOD_ml): Likewise.
(MOD_mm, MOD_mn, MOD_mp, MOD_mq, MOD_sp): Likewise.
(WR_mb, RD_mc, RD_md, WR_md, RD_me, RD_mf, WR_mf): New macros.
(RD_mg, WR_mhi, RD_mj, WR_mj, RD_ml, RD_mmn): Likewise.
(RD_mp, WR_mp, RD_mq, RD_sp, WR_sp): Likewise.
(WR_s): Update macro.
(micromips_opcodes): Update register use flags of: "addiu",
"addiupc", "addiur1sp", "addiur2", "addius5", "addiusp", "addu",
"and", "andi", "beq", "beqz", "bne", "bnez", "di", "ei", "j",
"jalr", "jalrs", "jr", "jraddiusp", "jrc", "lbu", "lhu", "li",
"lui", "lw", "lwm", "mfhi", "mflo", "move", "movep", "not",
"nor", "or", "ori", "sb", "sh", "sll", "srl", "subu", "sw",
"swm" and "xor" instructions.
2011-08-09 14:25:29 +00:00
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2011-08-09 Maciej W. Rozycki <macro@codesourcery.com>
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* micromips-opc.c (MOD_mb, MOD_mc, MOD_md): Remove macros.
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(MOD_me, MOD_mf, MOD_mg, MOD_mhi, MOD_mj, MOD_ml): Likewise.
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(MOD_mm, MOD_mn, MOD_mp, MOD_mq, MOD_sp): Likewise.
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(WR_mb, RD_mc, RD_md, WR_md, RD_me, RD_mf, WR_mf): New macros.
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(RD_mg, WR_mhi, RD_mj, WR_mj, RD_ml, RD_mmn): Likewise.
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(RD_mp, WR_mp, RD_mq, RD_sp, WR_sp): Likewise.
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(WR_s): Update macro.
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(micromips_opcodes): Update register use flags of: "addiu",
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"addiupc", "addiur1sp", "addiur2", "addius5", "addiusp", "addu",
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"and", "andi", "beq", "beqz", "bne", "bnez", "di", "ei", "j",
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"jalr", "jalrs", "jr", "jraddiusp", "jrc", "lbu", "lhu", "li",
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"lui", "lw", "lwm", "mfhi", "mflo", "move", "movep", "not",
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"nor", "or", "ori", "sb", "sh", "sll", "srl", "subu", "sw",
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"swm" and "xor" instructions.
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2011-08-05 16:52:50 +00:00
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2011-08-05 David S. Miller <davem@davemloft.net>
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* sparc-dis.c (v9a_ast_reg_names): Add "cps".
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(X_RS3): New macro.
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(print_insn_sparc): Handle '4', '5', and '(' format codes.
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Accept %asr numbers below 28.
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* sparc-opc.c (sparc_opcodes): Add entries for HPC and VIS3
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instructions.
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2011-08-02 19:58:06 +00:00
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2011-08-02 Quentin Neill <quentin.neill@amd.com>
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* i386-dis.c (xop_table): Remove spurious bextr insn.
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2011-08-01 23:04:23 +00:00
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2011-08-01 H.J. Lu <hongjiu.lu@intel.com>
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PR ld/13048
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* i386-dis.c (print_insn): Optimize info->mach check.
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2011-08-01 19:25:48 +00:00
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2011-08-01 H.J. Lu <hongjiu.lu@intel.com>
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PR gas/13046
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* i386-opc.tbl: Add Disp32S to 64bit call.
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* i386-tbl.h: Regenerated.
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bfd/
2011-02-25 Chao-ying Fu <fu@mips.com>
Ilie Garbacea <ilie@mips.com>
Maciej W. Rozycki <macro@codesourcery.com>
Joseph Myers <joseph@codesourcery.com>
Catherine Moore <clm@codesourcery.com>
Richard Sandiford <rdsandiford@googlemail.com>
* archures.c (bfd_mach_mips_micromips): New macro.
* cpu-mips.c (I_micromips): New enum value.
(arch_info_struct): Add bfd_mach_mips_micromips.
* elfxx-mips.h (_bfd_mips_elf_is_target_special_symbol): New
prototype.
(_bfd_mips_elf_relax_section): Likewise.
(_bfd_mips16_elf_reloc_unshuffle): Rename to...
(_bfd_mips_elf_reloc_unshuffle): ... this. Handle microMIPS
ASE.
(_bfd_mips16_elf_reloc_shuffle): Rename to...
(_bfd_mips_elf_reloc_shuffle): ... this. Handle microMIPS ASE.
(gprel16_reloc_p): Handle microMIPS ASE.
(literal_reloc_p): New function.
* elf32-mips.c (elf_micromips_howto_table_rel): New variable.
(_bfd_mips_elf32_gprel16_reloc): Handle microMIPS ASE.
(mips16_gprel_reloc): Update for _bfd_mips_elf_reloc_unshuffle
and _bfd_mips_elf_reloc_shuffle changes.
(mips_elf_gprel32_reloc): Update comment.
(micromips_reloc_map): New variable.
(bfd_elf32_bfd_reloc_type_lookup): Handle microMIPS ASE.
(mips_elf32_rtype_to_howto): Likewise.
(mips_info_to_howto_rel): Likewise.
(bfd_elf32_bfd_is_target_special_symbol): Define.
(bfd_elf32_bfd_relax_section): Likewise.
* elf64-mips.c (micromips_elf64_howto_table_rel): New variable.
(micromips_elf64_howto_table_rela): Likewise.
(mips16_gprel_reloc): Update for _bfd_mips_elf_reloc_unshuffle
and _bfd_mips_elf_reloc_shuffle changes.
(micromips_reloc_map): Likewise.
(bfd_elf64_bfd_reloc_type_lookup): Handle microMIPS ASE.
(bfd_elf64_bfd_reloc_name_lookup): Likewise.
(mips_elf64_rtype_to_howto): Likewise.
(bfd_elf64_bfd_is_target_special_symbol): Define.
* elfn32-mips.c (elf_micromips_howto_table_rel): New variable.
(elf_micromips_howto_table_rela): Likewise.
(mips16_gprel_reloc): Update for _bfd_mips_elf_reloc_unshuffle
and _bfd_mips_elf_reloc_shuffle changes.
(micromips_reloc_map): Likewise.
(bfd_elf32_bfd_reloc_type_lookup): Handle microMIPS ASE.
(bfd_elf32_bfd_reloc_name_lookup): Likewise.
(mips_elf_n32_rtype_to_howto): Likewise.
(bfd_elf32_bfd_is_target_special_symbol): Define.
* elfxx-mips.c (LA25_LUI_MICROMIPS_1): New macro.
(LA25_LUI_MICROMIPS_2): Likewise.
(LA25_J_MICROMIPS_1, LA25_J_MICROMIPS_2): Likewise.
(LA25_ADDIU_MICROMIPS_1, LA25_ADDIU_MICROMIPS_2): Likewise.
(TLS_RELOC_P): Handle microMIPS ASE.
(mips_elf_create_stub_symbol): Adjust value of stub symbol if
target is a microMIPS function.
(micromips_reloc_p): New function.
(micromips_reloc_shuffle_p): Likewise.
(got16_reloc_p, call16_reloc_p): Handle microMIPS ASE.
(got_disp_reloc_p, got_page_reloc_p): New functions.
(got_ofst_reloc_p): Likewise.
(got_hi16_reloc_p, got_lo16_reloc_p): Likewise.
(call_hi16_reloc_p, call_lo16_reloc_p): Likewise.
(hi16_reloc_p, lo16_reloc_p, jal_reloc_p): Handle microMIPS ASE.
(micromips_branch_reloc_p): New function.
(tls_gd_reloc_p, tls_ldm_reloc_p): Likewise.
(tls_gottprel_reloc_p): Likewise.
(_bfd_mips16_elf_reloc_unshuffle): Rename to...
(_bfd_mips_elf_reloc_unshuffle): ... this. Handle microMIPS
ASE.
(_bfd_mips16_elf_reloc_shuffle): Rename to...
(_bfd_mips_elf_reloc_shuffle): ... this. Handle microMIPS ASE.
(_bfd_mips_elf_lo16_reloc): Handle microMIPS ASE.
(mips_tls_got_index, mips_elf_got_page): Likewise.
(mips_elf_create_local_got_entry): Likewise.
(mips_elf_relocation_needs_la25_stub): Likewise.
(mips_elf_calculate_relocation): Likewise.
(mips_elf_perform_relocation): Likewise.
(_bfd_mips_elf_symbol_processing): Likewise.
(_bfd_mips_elf_add_symbol_hook): Likewise.
(_bfd_mips_elf_link_output_symbol_hook): Likewise.
(mips_elf_add_lo16_rel_addend): Likewise.
(_bfd_mips_elf_check_relocs): Likewise.
(mips_elf_adjust_addend): Likewise.
(_bfd_mips_elf_relocate_section): Likewise.
(mips_elf_create_la25_stub): Likewise.
(_bfd_mips_vxworks_finish_dynamic_symbol): Likewise.
(_bfd_mips_elf_gc_sweep_hook): Likewise.
(_bfd_mips_elf_is_target_special_symbol): New function.
(mips_elf_relax_delete_bytes): Likewise.
(opcode_descriptor): New structure.
(RA): New macro.
(OP32_SREG, OP32_TREG, OP16_VALID_REG): Likewise.
(b_insns_32, bc_insn_32, bz_insn_32, bzal_insn_32): New variables.
(beq_insn_32): Likewise.
(b_insn_16, bz_insn_16): New variables.
(BZC32_REG_FIELD): New macro.
(bz_rs_insns_32, bz_rt_insns_32): New variables.
(bzc_insns_32, bz_insns_16):Likewise.
(BZ16_REG, BZ16_REG_FIELD): New macros.
(jal_insn_32_bd16, jal_insn_32_bd32): New variables.
(jal_x_insn_32_bd32): Likewise.
(j_insn_32, jalr_insn_32): Likewise.
(ds_insns_32_bd16, ds_insns_32_bd32): Likewise.
(jalr_insn_16_bd16, jalr_insn_16_bd32, jr_insn_16): Likewise.
(JR16_REG): New macro.
(ds_insns_16_bd16): New variable.
(lui_insn): Likewise.
(addiu_insn, addiupc_insn): Likewise.
(ADDIUPC_REG_FIELD): New macro.
(MOVE32_RD, MOVE32_RS): Likewise.
(MOVE16_RD_FIELD, MOVE16_RS_FIELD): Likewise.
(move_insns_32, move_insns_16): New variables.
(nop_insn_32, nop_insn_16): Likewise.
(MATCH): New macro.
(find_match): New function.
(check_br16_dslot, check_br32_dslot): Likewise.
(check_br16, check_br32): Likewise.
(IS_BITSIZE): New macro.
(check_4byte_branch): New function.
(_bfd_mips_elf_relax_section): Likewise.
(_bfd_mips_elf_merge_private_bfd_data): Disallow linking MIPS16
and microMIPS modules together.
(_bfd_mips_elf_print_private_bfd_data): Handle microMIPS ASE.
* reloc.c (BFD_RELOC_MICROMIPS_7_PCREL_S1): New relocation.
(BFD_RELOC_MICROMIPS_10_PCREL_S1): Likewise.
(BFD_RELOC_MICROMIPS_16_PCREL_S1): Likewise.
(BFD_RELOC_MICROMIPS_GPREL16): Likewise.
(BFD_RELOC_MICROMIPS_JMP, BFD_RELOC_MICROMIPS_HI16): Likewise.
(BFD_RELOC_MICROMIPS_HI16_S): Likewise.
(BFD_RELOC_MICROMIPS_LO16): Likewise.
(BFD_RELOC_MICROMIPS_LITERAL): Likewise.
(BFD_RELOC_MICROMIPS_GOT16): Likewise.
(BFD_RELOC_MICROMIPS_CALL16): Likewise.
(BFD_RELOC_MICROMIPS_GOT_HI16): Likewise.
(BFD_RELOC_MICROMIPS_GOT_LO16): Likewise.
(BFD_RELOC_MICROMIPS_CALL_HI16): Likewise.
(BFD_RELOC_MICROMIPS_CALL_LO16): Likewise.
(BFD_RELOC_MICROMIPS_SUB): Likewise.
(BFD_RELOC_MICROMIPS_GOT_PAGE): Likewise.
(BFD_RELOC_MICROMIPS_GOT_OFST): Likewise.
(BFD_RELOC_MICROMIPS_GOT_DISP): Likewise.
(BFD_RELOC_MICROMIPS_HIGHEST): Likewise.
(BFD_RELOC_MICROMIPS_HIGHER): Likewise.
(BFD_RELOC_MICROMIPS_SCN_DISP): Likewise.
(BFD_RELOC_MICROMIPS_JALR): Likewise.
(BFD_RELOC_MICROMIPS_TLS_GD): Likewise.
(BFD_RELOC_MICROMIPS_TLS_LDM): Likewise.
(BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16): Likewise.
(BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16): Likewise.
(BFD_RELOC_MICROMIPS_TLS_GOTTPREL): Likewise.
(BFD_RELOC_MICROMIPS_TLS_TPREL_HI16): Likewise.
(BFD_RELOC_MICROMIPS_TLS_TPREL_LO16): Likewise.
* bfd-in2.h: Regenerate.
* libbfd.h: Regenerate.
binutils/
2011-02-25 Chao-ying Fu <fu@mips.com>
Maciej W. Rozycki <macro@codesourcery.com>
* readelf.c (get_machine_flags): Handle microMIPS ASE.
(get_mips_symbol_other): Likewise.
gas/
2011-02-25 Maciej W. Rozycki <macro@codesourcery.com>
Chao-ying Fu <fu@mips.com>
Richard Sandiford <rdsandiford@googlemail.com>
* config/tc-mips.h (mips_segment_info): Add one bit for
microMIPS.
(TC_LABEL_IS_LOCAL): New macro.
(mips_label_is_local): New prototype.
* config/tc-mips.c (S0, S7): New macros.
(emit_branch_likely_macro): New variable.
(mips_set_options): Add micromips.
(mips_opts): Initialise micromips to -1.
(file_ase_micromips): New variable.
(CPU_HAS_MICROMIPS): New macro.
(hilo_interlocks): Set for microMIPS too.
(gpr_interlocks): Likewise.
(cop_interlocks): Likewise.
(cop_mem_interlocks): Likewise.
(HAVE_CODE_COMPRESSION): New macro.
(micromips_op_hash): New variable.
(micromips_nop16_insn, micromips_nop32_insn): New variables.
(NOP_INSN): Handle microMIPS ASE.
(mips32_to_micromips_reg_b_map): New macro.
(mips32_to_micromips_reg_c_map): Likewise.
(mips32_to_micromips_reg_d_map): Likewise.
(mips32_to_micromips_reg_e_map): Likewise.
(mips32_to_micromips_reg_f_map): Likewise.
(mips32_to_micromips_reg_g_map): Likewise.
(mips32_to_micromips_reg_l_map): Likewise.
(mips32_to_micromips_reg_n_map): Likewise.
(mips32_to_micromips_reg_h_map): New variable.
(mips32_to_micromips_reg_m_map): Likewise.
(mips32_to_micromips_reg_q_map): Likewise.
(micromips_to_32_reg_h_map): New variable.
(micromips_to_32_reg_i_map): Likewise.
(micromips_to_32_reg_m_map): Likewise.
(micromips_to_32_reg_q_map): Likewise.
(micromips_to_32_reg_b_map): New macro.
(micromips_to_32_reg_c_map): Likewise.
(micromips_to_32_reg_d_map): Likewise.
(micromips_to_32_reg_e_map): Likewise.
(micromips_to_32_reg_f_map): Likewise.
(micromips_to_32_reg_g_map): Likewise.
(micromips_to_32_reg_l_map): Likewise.
(micromips_to_32_reg_n_map): Likewise.
(micromips_imm_b_map, micromips_imm_c_map): New macros.
(RELAX_DELAY_SLOT_16BIT): New macro.
(RELAX_DELAY_SLOT_SIZE_FIRST): Likewise.
(RELAX_DELAY_SLOT_SIZE_SECOND): Likewise.
(RELAX_MICROMIPS_ENCODE, RELAX_MICROMIPS_P): New macros.
(RELAX_MICROMIPS_TYPE, RELAX_MICROMIPS_AT): Likewise.
(RELAX_MICROMIPS_U16BIT, RELAX_MICROMIPS_UNCOND): Likewise.
(RELAX_MICROMIPS_COMPACT, RELAX_MICROMIPS_LINK): Likewise.
(RELAX_MICROMIPS_RELAX32, RELAX_MICROMIPS_TOOFAR16): Likewise.
(RELAX_MICROMIPS_MARK_TOOFAR16): Likewise.
(RELAX_MICROMIPS_CLEAR_TOOFAR16): Likewise.
(RELAX_MICROMIPS_TOOFAR32): Likewise.
(RELAX_MICROMIPS_MARK_TOOFAR32): Likewise.
(RELAX_MICROMIPS_CLEAR_TOOFAR32): Likewise.
(INSERT_OPERAND, EXTRACT_OPERAND): Handle microMIPS ASE.
(mips_macro_warning): Add delay_slot_16bit_p, delay_slot_32bit_p,
fsize and insns.
(mips_mark_labels): New function.
(mips16_small, mips16_ext): Remove variables, replacing with...
(forced_insn_size): ... this.
(append_insn, mips16_ip): Update accordingly.
(micromips_insn_length): New function.
(insn_length): Return the length of microMIPS instructions.
(mips_record_mips16_mode): Rename to...
(mips_record_compressed_mode): ... this. Handle microMIPS ASE.
(install_insn): Handle microMIPS ASE.
(reglist_lookup): New function.
(is_size_valid, is_delay_slot_valid): Likewise.
(md_begin): Handle microMIPS ASE.
(md_assemble): Likewise. Update for append_insn interface change.
(micromips_reloc_p): New function.
(got16_reloc_p): Handle microMIPS ASE.
(hi16_reloc_p): Likewise.
(lo16_reloc_p): Likewise.
(jmp_reloc_p): New function.
(jalr_reloc_p): Likewise.
(matching_lo_reloc): Handle microMIPS ASE.
(insn_uses_reg, reg_needs_delay): Likewise.
(mips_move_labels): Likewise.
(mips16_mark_labels): Rename to...
(mips_compressed_mark_labels): ... this. Handle microMIPS ASE.
(gpr_mod_mask): New function.
(gpr_read_mask, gpr_write_mask): Handle microMIPS ASE.
(fpr_read_mask, fpr_write_mask): Likewise.
(insns_between, nops_for_vr4130, nops_for_insn): Likewise.
(fix_loongson2f_nop, fix_loongson2f_jump): Likewise.
(MICROMIPS_LABEL_CHAR): New macro.
(micromips_target_label, micromips_target_name): New variables.
(micromips_label_name, micromips_label_expr): New functions.
(micromips_label_inc, micromips_add_label): Likewise.
(mips_label_is_local): Likewise.
(micromips_map_reloc): Likewise.
(can_swap_branch_p): Handle microMIPS ASE.
(append_insn): Add expansionp argument. Handle microMIPS ASE.
(start_noreorder, end_noreorder): Handle microMIPS ASE.
(macro_start, macro_warning, macro_end): Likewise.
(brk_fmt, cop12_fmt, jalr_fmt, lui_fmt): New variables.
(mem12_fmt, mfhl_fmt, shft_fmt, trap_fmt): Likewise.
(BRK_FMT, COP12_FMT, JALR_FMT, LUI_FMT): New macros.
(MEM12_FMT, MFHL_FMT, SHFT_FMT, TRAP_FMT): Likewise.
(macro_build): Handle microMIPS ASE. Update for append_insn
interface change.
(mips16_macro_build): Update for append_insn interface change.
(macro_build_jalr): Handle microMIPS ASE.
(macro_build_lui): Likewise. Simplify.
(load_register): Handle microMIPS ASE.
(load_address): Likewise.
(move_register): Likewise.
(macro_build_branch_likely): New function.
(macro_build_branch_ccl): Likewise.
(macro_build_branch_rs): Likewise.
(macro_build_branch_rsrt): Likewise.
(macro): Handle microMIPS ASE.
(validate_micromips_insn): New function.
(expr_const_in_range): Likewise.
(mips_ip): Handle microMIPS ASE.
(options): Add OPTION_MICROMIPS and OPTION_NO_MICROMIPS.
(md_longopts): Add mmicromips and mno-micromips.
(md_parse_option): Handle OPTION_MICROMIPS and
OPTION_NO_MICROMIPS.
(mips_after_parse_args): Handle microMIPS ASE.
(md_pcrel_from): Handle microMIPS relocations.
(mips_force_relocation): Likewise.
(md_apply_fix): Likewise.
(mips_align): Handle microMIPS ASE.
(s_mipsset): Likewise.
(s_cpload, s_cpsetup, s_cpreturn): Use relocation wrappers.
(s_dtprel_internal): Likewise.
(s_gpword, s_gpdword): Likewise.
(s_insn): Handle microMIPS ASE.
(s_mips_stab): Likewise.
(relaxed_micromips_32bit_branch_length): New function.
(relaxed_micromips_16bit_branch_length): New function.
(md_estimate_size_before_relax): Handle microMIPS ASE.
(mips_fix_adjustable): Likewise.
(tc_gen_reloc): Handle microMIPS relocations.
(mips_relax_frag): Handle microMIPS ASE.
(md_convert_frag): Likewise.
(mips_frob_file_after_relocs): Likewise.
(mips_elf_final_processing): Likewise.
(mips_nop_opcode): Likewise.
(mips_handle_align): Likewise.
(md_show_usage): Handle microMIPS options.
* symbols.c (TC_LABEL_IS_LOCAL): New macro.
(S_IS_LOCAL): Add a TC_LABEL_IS_LOCAL check.
* doc/as.texinfo (Target MIPS options): Add -mmicromips and
-mno-micromips.
(-mmicromips, -mno-micromips): New options.
* doc/c-mips.texi (-mmicromips, -mno-micromips): New options.
(MIPS ISA): Document .set micromips and .set nomicromips.
(MIPS insn): Update for microMIPS support.
gas/testsuite/
2011-02-25 Maciej W. Rozycki <macro@codesourcery.com>
Chao-ying Fu <fu@mips.com>
Richard Sandiford <rdsandiford@googlemail.com>
* gas/mips/micromips.d: New test.
* gas/mips/micromips-branch-delay.d: Likewise.
* gas/mips/micromips-branch-relax.d: Likewise.
* gas/mips/micromips-branch-relax-pic.d: Likewise.
* gas/mips/micromips-size-1.d: Likewise.
* gas/mips/micromips-trap.d: Likewise.
* gas/mips/micromips.l: New stderr output.
* gas/mips/micromips-branch-delay.l: Likewise.
* gas/mips/micromips-branch-relax.l: Likewise.
* gas/mips/micromips-branch-relax-pic.l: Likewise.
* gas/mips/micromips-size-0.l: New list test.
* gas/mips/micromips-size-1.l: New stderr output.
* gas/mips/micromips.s: New test source.
* gas/mips/micromips-branch-delay.s: Likewise.
* gas/mips/micromips-branch-relax.s: Likewise.
* gas/mips/micromips-size-0.s: Likewise.
* gas/mips/micromips-size-1.s: Likewise.
* gas/mips/mips.exp: Run the new tests.
* gas/mips/dli.s: Use .p2align.
* gas/mips/elf_ase_micromips.d: New test.
* gas/mips/elf_ase_micromips-2.d: Likewise.
* gas/mips/micromips@abs.d: Likewise.
* gas/mips/micromips@add.d: Likewise.
* gas/mips/micromips@alnv_ps-swap.d: Likewise.
* gas/mips/micromips@and.d: Likewise.
* gas/mips/micromips@beq.d: Likewise.
* gas/mips/micromips@bge.d: Likewise.
* gas/mips/micromips@bgeu.d: Likewise.
* gas/mips/micromips@blt.d: Likewise.
* gas/mips/micromips@bltu.d: Likewise.
* gas/mips/micromips@branch-likely.d: Likewise.
* gas/mips/micromips@branch-misc-1.d: Likewise.
* gas/mips/micromips@branch-misc-2-64.d: Likewise.
* gas/mips/micromips@branch-misc-2.d: Likewise.
* gas/mips/micromips@branch-misc-2pic-64.d: Likewise.
* gas/mips/micromips@branch-misc-2pic.d: Likewise.
* gas/mips/micromips@branch-misc-4-64.d: Likewise.
* gas/mips/micromips@branch-misc-4.d: Likewise.
* gas/mips/micromips@branch-self.d: Likewise.
* gas/mips/micromips@cache.d: Likewise.
* gas/mips/micromips@daddi.d: Likewise.
* gas/mips/micromips@dli.d: Likewise.
* gas/mips/micromips@elf-jal.d: Likewise.
* gas/mips/micromips@elf-rel2.d: Likewise.
* gas/mips/micromips@elfel-rel2.d: Likewise.
* gas/mips/micromips@elf-rel4.d: Likewise.
* gas/mips/micromips@jal-svr4pic.d: Likewise.
* gas/mips/micromips@jal-svr4pic-noreorder.d: Likewise.
* gas/mips/micromips@lb-svr4pic-ilocks.d: Likewise.
* gas/mips/micromips@li.d: Likewise.
* gas/mips/micromips@loc-swap-dis.d: Likewise.
* gas/mips/micromips@loc-swap.d: Likewise.
* gas/mips/micromips@mips1-fp.d: Likewise.
* gas/mips/micromips@mips32-cp2.d: Likewise.
* gas/mips/micromips@mips32-imm.d: Likewise.
* gas/mips/micromips@mips32-sf32.d: Likewise.
* gas/mips/micromips@mips32.d: Likewise.
* gas/mips/micromips@mips32r2-cp2.d: Likewise.
* gas/mips/micromips@mips32r2-fp32.d: Likewise.
* gas/mips/micromips@mips32r2-sync.d: Likewise.
* gas/mips/micromips@mips32r2.d: Likewise.
* gas/mips/micromips@mips4-branch-likely.d: Likewise.
* gas/mips/micromips@mips4-fp.d: Likewise.
* gas/mips/micromips@mips4.d: Likewise.
* gas/mips/micromips@mips5.d: Likewise.
* gas/mips/micromips@mips64-cp2.d: Likewise.
* gas/mips/micromips@mips64.d: Likewise.
* gas/mips/micromips@mips64r2.d: Likewise.
* gas/mips/micromips@pref.d: Likewise.
* gas/mips/micromips@relax-at.d: Likewise.
* gas/mips/micromips@relax.d: Likewise.
* gas/mips/micromips@rol-hw.d: Likewise.
* gas/mips/micromips@uld2-eb.d: Likewise.
* gas/mips/micromips@uld2-el.d: Likewise.
* gas/mips/micromips@ulh2-eb.d: Likewise.
* gas/mips/micromips@ulh2-el.d: Likewise.
* gas/mips/micromips@ulw2-eb-ilocks.d: Likewise.
* gas/mips/micromips@ulw2-el-ilocks.d: Likewise.
* gas/mips/cache.d: Likewise.
* gas/mips/daddi.d: Likewise.
* gas/mips/mips32-imm.d: Likewise.
* gas/mips/pref.d: Likewise.
* gas/mips/elf-rel27.d: Handle microMIPS ASE.
* gas/mips/l_d.d: Likewise.
* gas/mips/l_d-n32.d: Likewise.
* gas/mips/l_d-n64.d: Likewise.
* gas/mips/ld.d: Likewise.
* gas/mips/ld-n32.d: Likewise.
* gas/mips/ld-n64.d: Likewise.
* gas/mips/s_d.d: Likewise.
* gas/mips/s_d-n32.d: Likewise.
* gas/mips/s_d-n64.d: Likewise.
* gas/mips/sd.d: Likewise.
* gas/mips/sd-n32.d: Likewise.
* gas/mips/sd-n64.d: Likewise.
* gas/mips/mips32.d: Update immediates.
* gas/mips/micromips@mips32-cp2.s: New test source.
* gas/mips/micromips@mips32-imm.s: Likewise.
* gas/mips/micromips@mips32r2-cp2.s: Likewise.
* gas/mips/micromips@mips64-cp2.s: Likewise.
* gas/mips/cache.s: Likewise.
* gas/mips/daddi.s: Likewise.
* gas/mips/mips32-imm.s: Likewise.
* gas/mips/elf-rel4.s: Handle microMIPS ASE.
* gas/mips/lb-pic.s: Likewise.
* gas/mips/ld.s: Likewise.
* gas/mips/mips32.s: Likewise.
* gas/mips/mips.exp: Add the micromips arch. Exclude mips16e
from micromips. Run mips32-imm.
* gas/mips/jal-mask-11.d: New test.
* gas/mips/jal-mask-12.d: Likewise.
* gas/mips/micromips@jal-mask-11.d: Likewise.
* gas/mips/jal-mask-1.s: Source for the new tests.
* gas/mips/jal-mask-21.d: New test.
* gas/mips/jal-mask-22.d: Likewise.
* gas/mips/micromips@jal-mask-12.d: Likewise.
* gas/mips/jal-mask-2.s: Source for the new tests.
* gas/mips/mips.exp: Run the new tests.
* gas/mips/mips16-e.d: Add --special-syms to `objdump'.
* gas/mips/tmips16-e.d: Likewise.
* gas/mips/mipsel16-e.d: Likewise.
* gas/mips/tmipsel16-e.d: Likewise.
* gas/mips/and.s: Adjust padding.
* gas/mips/beq.s: Likewise.
* gas/mips/bge.s: Likewise.
* gas/mips/bgeu.s: Likewise.
* gas/mips/blt.s: Likewise.
* gas/mips/bltu.s: Likewise.
* gas/mips/branch-misc-2.s: Likewise.
* gas/mips/jal.s: Likewise.
* gas/mips/li.s: Likewise.
* gas/mips/mips4.s: Likewise.
* gas/mips/mips4-fp.s: Likewise.
* gas/mips/relax.s: Likewise.
* gas/mips/and.d: Update accordingly.
* gas/mips/elf-jal.d: Likewise.
* gas/mips/jal.d: Likewise.
* gas/mips/li.d: Likewise.
* gas/mips/relax-at.d: Likewise.
* gas/mips/relax.d: Likewise.
include/elf/
2011-02-25 Chao-ying Fu <fu@mips.com>
Maciej W. Rozycki <macro@codesourcery.com>
* mips.h (R_MICROMIPS_min): New relocations.
(R_MICROMIPS_26_S1): Likewise.
(R_MICROMIPS_HI16, R_MICROMIPS_LO16): Likewise.
(R_MICROMIPS_GPREL16, R_MICROMIPS_LITERAL): Likewise.
(R_MICROMIPS_GOT16, R_MICROMIPS_PC7_S1): Likewise.
(R_MICROMIPS_PC10_S1, R_MICROMIPS_PC16_S1): Likewise.
(R_MICROMIPS_CALL16, R_MICROMIPS_GOT_DISP): Likewise.
(R_MICROMIPS_GOT_PAGE, R_MICROMIPS_GOT_OFST): Likewise.
(R_MICROMIPS_GOT_HI16, R_MICROMIPS_GOT_LO16): Likewise.
(R_MICROMIPS_SUB, R_MICROMIPS_HIGHER): Likewise.
(R_MICROMIPS_HIGHEST, R_MICROMIPS_CALL_HI16): Likewise.
(R_MICROMIPS_CALL_LO16, R_MICROMIPS_SCN_DISP): Likewise.
(R_MICROMIPS_JALR, R_MICROMIPS_HI0_LO16): Likewise.
(R_MICROMIPS_TLS_GD, R_MICROMIPS_TLS_LDM): Likewise.
(R_MICROMIPS_TLS_DTPREL_HI, R_MICROMIPS_TLS_DTPREL_LO): Likewise.
(R_MICROMIPS_TLS_GOTTPREL): Likewise.
(R_MICROMIPS_TLS_TPREL_HI16): Likewise.
(R_MICROMIPS_TLS_TPREL_LO16): Likewise.
(R_MICROMIPS_GPREL7_S2, R_MICROMIPS_PC23_S2): Likewise.
(R_MICROMIPS_max): Likewise.
(EF_MIPS_ARCH_ASE_MICROMIPS): New macro.
(STO_MIPS_ISA, STO_MIPS_FLAGS): Likewise.
(ELF_ST_IS_MIPS_PLT, ELF_ST_SET_MIPS_PLT): Likewise.
(STO_MICROMIPS): Likewise.
(ELF_ST_IS_MICROMIPS, ELF_ST_SET_MICROMIPS): Likewise.
(ELF_ST_IS_COMPRESSED): Likewise.
(STO_MIPS_PLT, STO_MIPS_PIC): Rework.
(ELF_ST_IS_MIPS_PIC, ELF_ST_SET_MIPS_PIC): Likewise.
(STO_MIPS16, ELF_ST_IS_MIPS16, ELF_ST_SET_MIPS16): Likewise.
include/opcode/
2011-02-25 Chao-ying Fu <fu@mips.com>
Maciej W. Rozycki <macro@codesourcery.com>
* mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
(OP_MASK_STYPE, OP_SH_STYPE): Likewise.
(OP_MASK_CODE10, OP_SH_CODE10): Likewise.
(OP_MASK_TRAP, OP_SH_TRAP): Likewise.
(OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
(OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
(OP_MASK_RS3, OP_SH_RS3): Likewise.
(OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
(OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
(OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
(OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
(OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
(OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
(OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
(OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
(OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
(OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
(OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
(OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
(OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
(OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
(INSN_WRITE_GPR_S): New macro.
(INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise.
(INSN2_READ_FPR_D): Likewise.
(INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise.
(INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise.
(INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
(INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise.
(INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise.
(INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise.
(INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise.
(INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
(CPU_MICROMIPS): New macro.
(M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values.
(M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise.
(M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise.
(M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise.
(M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
(M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
(M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise.
(M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise.
(M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
(M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise.
(M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise.
(M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise.
(M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
(MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
(MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
(MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
(MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
(MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
(MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
(MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
(MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
(MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
(MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
(MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
(MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
(MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
(MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
(MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
(MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
(MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
(MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
(MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
(MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
(MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
(MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
(MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
(MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
(MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
(MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
(MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
(MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
(MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
(MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
(MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
(MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
(MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
(MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
(MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
(MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
(MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
(MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
(MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
(MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
(MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
(MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
(MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
(MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
(MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
(MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
(MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
(MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
(MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
(MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
(MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
(MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
(MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
(MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
(MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
(MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
(MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
(MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
(MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
(MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
(MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
(MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
(MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
(MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
(MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
(MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
(MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
(MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
(MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
(MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
(MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
(MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
(MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
(MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
(MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
(MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
(MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
(MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
(MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
(MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
(MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
(MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
(MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
(MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
(MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
(MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
(MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
(MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
(MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
(MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
(MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
(MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
(micromips_opcodes): New declaration.
(bfd_micromips_num_opcodes): Likewise.
ld/testsuite/
2011-02-25 Catherine Moore <clm@codesourcery.com>
Chao-ying Fu <fu@mips.com>
Maciej W. Rozycki <macro@codesourcery.com>
* lib/ld-lib.exp (run_dump_test): Support distinct assembler
flags for the same source named multiple times.
* ld-mips-elf/jalx-1.s: New test source.
* ld-mips-elf/jalx-1.d: New test output.
* ld-mips-elf/jalx-1.ld: New test linker script.
* ld-mips-elf/jalx-2-main.s: New test source.
* ld-mips-elf/jalx-2-ex.s: Likewise.
* ld-mips-elf/jalx-2-printf.s: Likewise.
* ld-mips-elf/jalx-2.dd: New test output.
* ld-mips-elf/jalx-2.ld: New test linker script.
* ld-mips-elf/mips16-and-micromips.d: New test.
* ld-mips-elf/mips-elf.exp: Run the new tests
opcodes/
2011-02-25 Chao-ying Fu <fu@mips.com>
Maciej W. Rozycki <macro@codesourcery.com>
* micromips-opc.c: New file.
* mips-dis.c (micromips_to_32_reg_b_map): New array.
(micromips_to_32_reg_c_map, micromips_to_32_reg_d_map): Likewise.
(micromips_to_32_reg_e_map, micromips_to_32_reg_f_map): Likewise.
(micromips_to_32_reg_g_map, micromips_to_32_reg_l_map): Likewise.
(micromips_to_32_reg_q_map): Likewise.
(micromips_imm_b_map, micromips_imm_c_map): Likewise.
(micromips_ase): New variable.
(is_micromips): New function.
(set_default_mips_dis_options): Handle microMIPS ASE.
(print_insn_micromips): New function.
(is_compressed_mode_p): Likewise.
(_print_insn_mips): Handle microMIPS instructions.
* Makefile.am (CFILES): Add micromips-opc.c.
* configure.in (bfd_mips_arch): Add micromips-opc.lo.
* Makefile.in: Regenerate.
* configure: Regenerate.
* mips-dis.c (micromips_to_32_reg_h_map): New variable.
(micromips_to_32_reg_i_map): Likewise.
(micromips_to_32_reg_m_map): Likewise.
(micromips_to_32_reg_n_map): New macro.
2011-07-24 14:20:15 +00:00
|
|
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2011-07-24 Chao-ying Fu <fu@mips.com>
|
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Maciej W. Rozycki <macro@codesourcery.com>
|
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|
|
* micromips-opc.c: New file.
|
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|
|
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* mips-dis.c (micromips_to_32_reg_b_map): New array.
|
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|
|
|
(micromips_to_32_reg_c_map, micromips_to_32_reg_d_map): Likewise.
|
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|
|
|
|
(micromips_to_32_reg_e_map, micromips_to_32_reg_f_map): Likewise.
|
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|
|
|
(micromips_to_32_reg_g_map, micromips_to_32_reg_l_map): Likewise.
|
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|
|
(micromips_to_32_reg_q_map): Likewise.
|
|
|
|
|
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(micromips_imm_b_map, micromips_imm_c_map): Likewise.
|
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|
(micromips_ase): New variable.
|
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(is_micromips): New function.
|
|
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(set_default_mips_dis_options): Handle microMIPS ASE.
|
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|
(print_insn_micromips): New function.
|
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(is_compressed_mode_p): Likewise.
|
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|
(_print_insn_mips): Handle microMIPS instructions.
|
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|
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* Makefile.am (CFILES): Add micromips-opc.c.
|
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* configure.in (bfd_mips_arch): Add micromips-opc.lo.
|
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* Makefile.in: Regenerate.
|
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* configure: Regenerate.
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* mips-dis.c (micromips_to_32_reg_h_map): New variable.
|
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(micromips_to_32_reg_i_map): Likewise.
|
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(micromips_to_32_reg_m_map): Likewise.
|
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(micromips_to_32_reg_n_map): New macro.
|
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2011-07-24 14:04:51 +00:00
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2011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
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* mips-opc.c (NODS): New macro.
|
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(TRAP): Adjust for the rename of INSN_TRAP to INSN_NO_DELAY_SLOT.
|
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(DSP_VOLA): Likewise.
|
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(mips_builtin_opcodes): Add NODS annotation to "deret" and
|
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"eret". Replace INSN_SYNC with NODS throughout. Use NODS in
|
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place of TRAP for "wait", "waiti" and "yield".
|
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* mips16-opc.c (NODS): New macro.
|
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(TRAP): Adjust for the rename of INSN_TRAP to INSN_NO_DELAY_SLOT.
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(mips16_opcodes): Use NODS in place of TRAP for "jalrc", "jrc",
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"restore" and "save".
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2011-07-22 20:22:38 +00:00
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2011-07-22 H.J. Lu <hongjiu.lu@intel.com>
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* configure.in: Handle bfd_k1om_arch.
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* configure: Regenerated.
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* disassemble.c (disassembler): Handle bfd_k1om_arch.
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* i386-dis.c (print_insn): Handle bfd_mach_k1om and
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bfd_mach_k1om_intel_syntax.
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* i386-gen.c (cpu_flag_init): Set CPU_UNKNOWN_FLAGS to
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~(CpuL1OM|CpuK1OM). Add CPU_K1OM_FLAGS.
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(cpu_flags): Add CpuK1OM.
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* i386-opc.h (CpuK1OM): New.
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(i386_cpu_flags): Add cpuk1om.
|
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* i386-init.h: Regenerated.
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* i386-tbl.h: Likewise.
|
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2011-07-12 08:45:45 +00:00
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2011-07-12 Nick Clifton <nickc@redhat.com>
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* arm-dis.c (print_insn_arm): Revert previous, undocumented,
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|
accidental change.
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2011-07-01 16:11:27 +00:00
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2011-07-01 Nick Clifton <nickc@redhat.com>
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|
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PR binutils/12329
|
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* avr-dis.c (avr_operand): Fix disassembly of ELPM, LPM and SPM
|
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insns using post-increment addressing.
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2011-07-01 01:34:35 +00:00
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2011-06-30 H.J. Lu <hongjiu.lu@intel.com>
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* i386-dis.c (vex_len_table): Update rorxS.
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2011-06-30 15:44:55 +00:00
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2011-06-30 H.J. Lu <hongjiu.lu@intel.com>
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AVX Programming Reference (June, 2011)
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* i386-dis.c (vex_len_table): Correct rorxS.
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* i386-opc.tbl: Correct rorx.
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* i386-tbl.h: Regenerated.
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2011-06-29 20:46:11 +00:00
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2011-06-29 H.J. Lu <hongjiu.lu@intel.com>
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* tilegx-opc.c (find_opcode): Replace "index" with "i".
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* tilepro-opc.c (find_opcode): Likewise.
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2011-06-29 20:42:48 +00:00
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2011-06-29 Richard Sandiford <rdsandiford@googlemail.com>
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* mips16-opc.c (jalrc, jrc): Move earlier in file.
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2011-06-21 17:56:46 +00:00
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2011-06-21 H.J. Lu <hongjiu.lu@intel.com>
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* i386-dis.c (prefix_table): Re-indent PREFIX_VEX_0F388C and
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PREFIX_VEX_0F388E.
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2011-06-17 15:06:46 +00:00
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2011-06-17 Andreas Schwab <schwab@redhat.com>
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* Makefile.am (MAINTAINERCLEANFILES): Move s390-opc.tab ...
|
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(MOSTLYCLEANFILES): ... here.
|
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* Makefile.in: Regenerate.
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2011-06-14 05:11:52 +00:00
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2011-06-14 Alan Modra <amodra@gmail.com>
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* Makefile.in: Regenerate.
|
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* Makefile.am (ALL_MACHINES): Add cpu-tilegx.lo and cpu-tilepro.lo.
(ALL_MACHINE_CFILES): Add cpu-tilegx.c and cpu-tilepro.c.
(BFD32_BACKENDS): Add elf32-tilegx.lo, elf32-tilepro.lo,
and elfxx-tilegx.lo.
(BFD32_BACKENDS_CFILES): Add elf32-tilegx.c elf32-tilepro.c, and
elfxx-tilegx.c.
(BFD64_BACKENDS): Add elf64-tilegx.lo.
(BFD64_BACKENDS_CFILES): Add elf64-tilegx.c.
* Makefile.in: Regenerate.
* arctures.c (bfd_architecture): Define bfd_arch_tilepro,
bfd_arch_tilegx, bfd_mach_tilepro, bfd_mach_tilegx.
(bfd_arch_info): Add bfd_tilegx_arch, bfd_tilepro_arch.
(bfd_archures_list): Add bfd_tilegx_arch, bfd_tilepro_arch.
bfd-in2.h: Regenerate.
* config.bfd: Handle tilegx-*-* and tilepro-*-*.
* configure.in: Handle bfd_elf32_tilegx_vec, bfd_elf32_tilepro_vec,
and bfd_elf64_tilegx_vec.
* configure: Regenerate.
* elf-bfd.h (enum elf_target_id): Define TILEGX_ELF_DATA and
TILEPRO_ELF_DATA.
* libbfd.h: Regenerate.
* reloc.c: Add BFD_RELOC_TILEPRO_{COPY, GLOB_DAT, JMP_SLOT,
RELATIVE, BROFF_X1, JOFFLONG_X1, JOFFLONG_X1_PLT, IMM8_X0,
IMM8_Y0, IMM8_X1, IMM8_Y1, DEST_IMM8_X1, MT_IMM15_X1, MF_IMM15_X1,
IMM16_X0, IMM16_X1, IMM16_X0_LO, IMM16_X1_LO, IMM16_X0_HI,
IMM16_X1_HI, IMM16_X0_HA, IMM16_X1_HA, IMM16_X0_PCREL,
IMM16_X1_PCREL, IMM16_X0_LO_PCREL, IMM16_X1_LO_PCREL,
IMM16_X0_HI_PCREL, IMM16_X1_HI_PCREL, IMM16_X0_HA_PCREL,
IMM16_X1_HA_PCREL, IMM16_X0_GOT, IMM16_X1_GOT, IMM16_X0_GOT_LO,
IMM16_X1_GOT_LO, IMM16_X0_GOT_HI, IMM16_X1_GOT_HI,
IMM16_X0_GOT_HA, IMM16_X1_GOT_HA, MMSTART_X0, MMEND_X0,
MMSTART_X1, MMEND_X1, SHAMT_X0, SHAMT_X1, SHAMT_Y0, SHAMT_Y1,
IMM16_X0_TLS_GD, IMM16_X1_TLS_GD, IMM16_X0_TLS_GD_LO,
IMM16_X1_TLS_GD_LO, IMM16_X0_TLS_GD_HI, IMM16_X1_TLS_GD_HI,
IMM16_X0_TLS_GD_HA, IMM16_X1_TLS_GD_HA, IMM16_X0_TLS_IE,
IMM16_X1_TLS_IE, IMM16_X0_TLS_IE_LO, IMM16_X1_TLS_IE_LO,
IMM16_X0_TLS_IE_HI, IMM16_X1_TLS_IE_HI, IMM16_X0_TLS_IE_HA,
IMM16_X1_TLS_IE_HA, TLS_DTPMOD32, TLS_DTPOFF32, TLS_TPOFF32}
Add BFD_RELOC_TILEGX_{HW0, HW1, HW2, HW3, HW0_LAST, HW1_LAST,
HW2_LAST, COPY, GLOB_DAT, JMP_SLOT, RELATIVE, BROFF_X1,
JUMPOFF_X1, JUMPOFF_X1_PLT, IMM8_X0, IMM8_Y0, IMM8_X1, IMM8_Y1,
DEST_IMM8_X1, MT_IMM14_X1, MF_IMM14_X1, MMSTART_X0, MMEND_X0,
SHAMT_X0, SHAMT_X1, SHAMT_Y0, SHAMT_Y1, IMM16_X0_HW0,
IMM16_X1_HW0, IMM16_X0_HW1, IMM16_X1_HW1, IMM16_X0_HW2,
IMM16_X1_HW2, IMM16_X0_HW3, IMM16_X1_HW3, IMM16_X0_HW0_LAST,
IMM16_X1_HW0_LAST, IMM16_X0_HW1_LAST, IMM16_X1_HW1_LAST,
IMM16_X0_HW2_LAST, IMM16_X1_HW2_LAST, IMM16_X0_HW0_PCREL,
IMM16_X1_HW0_PCREL, IMM16_X0_HW1_PCREL, IMM16_X1_HW1_PCREL,
IMM16_X0_HW2_PCREL, IMM16_X1_HW2_PCREL, IMM16_X0_HW3_PCREL,
IMM16_X1_HW3_PCREL, IMM16_X0_HW0_LAST_PCREL,
IMM16_X1_HW0_LAST_PCREL, IMM16_X0_HW1_LAST_PCREL,
IMM16_X1_HW1_LAST_PCREL, IMM16_X0_HW2_LAST_PCREL,
IMM16_X1_HW2_LAST_PCREL, IMM16_X0_HW0_GOT, IMM16_X1_HW0_GOT,
IMM16_X0_HW1_GOT, IMM16_X1_HW1_GOT, IMM16_X0_HW2_GOT,
IMM16_X1_HW2_GOT, IMM16_X0_HW3_GOT, IMM16_X1_HW3_GOT,
IMM16_X0_HW0_LAST_GOT, IMM16_X1_HW0_LAST_GOT,
IMM16_X0_HW1_LAST_GOT, IMM16_X1_HW1_LAST_GOT,
IMM16_X0_HW2_LAST_GOT, IMM16_X1_HW2_LAST_GOT, IMM16_X0_HW0_TLS_GD,
IMM16_X1_HW0_TLS_GD, IMM16_X0_HW1_TLS_GD, IMM16_X1_HW1_TLS_GD,
IMM16_X0_HW2_TLS_GD, IMM16_X1_HW2_TLS_GD, IMM16_X0_HW3_TLS_GD,
IMM16_X1_HW3_TLS_GD, IMM16_X0_HW0_LAST_TLS_GD,
IMM16_X1_HW0_LAST_TLS_GD, IMM16_X0_HW1_LAST_TLS_GD,
IMM16_X1_HW1_LAST_TLS_GD, IMM16_X0_HW2_LAST_TLS_GD,
IMM16_X1_HW2_LAST_TLS_GD, IMM16_X0_HW0_TLS_IE,
IMM16_X1_HW0_TLS_IE, IMM16_X0_HW1_TLS_IE, IMM16_X1_HW1_TLS_IE,
IMM16_X0_HW2_TLS_IE, IMM16_X1_HW2_TLS_IE, IMM16_X0_HW3_TLS_IE,
IMM16_X1_HW3_TLS_IE, IMM16_X0_HW0_LAST_TLS_IE,
IMM16_X1_HW0_LAST_TLS_IE, IMM16_X0_HW1_LAST_TLS_IE,
IMM16_X1_HW1_LAST_TLS_IE, IMM16_X0_HW2_LAST_TLS_IE,
IMM16_X1_HW2_LAST_TLS_IE, TLS_DTPMOD64, TLS_DTPOFF64, TLS_TPOFF64,
TLS_DTPMOD32, TLS_DTPOFF32, TLS_TPOFF32}
* targets.c (bfd_elf32_tilegx_vec): Declare.
(bfd_elf32_tilepro_vec): Declare.
(bfd_elf64_tilegx_vec): Declare.
(bfd_target_vector): Add bfd_elf32_tilegx_vec, bfd_elf32_tilepro_vec,
and bfd_elf64_tilegx_vec.
* cpu-tilegx.c: New file.
* cpu-tilepro.c: New file.
* elf32-tilepro.h: New file.
* elf32-tilepro.c: New file.
* elf32-tilegx.c: New file.
* elf32-tilegx.h: New file.
* elf64-tilegx.c: New file.
* elf64-tilegx.h: New file.
* elfxx-tilegx.c: New file.
* elfxx-tilegx.h: New file.
* Makefile.am (TARGET_CPU_CFILES): Add config/tc-tilegx.c and
config/tc-tilepro.c.
(TARGET_CPU_HFILES): Add config/tc-tilegx.h and
config/tc-tilepro.h.
* Makefile.in: Regenerate.
* configure.tgt (tilepro-*-*): New.
(tilegx-*-*): Likewise.
* config/tc-tilegx.c: New file.
* config/tc-tilegx.h: Likewise.
* config/tc-tilepro.h: Likewise.
* config/tc-tilepro.c: Likewise.
* doc/Makefile.am (CPU_DOCS): Add c-tilegx.texi and
c-tilepro.texi.
* doc/Makefile.in: Regenerate.
* doc/all.texi (TILEGX): Define.
(TILEPRO): Define.
* doc/as.texinfo: Add Tile-Gx and TILEPro documentation. Include
c-tilegx.texi and c-tilepro.texi.
* doc/c-tilegx.texi: New.
* doc/c-tilepro.texi: New.
* gas/tilepro/t_constants.s: New file.
* gas/tilepro/t_constants.d: Likewise.
* gas/tilepro/t_insns.s: Likewise.
* gas/tilepro/tilepro.exp: Likewise.
* gas/tilepro/t_insns.d: Likewise.
* gas/tilegx/tilegx.exp: Likewise.
* gas/tilegx/t_insns.d: Likewise.
* gas/tilegx/t_insns.s: Likewise.
* dis-asm.h (print_insn_tilegx): Declare.
(print_insn_tilepro): Likewise.
* tilegx.h: New file.
* tilepro.h: New file.
* common.h: Add EM_TILEGX.
* tilegx.h: New file.
* tilepro.h: New file.
* Makefile.am (ALL_EMULATION_SOURCES): Add eelf32tilegx.c and
eelf32tilepro.c.
(ALL_64_EMULATION_SOURCES): Add eelf64tilegx.c.
(eelf32tilegx.c): New target.
(eelf32tilepro.c): Likewise.
(eelf64tilegx.c): Likewise.
* Makefile.in: Regenerate.
* configure.tgt: Handle tilegx-*-* and tilepro-*-*.
* emulparams/elf32tilegx.sh: New file.
* emulparams/elf64tilegx.sh: New file.
* emulparams/elf32tilepro.sh: New file.
* ld-elf/eh5.d: Don't run on tile*.
* ld-srec/srec.exp: xfail on tile*.
* ld-tilegx/external.s: New file.
* ld-tilegx/reloc.d: New file.
* ld-tilegx/reloc.s: New file.
* ld-tilegx/tilegx.exp: New file.
* ld-tilepro/external.s: New file.
* ld-tilepro/reloc.d: New file.
* ld-tilepro/reloc.s: New file.
* ld-tilepro/tilepro.exp: New file.
* Makefile.am (TARGET_LIBOPCODES_CFILES): Add tilegx-dis.c,
tilegx-opc.c, tilepro-dis.c, and tilepro-opc.c.
* Makefile.in: Regenerate.
* configure.in: Handle bfd_tilegx_arch and bfd_tilepro_arch.
* configure: Regenerate.
* disassemble.c (disassembler): Add ARCH_tilegx and ARCH_tilepro.
* po/POTFILES.in: Regenerate.
* tilegx-dis.c: New file.
* tilegx-opc.c: New file.
* tilepro-dis.c: New file.
* tilepro-opc.c: New file.
2011-06-13 15:18:54 +00:00
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2011-06-13 Walter Lee <walt@tilera.com>
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* Makefile.am (TARGET_LIBOPCODES_CFILES): Add tilegx-dis.c,
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tilegx-opc.c, tilepro-dis.c, and tilepro-opc.c.
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* Makefile.in: Regenerate.
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* configure.in: Handle bfd_tilegx_arch and bfd_tilepro_arch.
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* configure: Regenerate.
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* disassemble.c (disassembler): Add ARCH_tilegx and ARCH_tilepro.
|
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* po/POTFILES.in: Regenerate.
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* tilegx-dis.c: New file.
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* tilegx-opc.c: New file.
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* tilepro-dis.c: New file.
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* tilepro-opc.c: New file.
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Support AVX Programming Reference (June, 2011).
gas/
2011-06-10 H.J. Lu <hongjiu.lu@intel.com>
AVX Programming Reference (June, 2011)
* config/tc-i386.c (i386_error): Add invalid_vsib_address and
unsupported_vector_index_register.
(cpu_arch): Add .avx2, .bmi2, .lzcnt and .invpcid.
(check_VecOperands): New.
(match_template): Call check_VecOperands. Handle
invalid_vsib_address and unsupported_vector_index_register.
(build_modrm_byte): Support VecSIB. Check register-only source
operand when two source operands are swapped.
(i386_index_check): Allow Xmm/Ymm index registers.
* doc/c-i386.texi: Document avx2/.avx2, bmi2/.bmi2, lzcnt/.lzcnt
and invpcid./invpcid.
gas/testsuite/
2011-06-10 H.J. Lu <hongjiu.lu@intel.com>
AVX Programming Reference (June, 2011)
* gas/i386/arch-10-1.l: Updated.
* gas/i386/arch-10-2.l: Likewise.
* gas/i386/arch-10-3.l: Likewise.
* gas/i386/arch-10-4.l: Likewise.
* gas/i386/arch-10.s: Add LZCNT to comments.
* gas/i386/x86-64-arch-2.s: Likewise.
* gas/i386/arch-10-lzcnt.d: New.
* gas/i386/avx-gather-intel.d: Likewise.
* gas/i386/avx-gather.d: Likewise.
* gas/i386/avx-gather.s: Likewise.
* gas/i386/avx2-intel.d: Likewise.
* gas/i386/avx2.d: Likewise.
* gas/i386/avx2.s: Likewise
* gas/i386/avx256int-intel.d: Likewise.
* gas/i386/avx256int.d: Likewise.
* gas/i386/avx256int.s: Likewise.
* gas/i386/bmi2-intel.d: Likewise.
* gas/i386/bmi2.d: Likewise.
* gas/i386/bmi2.s: Likewise.
* gas/i386/inval-invpcid.l:Likewise.
* gas/i386/inval-invpcid.s: Likewise.
* gas/i386/invpcid-intel.d: Likewise.
* gas/i386/invpcid.d: Likewise.
* gas/i386/invpcid.s: Likewise.
* gas/i386/x86-64-arch-2-lzcnt.d: Likewise.
* gas/i386/x86-64-avx-gather-intel.d: Likewise.
* gas/i386/x86-64-avx-gather.d: Likewise.
* gas/i386/x86-64-avx-gather.s: Likewise.
* gas/i386/x86-64-avx2-intel.d: Likewise.
* gas/i386/x86-64-avx2.d: Likewise.
* gas/i386/x86-64-avx2.s: Likewise.
* gas/i386/x86-64-avx256int-intel.d: Likewise.
* gas/i386/x86-64-avx256int.d: Likewise.
* gas/i386/x86-64-avx256int.s: Likewise.
* gas/i386/x86-64-bmi2-intel.d: Likewise.
* gas/i386/x86-64-bmi2.d: Likewise.
* gas/i386/x86-64-bmi2.s: Likewise.
* gas/i386/x86-64-inval-invpcid.l: Likewise.
* gas/i386/x86-64-inval-invpcid.s: Likewise.
* gas/i386/x86-64-invpcid-intel.d: Likewise.
* gas/i386/x86-64-invpcid.d: Likewise.
* gas/i386/x86-64-invpcid.s: Likewise.
opcodes/
2011-06-10 H.J. Lu <hongjiu.lu@intel.com>
AVX Programming Reference (June, 2011)
* i386-dis.c (XMGatherQ): New.
* i386-dis.c (EXxmm_mb): New.
(EXxmm_mb): Likewise.
(EXxmm_mw): Likewise.
(EXxmm_md): Likewise.
(EXxmm_mq): Likewise.
(EXxmmdw): Likewise.
(EXxmmqd): Likewise.
(VexGatherQ): Likewise.
(MVexVSIBDWpX): Likewise.
(MVexVSIBQWpX): Likewise.
(xmm_mb_mode): Likewise.
(xmm_mw_mode): Likewise.
(xmm_md_mode): Likewise.
(xmm_mq_mode): Likewise.
(xmmdw_mode): Likewise.
(xmmqd_mode): Likewise.
(ymmxmm_mode): Likewise.
(vex_vsib_d_w_dq_mode): Likewise.
(vex_vsib_q_w_dq_mode): Likewise.
(MOD_VEX_0F385A_PREFIX_2): Likewise.
(MOD_VEX_0F388C_PREFIX_2): Likewise.
(MOD_VEX_0F388E_PREFIX_2): Likewise.
(PREFIX_0F3882): Likewise.
(PREFIX_VEX_0F3816): Likewise.
(PREFIX_VEX_0F3836): Likewise.
(PREFIX_VEX_0F3845): Likewise.
(PREFIX_VEX_0F3846): Likewise.
(PREFIX_VEX_0F3847): Likewise.
(PREFIX_VEX_0F3858): Likewise.
(PREFIX_VEX_0F3859): Likewise.
(PREFIX_VEX_0F385A): Likewise.
(PREFIX_VEX_0F3878): Likewise.
(PREFIX_VEX_0F3879): Likewise.
(PREFIX_VEX_0F388C): Likewise.
(PREFIX_VEX_0F388E): Likewise.
(PREFIX_VEX_0F3890..PREFIX_VEX_0F3893): Likewise.
(PREFIX_VEX_0F38F5): Likewise.
(PREFIX_VEX_0F38F6): Likewise.
(PREFIX_VEX_0F3A00): Likewise.
(PREFIX_VEX_0F3A01): Likewise.
(PREFIX_VEX_0F3A02): Likewise.
(PREFIX_VEX_0F3A38): Likewise.
(PREFIX_VEX_0F3A39): Likewise.
(PREFIX_VEX_0F3A46): Likewise.
(PREFIX_VEX_0F3AF0): Likewise.
(VEX_LEN_0F3816_P_2): Likewise.
(VEX_LEN_0F3819_P_2): Likewise.
(VEX_LEN_0F3836_P_2): Likewise.
(VEX_LEN_0F385A_P_2_M_0): Likewise.
(VEX_LEN_0F38F5_P_0): Likewise.
(VEX_LEN_0F38F5_P_1): Likewise.
(VEX_LEN_0F38F5_P_3): Likewise.
(VEX_LEN_0F38F6_P_3): Likewise.
(VEX_LEN_0F38F7_P_1): Likewise.
(VEX_LEN_0F38F7_P_2): Likewise.
(VEX_LEN_0F38F7_P_3): Likewise.
(VEX_LEN_0F3A00_P_2): Likewise.
(VEX_LEN_0F3A01_P_2): Likewise.
(VEX_LEN_0F3A38_P_2): Likewise.
(VEX_LEN_0F3A39_P_2): Likewise.
(VEX_LEN_0F3A46_P_2): Likewise.
(VEX_LEN_0F3AF0_P_3): Likewise.
(VEX_W_0F3816_P_2): Likewise.
(VEX_W_0F3818_P_2): Likewise.
(VEX_W_0F3819_P_2): Likewise.
(VEX_W_0F3836_P_2): Likewise.
(VEX_W_0F3846_P_2): Likewise.
(VEX_W_0F3858_P_2): Likewise.
(VEX_W_0F3859_P_2): Likewise.
(VEX_W_0F385A_P_2_M_0): Likewise.
(VEX_W_0F3878_P_2): Likewise.
(VEX_W_0F3879_P_2): Likewise.
(VEX_W_0F3A00_P_2): Likewise.
(VEX_W_0F3A01_P_2): Likewise.
(VEX_W_0F3A02_P_2): Likewise.
(VEX_W_0F3A38_P_2): Likewise.
(VEX_W_0F3A39_P_2): Likewise.
(VEX_W_0F3A46_P_2): Likewise.
(MOD_VEX_0F3818_PREFIX_2): Removed.
(MOD_VEX_0F3819_PREFIX_2): Likewise.
(VEX_LEN_0F60_P_2..VEX_LEN_0F6D_P_2): Likewise.
(VEX_LEN_0F70_P_1..VEX_LEN_0F76_P_2): Likewise.
(VEX_LEN_0FD1_P_2..VEX_LEN_0FD5_P_2): Likewise.
(VEX_LEN_0FD7_P_2_M_1..VEX_LEN_0F3819_P_2_M_0): Likewise.
(VEX_LEN_0F381C_P_2..VEX_LEN_0F3840_P_2): Likewise.
(VEX_LEN_0F3A0E_P_2): Likewise.
(VEX_LEN_0F3A0F_P_2): Likewise.
(VEX_LEN_0F3A42_P_2): Likewise.
(VEX_LEN_0F3A4C_P_2): Likewise.
(VEX_W_0F3818_P_2_M_0): Likewise.
(VEX_W_0F3819_P_2_M_0): Likewise.
(prefix_table): Updated.
(three_byte_table): Likewise.
(vex_table): Likewise.
(vex_len_table): Likewise.
(vex_w_table): Likewise.
(mod_table): Likewise.
(putop): Handle "LW".
(intel_operand_size): Handle xmm_mb_mode, xmm_mw_mode,
xmm_md_mode, xmm_mq_mode, xmmdw_mode, xmmqd_mode, ymmxmm_mode,
vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode.
(OP_EX): Likewise.
(OP_E_memory): Handle vex_vsib_d_w_dq_mode and
vex_vsib_q_w_dq_mode.
(OP_XMM): Handle vex_vsib_q_w_dq_mode.
(OP_VEX): Likewise.
* i386-gen.c (cpu_flag_init): Add CpuAVX2 to CPU_ANY_SSE_FLAGS
and CPU_ANY_AVX_FLAGS. Add CPU_BMI2_FLAGS, CPU_LZCNT_FLAGS,
CPU_INVPCID_FLAGS and CPU_AVX2_FLAGS.
(cpu_flags): Add CpuAVX2, CpuBMI2, CpuLZCNT and CpuINVPCID.
(opcode_modifiers): Add VecSIB.
* i386-opc.h (CpuAVX2): New.
(CpuBMI2): Likewise.
(CpuLZCNT): Likewise.
(CpuINVPCID): Likewise.
(VecSIB128): Likewise.
(VecSIB256): Likewise.
(VecSIB): Likewise.
(i386_cpu_flags): Add cpuavx2, cpubmi2, cpulzcnt and cpuinvpcid.
(i386_opcode_modifier): Add vecsib.
* i386-opc.tbl: Add invpcid, AVX2 and BMI2 instructions.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
2011-06-10 21:27:40 +00:00
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2011-06-10 H.J. Lu <hongjiu.lu@intel.com>
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AVX Programming Reference (June, 2011)
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* i386-dis.c (XMGatherQ): New.
|
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|
|
* i386-dis.c (EXxmm_mb): New.
|
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(EXxmm_mb): Likewise.
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(EXxmm_mw): Likewise.
|
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(EXxmm_md): Likewise.
|
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(EXxmm_mq): Likewise.
|
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(EXxmmdw): Likewise.
|
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(EXxmmqd): Likewise.
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(VexGatherQ): Likewise.
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(MVexVSIBDWpX): Likewise.
|
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(MVexVSIBQWpX): Likewise.
|
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(xmm_mb_mode): Likewise.
|
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(xmm_mw_mode): Likewise.
|
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|
(xmm_md_mode): Likewise.
|
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(xmm_mq_mode): Likewise.
|
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(xmmdw_mode): Likewise.
|
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(xmmqd_mode): Likewise.
|
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(ymmxmm_mode): Likewise.
|
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(vex_vsib_d_w_dq_mode): Likewise.
|
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|
|
(vex_vsib_q_w_dq_mode): Likewise.
|
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(MOD_VEX_0F385A_PREFIX_2): Likewise.
|
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(MOD_VEX_0F388C_PREFIX_2): Likewise.
|
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|
(MOD_VEX_0F388E_PREFIX_2): Likewise.
|
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(PREFIX_0F3882): Likewise.
|
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(PREFIX_VEX_0F3816): Likewise.
|
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(PREFIX_VEX_0F3836): Likewise.
|
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(PREFIX_VEX_0F3845): Likewise.
|
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(PREFIX_VEX_0F3846): Likewise.
|
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(PREFIX_VEX_0F3847): Likewise.
|
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|
(PREFIX_VEX_0F3858): Likewise.
|
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|
(PREFIX_VEX_0F3859): Likewise.
|
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(PREFIX_VEX_0F385A): Likewise.
|
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|
(PREFIX_VEX_0F3878): Likewise.
|
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|
(PREFIX_VEX_0F3879): Likewise.
|
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|
(PREFIX_VEX_0F388C): Likewise.
|
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|
|
(PREFIX_VEX_0F388E): Likewise.
|
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(PREFIX_VEX_0F3890..PREFIX_VEX_0F3893): Likewise.
|
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|
(PREFIX_VEX_0F38F5): Likewise.
|
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|
(PREFIX_VEX_0F38F6): Likewise.
|
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(PREFIX_VEX_0F3A00): Likewise.
|
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(PREFIX_VEX_0F3A01): Likewise.
|
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(PREFIX_VEX_0F3A02): Likewise.
|
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(PREFIX_VEX_0F3A38): Likewise.
|
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(PREFIX_VEX_0F3A39): Likewise.
|
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(PREFIX_VEX_0F3A46): Likewise.
|
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|
(PREFIX_VEX_0F3AF0): Likewise.
|
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(VEX_LEN_0F3816_P_2): Likewise.
|
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(VEX_LEN_0F3819_P_2): Likewise.
|
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(VEX_LEN_0F3836_P_2): Likewise.
|
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(VEX_LEN_0F385A_P_2_M_0): Likewise.
|
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(VEX_LEN_0F38F5_P_0): Likewise.
|
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(VEX_LEN_0F38F5_P_1): Likewise.
|
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(VEX_LEN_0F38F5_P_3): Likewise.
|
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(VEX_LEN_0F38F6_P_3): Likewise.
|
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(VEX_LEN_0F38F7_P_1): Likewise.
|
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(VEX_LEN_0F38F7_P_2): Likewise.
|
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(VEX_LEN_0F38F7_P_3): Likewise.
|
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(VEX_LEN_0F3A00_P_2): Likewise.
|
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(VEX_LEN_0F3A01_P_2): Likewise.
|
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(VEX_LEN_0F3A38_P_2): Likewise.
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(VEX_LEN_0F3A39_P_2): Likewise.
|
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(VEX_LEN_0F3A46_P_2): Likewise.
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(VEX_LEN_0F3AF0_P_3): Likewise.
|
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(VEX_W_0F3816_P_2): Likewise.
|
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(VEX_W_0F3818_P_2): Likewise.
|
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(VEX_W_0F3819_P_2): Likewise.
|
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(VEX_W_0F3836_P_2): Likewise.
|
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(VEX_W_0F3846_P_2): Likewise.
|
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(VEX_W_0F3858_P_2): Likewise.
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(VEX_W_0F3859_P_2): Likewise.
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(VEX_W_0F385A_P_2_M_0): Likewise.
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(VEX_W_0F3878_P_2): Likewise.
|
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(VEX_W_0F3879_P_2): Likewise.
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(VEX_W_0F3A00_P_2): Likewise.
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(VEX_W_0F3A01_P_2): Likewise.
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(VEX_W_0F3A02_P_2): Likewise.
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(VEX_W_0F3A38_P_2): Likewise.
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(VEX_W_0F3A39_P_2): Likewise.
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(VEX_W_0F3A46_P_2): Likewise.
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(MOD_VEX_0F3818_PREFIX_2): Removed.
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(MOD_VEX_0F3819_PREFIX_2): Likewise.
|
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(VEX_LEN_0F60_P_2..VEX_LEN_0F6D_P_2): Likewise.
|
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(VEX_LEN_0F70_P_1..VEX_LEN_0F76_P_2): Likewise.
|
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(VEX_LEN_0FD1_P_2..VEX_LEN_0FD5_P_2): Likewise.
|
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(VEX_LEN_0FD7_P_2_M_1..VEX_LEN_0F3819_P_2_M_0): Likewise.
|
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(VEX_LEN_0F381C_P_2..VEX_LEN_0F3840_P_2): Likewise.
|
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|
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(VEX_LEN_0F3A0E_P_2): Likewise.
|
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(VEX_LEN_0F3A0F_P_2): Likewise.
|
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(VEX_LEN_0F3A42_P_2): Likewise.
|
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(VEX_LEN_0F3A4C_P_2): Likewise.
|
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(VEX_W_0F3818_P_2_M_0): Likewise.
|
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|
|
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|
(VEX_W_0F3819_P_2_M_0): Likewise.
|
|
|
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|
|
(prefix_table): Updated.
|
|
|
|
|
|
(three_byte_table): Likewise.
|
|
|
|
|
|
(vex_table): Likewise.
|
|
|
|
|
|
(vex_len_table): Likewise.
|
|
|
|
|
|
(vex_w_table): Likewise.
|
|
|
|
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|
(mod_table): Likewise.
|
|
|
|
|
|
(putop): Handle "LW".
|
|
|
|
|
|
(intel_operand_size): Handle xmm_mb_mode, xmm_mw_mode,
|
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|
|
|
xmm_md_mode, xmm_mq_mode, xmmdw_mode, xmmqd_mode, ymmxmm_mode,
|
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|
|
|
vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode.
|
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(OP_EX): Likewise.
|
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|
|
|
|
(OP_E_memory): Handle vex_vsib_d_w_dq_mode and
|
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|
vex_vsib_q_w_dq_mode.
|
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(OP_XMM): Handle vex_vsib_q_w_dq_mode.
|
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|
(OP_VEX): Likewise.
|
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|
* i386-gen.c (cpu_flag_init): Add CpuAVX2 to CPU_ANY_SSE_FLAGS
|
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|
|
|
and CPU_ANY_AVX_FLAGS. Add CPU_BMI2_FLAGS, CPU_LZCNT_FLAGS,
|
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|
CPU_INVPCID_FLAGS and CPU_AVX2_FLAGS.
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|
|
(cpu_flags): Add CpuAVX2, CpuBMI2, CpuLZCNT and CpuINVPCID.
|
|
|
|
|
|
(opcode_modifiers): Add VecSIB.
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.h (CpuAVX2): New.
|
|
|
|
|
|
(CpuBMI2): Likewise.
|
|
|
|
|
|
(CpuLZCNT): Likewise.
|
|
|
|
|
|
(CpuINVPCID): Likewise.
|
|
|
|
|
|
(VecSIB128): Likewise.
|
|
|
|
|
|
(VecSIB256): Likewise.
|
|
|
|
|
|
(VecSIB): Likewise.
|
|
|
|
|
|
(i386_cpu_flags): Add cpuavx2, cpubmi2, cpulzcnt and cpuinvpcid.
|
|
|
|
|
|
(i386_opcode_modifier): Add vecsib.
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl: Add invpcid, AVX2 and BMI2 instructions.
|
|
|
|
|
|
* i386-init.h: Regenerated.
|
|
|
|
|
|
* i386-tbl.h: Likewise.
|
|
|
|
|
|
|
2011-06-03 20:06:20 +00:00
|
|
|
|
2011-06-03 Quentin Neill <quentin.neill@amd.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-gen.c (cpu_flag_init): Add CpuF16C to CPU_BDVER2_FLAGS.
|
|
|
|
|
|
* i386-init.h: Regenerated.
|
|
|
|
|
|
|
2011-06-03 10:04:03 +00:00
|
|
|
|
2011-06-03 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR binutils/12752
|
|
|
|
|
|
* arm-dis.c (print_insn_coprocessor): Use bfd_vma type for
|
|
|
|
|
|
computing address offsets.
|
|
|
|
|
|
(print_arm_address): Likewise.
|
|
|
|
|
|
(print_insn_arm): Likewise.
|
|
|
|
|
|
(print_insn_thumb16): Likewise.
|
|
|
|
|
|
(print_insn_thumb32): Likewise.
|
|
|
|
|
|
|
2011-06-02 15:32:10 +00:00
|
|
|
|
2011-06-02 Jie Zhang <jie@codesourcery.com>
|
|
|
|
|
|
Nathan Sidwell <nathan@codesourcery.com>
|
|
|
|
|
|
Maciej Rozycki <macro@codesourcery.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arm-dis.c (print_insn_coprocessor): Explicitly print #-0
|
|
|
|
|
|
as address offset.
|
|
|
|
|
|
(print_arm_address): Likewise. Elide positive #0 appropriately.
|
|
|
|
|
|
(print_insn_arm): Likewise.
|
|
|
|
|
|
|
2011-06-03 10:04:03 +00:00
|
|
|
|
2011-06-02 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR gas/12752
|
|
|
|
|
|
* arm-dis.c (print_insn_thumb32): Do not sign extend addresses
|
|
|
|
|
|
passed to print_address_func.
|
|
|
|
|
|
|
2011-06-02 13:43:24 +00:00
|
|
|
|
2011-06-02 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arm-dis.c: Fix spelling mistakes.
|
|
|
|
|
|
* op/opcodes.pot: Regenerate.
|
|
|
|
|
|
|
2011-05-24 16:13:31 +00:00
|
|
|
|
2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* s390-opc.c: Replace S390_OPERAND_REG_EVEN with
|
|
|
|
|
|
S390_OPERAND_REG_PAIR. Fix INSTR_RRF_0UFEF instruction type.
|
|
|
|
|
|
* s390-opc.txt: Fix cxr instruction type.
|
|
|
|
|
|
|
2011-05-24 13:33:57 +00:00
|
|
|
|
2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* s390-opc.c: Add new instruction types marking register pair
|
|
|
|
|
|
operands.
|
|
|
|
|
|
* s390-opc.txt: Match instructions having register pair operands
|
|
|
|
|
|
to the new instruction types.
|
|
|
|
|
|
|
2011-05-19 11:10:59 +00:00
|
|
|
|
2011-05-19 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* v850-opc.c (cmpf.[sd]): Reverse the order of the reg1 and reg2
|
|
|
|
|
|
operands.
|
|
|
|
|
|
|
2011-05-11 22:35:20 +00:00
|
|
|
|
2011-05-10 Quentin Neill <quentin.neill@amd.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-gen.c (cpu_flag_init): Add new CPU_BDVER2_FLAGS.
|
|
|
|
|
|
* i386-init.h: Regenerated.
|
|
|
|
|
|
|
2011-04-27 10:02:27 +00:00
|
|
|
|
2011-04-27 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* po/da.po: Updated Danish translation.
|
|
|
|
|
|
|
2011-04-25 23:11:21 +00:00
|
|
|
|
2011-04-26 Anton Blanchard <anton@samba.org>
|
|
|
|
|
|
|
|
|
|
|
|
* ppc-opc.c: (powerpc_opcodes): Enable icswx for POWER7.
|
|
|
|
|
|
|
2011-04-21 05:48:06 +00:00
|
|
|
|
2011-04-21 DJ Delorie <dj@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* rx-decode.opc (rx_decode_opcode): Set the syntax for multi-byte NOPs.
|
|
|
|
|
|
* rx-decode.c: Regenerate.
|
|
|
|
|
|
|
2011-04-20 14:27:34 +00:00
|
|
|
|
2011-04-20 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-init.h: Regenerated.
|
|
|
|
|
|
|
2011-04-19 23:45:17 +00:00
|
|
|
|
2011-04-19 Quentin Neill <quentin.neill@amd.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-gen.c (cpu_flag_init): Remove 3dnow and 3dnowa bits
|
|
|
|
|
|
from bdver1 flags.
|
|
|
|
|
|
|
2011-04-13 13:20:24 +00:00
|
|
|
|
2011-04-13 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* v850-dis.c (disassemble): Always print a closing square brace if
|
|
|
|
|
|
an opening square brace was printed.
|
|
|
|
|
|
|
2011-04-12 16:01:48 +00:00
|
|
|
|
2011-04-12 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR binutils/12534
|
|
|
|
|
|
* arm-dis.c (thumb32_opcodes): Add %L suffix to LDRD and STRD insn
|
|
|
|
|
|
patterns.
|
|
|
|
|
|
(print_insn_thumb32): Handle %L.
|
|
|
|
|
|
|
2011-04-11 18:49:06 +00:00
|
|
|
|
2011-04-11 Julian Brown <julian@codesourcery.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arm-dis.c (psr_name): Fix typo for BASEPRI_MAX.
|
|
|
|
|
|
(print_insn_thumb32): Add APSR bitmask support.
|
|
|
|
|
|
|
2011-04-08 11:42:19 +00:00
|
|
|
|
2011-04-07 Paul Carroll<pcarroll@codesourcery.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arm-dis.c (print_insn): init vars moved into private_data structure.
|
|
|
|
|
|
|
2011-03-24 05:27:39 +00:00
|
|
|
|
2011-03-24 Mike Frysinger <vapier@gentoo.org>
|
|
|
|
|
|
|
|
|
|
|
|
* bfin-dis.c (decode_dsp32mac_0): Move MM zeroing down to MAC0 logic.
|
|
|
|
|
|
|
2011-03-22 18:10:48 +00:00
|
|
|
|
2011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* avr-dis.c (avr_operand): Add opcode_str parameter. Check for
|
|
|
|
|
|
post-increment to support LPM Z+ instruction. Add support for 'E'
|
|
|
|
|
|
constraint for DES instruction.
|
|
|
|
|
|
(print_insn_avr): Adjust calls to avr_operand. Rename variable.
|
|
|
|
|
|
|
include/elf/
* arm.h (R_ARM_IRELATIVE): New relocation.
bfd/
* reloc.c (BFD_RELOC_ARM_IRELATIVE): New relocation.
* bfd-in2.h: Regenerate.
* elf32-arm.c (elf32_arm_howto_table_2): Rename existing definition
to elf32_arm_howto_table_3 and replace with a single R_ARM_IRELATIVE
entry.
(elf32_arm_howto_from_type): Update accordingly.
(elf32_arm_reloc_map): Map BFD_RELOC_ARM_IRELATIVE to R_ARM_IRELATIVE.
(elf32_arm_reloc_name_lookup): Handle elf32_arm_howto_table_3.
(arm_plt_info): New structure, split out from elf32_arm_link_hash_entry
with an extra noncall_refcount field.
(arm_local_iplt_info): New structure.
(elf_arm_obj_tdata): Add local_iplt.
(elf32_arm_local_iplt): New accessor macro.
(elf32_arm_link_hash_entry): Replace plt_thumb_refcount,
plt_maybe_thumb_refcount and plt_got_offset with an arm_plt_info.
Change tls_type to a bitfield and add is_iplt.
(elf32_arm_link_hash_newfunc): Update accordingly.
(elf32_arm_allocate_local_sym_info): New function.
(elf32_arm_create_local_iplt): Likewise.
(elf32_arm_get_plt_info): Likewise.
(elf32_arm_plt_needs_thumb_stub_p): Likewise.
(elf32_arm_get_local_dynreloc_list): Likewise.
(create_ifunc_sections): Likewise.
(elf32_arm_copy_indirect_symbol): Update after the changes to
elf32_arm_link_hash_entry. Assert the is_iplt has not yet been set.
(arm_type_of_stub): Add an st_type argument. Use elf32_arm_get_plt_info
to get PLT information. Assert that all STT_GNU_IFUNC references
are turned into PLT references.
(arm_build_one_stub): Pass the symbol type to
elf32_arm_final_link_relocate.
(elf32_arm_size_stubs): Pass the symbol type to arm_type_of_stub.
(elf32_arm_allocate_irelocs): New function.
(elf32_arm_add_dynreloc): In static objects, use .rel.iplt for
all R_ARM_IRELATIVE.
(elf32_arm_allocate_plt_entry): New function.
(elf32_arm_populate_plt_entry): Likewise.
(elf32_arm_final_link_relocate): Add an st_type parameter.
Set srelgot to null for static objects. Use separate variables
to record which st_value and st_type should be used when generating
a dynamic relocation. Use elf32_arm_get_plt_info to find the
symbol's PLT information, setting has_iplt_entry, splt,
plt_offset and gotplt_offset accordingly. Check whether
STT_GNU_IFUNC symbols should resolve to an .iplt entry, and change
the relocation target accordingly. Broaden assert to include
.iplts. Don't set sreloc for static relocations. Assert that
we only generate dynamic R_ARM_RELATIVE relocations for R_ARM_ABS32
and R_ARM_ABS32_NOI. Generate R_ARM_IRELATIVE relocations instead
of R_ARM_RELATIVE relocations if the target is an STT_GNU_IFUNC
symbol. Pass the symbol type to arm_type_of_stub. Conditionally
resolve GOT references to the .igot.plt entry.
(elf32_arm_relocate_section): Update the call to
elf32_arm_final_link_relocate.
(elf32_arm_gc_sweep_hook): Use elf32_arm_get_plt_info to get PLT
information. Treat R_ARM_REL32 and R_ARM_REL32_NOI as call
relocations in shared libraries and relocatable executables.
Count non-call PLT references. Use elf32_arm_get_local_dynreloc_list
to get the list of dynamic relocations for a local symbol.
(elf32_arm_check_relocs): Always create ifunc sections. Set isym
at the same time as setting h. Use elf32_arm_allocate_local_sym_info
to allocate local symbol information. Treat R_ARM_REL32 and
R_ARM_REL32_NOI as call relocations in shared libraries and
relocatable executables. Record PLT information for local
STT_GNU_IFUNC functions as well as global functions. Count
non-call PLT references. Use elf32_arm_get_local_dynreloc_list
to get the list of dynamic relocations for a local symbol.
(elf32_arm_adjust_dynamic_symbol): Handle STT_GNU_IFUNC symbols.
Don't remove STT_GNU_IFUNC PLTs unless all references have been
removed. Update after the changes to elf32_arm_link_hash_entry.
(allocate_dynrelocs_for_symbol): Decide whether STT_GNU_IFUNC PLT
entries should live in .plt or .iplt. Check whether the .igot.plt
and .got entries can be combined. Use elf32_arm_allocate_plt_entry
to allocate .plt and .(i)got.plt entries. Detect which .got
entries will need R_ARM_IRELATIVE relocations and use
elf32_arm_allocate_irelocs to allocate them. Likewise other
non-.got dynamic relocations.
(elf32_arm_size_dynamic_sections): Allocate .iplt, .igot.plt
and dynamic relocations for local STT_GNU_IFUNC symbols.
Check whether the .igot.plt and .got entries can be combined.
Detect which .got entries will need R_ARM_IRELATIVE relocations
and use elf32_arm_allocate_irelocs to allocate them. Use stashed
section pointers intead of strcmp checks. Handle iplt and igotplt.
(elf32_arm_finish_dynamic_symbol): Use elf32_arm_populate_plt_entry
to fill in .plt, .got.plt and .rel(a).plt entries. Point
STT_GNU_IFUNC symbols at an .iplt entry if non-call relocations
resolve to it.
(elf32_arm_output_plt_map_1): New function, split out from
elf32_arm_output_plt_map. Handle .iplt entries. Use
elf32_arm_plt_needs_thumb_stub_p.
(elf32_arm_output_plt_map): Call it.
(elf32_arm_output_arch_local_syms): Add mapping symbols for
local .iplt entries.
(elf32_arm_swap_symbol_in): Handle Thumb STT_GNU_IFUNC symbols.
(elf32_arm_swap_symbol_out): Likewise.
(elf32_arm_add_symbol_hook): New function.
(elf_backend_add_symbol_hook): Define for all targets.
opcodes/
* arm-dis.c (get_sym_code_type): Treat STT_GNU_IFUNCs as code.
gas/
* config/tc-arm.c (md_pcrel_from_section): Use S_FORCE_RELOC to
determine whether a relocation is needed.
(md_apply_fix, arm_apply_sym_value): Likewise.
ld/testsuite/
* ld-arm/ifunc-1.s, ld-arm/ifunc-1.dd, ld-arm/ifunc-1.gd,
ld-arm/ifunc-1.rd, ld-arm/ifunc-2.s, ld-arm/ifunc-2.dd,
ld-arm/ifunc-2.gd, ld-arm/ifunc-2.rd, ld-arm/ifunc-3.s,
ld-arm/ifunc-3.dd, ld-arm/ifunc-3.gd, ld-arm/ifunc-3.rd,
ld-arm/ifunc-4.s, ld-arm/ifunc-4.dd, ld-arm/ifunc-4.gd,
ld-arm/ifunc-4.rd, ld-arm/ifunc-5.s, ld-arm/ifunc-5.dd,
ld-arm/ifunc-5.gd, ld-arm/ifunc-5.rd, ld-arm/ifunc-6.s,
ld-arm/ifunc-6.dd, ld-arm/ifunc-6.gd, ld-arm/ifunc-6.rd,
ld-arm/ifunc-7.s, ld-arm/ifunc-7.dd, ld-arm/ifunc-7.gd,
ld-arm/ifunc-7.rd, ld-arm/ifunc-8.s, ld-arm/ifunc-8.dd,
ld-arm/ifunc-8.gd, ld-arm/ifunc-8.rd, ld-arm/ifunc-9.s,
ld-arm/ifunc-9.dd, ld-arm/ifunc-9.gd, ld-arm/ifunc-9.rd,
ld-arm/ifunc-10.s, ld-arm/ifunc-10.dd, ld-arm/ifunc-10.gd,
ld-arm/ifunc-10.rd, ld-arm/ifunc-11.s, ld-arm/ifunc-11.dd,
ld-arm/ifunc-11.gd, ld-arm/ifunc-11.rd, ld-arm/ifunc-12.s,
ld-arm/ifunc-12.dd, ld-arm/ifunc-12.gd, ld-arm/ifunc-12.rd,
ld-arm/ifunc-13.s, ld-arm/ifunc-13.dd, ld-arm/ifunc-13.gd,
ld-arm/ifunc-13.rd, ld-arm/ifunc-14.s, ld-arm/ifunc-14.dd,
ld-arm/ifunc-14.gd, ld-arm/ifunc-14.rd, ld-arm/ifunc-15.s,
ld-arm/ifunc-15.dd, ld-arm/ifunc-15.gd, ld-arm/ifunc-15.rd,
ld-arm/ifunc-16.s, ld-arm/ifunc-16.dd, ld-arm/ifunc-16.gd,
ld-arm/ifunc-16.rd, ld-arm/ifunc-dynamic.ld,
ld-arm/ifunc-static.ld: New tests.
* ld-arm/farcall-group.d, ld-arm/farcall-group-size2.d,
ld-arm/farcall-mixed-lib-v4t.d, ld-arm/farcall-mixed-lib.d: Update
for new stub hashes.
* ld-arm/arm-elf.exp: Run them.
2011-03-14 16:04:16 +00:00
|
|
|
|
2011-03-14 Richard Sandiford <richard.sandiford@linaro.org>
|
|
|
|
|
|
|
|
|
|
|
|
* arm-dis.c (get_sym_code_type): Treat STT_GNU_IFUNCs as code.
|
|
|
|
|
|
|
2011-03-14 15:55:04 +00:00
|
|
|
|
2011-03-14 Richard Sandiford <richard.sandiford@linaro.org>
|
|
|
|
|
|
|
|
|
|
|
|
* arm-dis.c (get_sym_code_type): Don't check for STT_ARM_TFUNC.
|
|
|
|
|
|
Use branch types instead.
|
|
|
|
|
|
(print_insn): Likewise.
|
|
|
|
|
|
|
2011-02-28 16:34:39 +00:00
|
|
|
|
2011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
|
|
|
|
|
|
|
|
|
|
|
|
* mips-opc.c (mips_builtin_opcodes): Correct register use
|
|
|
|
|
|
annotation of "alnv.ps".
|
|
|
|
|
|
|
2011-02-28 16:06:51 +00:00
|
|
|
|
2011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
|
|
|
|
|
|
|
|
|
|
|
|
* mips-opc.c (mips_builtin_opcodes): Add "pref" macro.
|
|
|
|
|
|
|
2011-02-22 20:52:31 +00:00
|
|
|
|
2011-02-22 Mike Frysinger <vapier@gentoo.org>
|
|
|
|
|
|
|
|
|
|
|
|
* bfin-dis.c (OUTS): Remove p NULL check and txt NUL check.
|
|
|
|
|
|
|
2011-02-22 20:51:42 +00:00
|
|
|
|
2011-02-22 Mike Frysinger <vapier@gentoo.org>
|
|
|
|
|
|
|
|
|
|
|
|
* bfin-dis.c (print_insn_bfin): Change outf->fprintf_func to OUTS.
|
|
|
|
|
|
|
2011-02-20 01:26:14 +00:00
|
|
|
|
2011-02-19 Mike Frysinger <vapier@gentoo.org>
|
|
|
|
|
|
|
|
|
|
|
|
* bfin-dis.c (saved_state): Mark static. Change a[01]x to ax[] and
|
|
|
|
|
|
a[01]w to aw[]. Delete ac0, ac0_copy, ac1, an, aq, av0, av0s, av1,
|
|
|
|
|
|
av1s, az, cc, v, v_copy, vs, rnd_mod, v_internal, pc, ticks, insts,
|
|
|
|
|
|
exception, end_of_registers, msize, memory, bfd_mach.
|
|
|
|
|
|
(CCREG, PCREG, A0XREG, A0WREG, A1XREG, A1WREG, LC0REG, LT0REG,
|
|
|
|
|
|
LB0REG, LC1REG, LT1REG, LB1REG): Delete
|
|
|
|
|
|
(AXREG, AWREG, LCREG, LTREG, LBREG): Define.
|
|
|
|
|
|
(get_allreg): Change to new defines. Fallback to abort().
|
|
|
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|
|
2011-02-14 17:12:05 +00:00
|
|
|
|
2011-02-14 Mike Frysinger <vapier@gentoo.org>
|
|
|
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|
|
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|
|
* bfin-dis.c: Add whitespace/parenthesis where needed.
|
|
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|
|
2011-02-14 05:21:04 +00:00
|
|
|
|
2011-02-14 Mike Frysinger <vapier@gentoo.org>
|
|
|
|
|
|
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|
|
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|
|
* bfin-dis.c (decode_LoopSetup_0): Return when reg is greater
|
|
|
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|
than 7.
|
|
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|
2011-02-13 21:00:14 +00:00
|
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|
2011-02-13 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
|
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|
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* configure: Regenerate.
|
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|
2011-02-13 18:55:22 +00:00
|
|
|
|
2011-02-13 Mike Frysinger <vapier@gentoo.org>
|
|
|
|
|
|
|
|
|
|
|
|
* bfin-dis.c (decode_dsp32alu_0): Fix typo with A1 reg.
|
|
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|
2011-02-13 18:54:49 +00:00
|
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|
|
2011-02-13 Mike Frysinger <vapier@gentoo.org>
|
|
|
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|
|
|
|
|
|
|
|
* bfin-dis.c (decode_dsp32mult_0): Add 1 to dst for mac1. Output
|
|
|
|
|
|
dregs only when P is set, and dregs_lo otherwise.
|
|
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|
2011-02-13 18:53:16 +00:00
|
|
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|
2011-02-13 Mike Frysinger <vapier@gentoo.org>
|
|
|
|
|
|
|
|
|
|
|
|
* bfin-dis.c (decode_dsp32alu_0): Delete BYTEOP2M code.
|
|
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|
2011-02-12 19:38:11 +00:00
|
|
|
|
2011-02-12 Mike Frysinger <vapier@gentoo.org>
|
|
|
|
|
|
|
|
|
|
|
|
* bfin-dis.c (decode_pseudoDEBUG_0): Add space after PRNT.
|
|
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|
|
|
|
2011-02-12 19:37:32 +00:00
|
|
|
|
2011-02-12 Mike Frysinger <vapier@gentoo.org>
|
|
|
|
|
|
|
|
|
|
|
|
* bfin-dis.c (machine_registers): Delete REG_GP.
|
|
|
|
|
|
(reg_names): Delete "GP".
|
|
|
|
|
|
(decode_allregs): Change REG_GP to REG_LASTREG.
|
|
|
|
|
|
|
2011-02-12 19:36:31 +00:00
|
|
|
|
2011-02-12 Mike Frysinger <vapier@gentoo.org>
|
|
|
|
|
|
|
2011-02-28 16:03:38 +00:00
|
|
|
|
* bfin-dis.c (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2,
|
|
|
|
|
|
M_IH, M_IU): Delete.
|
2011-02-12 19:36:31 +00:00
|
|
|
|
|
2011-02-11 19:03:27 +00:00
|
|
|
|
2011-02-11 Mike Frysinger <vapier@gentoo.org>
|
|
|
|
|
|
|
|
|
|
|
|
* bfin-dis.c (reg_names): Add const.
|
|
|
|
|
|
(decode_dregs_lo, decode_dregs_hi, decode_dregs, decode_dregs_byte,
|
|
|
|
|
|
decode_pregs, decode_iregs, decode_mregs, decode_dpregs, decode_gregs,
|
|
|
|
|
|
decode_regs, decode_regs_lo, decode_regs_hi, decode_statbits,
|
|
|
|
|
|
decode_counters, decode_allregs): Likewise.
|
|
|
|
|
|
|
2011-02-09 18:43:41 +00:00
|
|
|
|
2011-02-09 Michael Snyder <msnyder@vmware.com>
|
|
|
|
|
|
|
2011-06-17 15:06:46 +00:00
|
|
|
|
* i386-dis.c (OP_J): Parenthesize expression to prevent
|
2011-02-09 18:43:41 +00:00
|
|
|
|
truncated addresses.
|
|
|
|
|
|
(print_insn): Fix indentation off-by-one.
|
|
|
|
|
|
|
2011-02-01 13:14:40 +00:00
|
|
|
|
2011-02-01 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* po/da.po: Updated Danish translation.
|
|
|
|
|
|
|
2011-01-21 00:53:11 +00:00
|
|
|
|
2011-01-21 Dave Murphy <davem@devkitpro.org>
|
|
|
|
|
|
|
|
|
|
|
|
* ppc-opc.c (NON32, NO371): Remove PPC_OPCODE_PPCPS.
|
|
|
|
|
|
|
2011-01-18 17:08:13 +00:00
|
|
|
|
2011-01-18 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-dis.c (sIbT): New.
|
|
|
|
|
|
(b_T_mode): Likewise.
|
|
|
|
|
|
(dis386): Replace sIb with sIbT on "pushT".
|
|
|
|
|
|
(x86_64_table): Replace sIb with Ib on "aam" and "aad".
|
|
|
|
|
|
(OP_sI): Handle b_T_mode. Properly sign-extend byte.
|
|
|
|
|
|
|
2011-01-18 14:14:46 +00:00
|
|
|
|
2011-01-18 Jan Kratochvil <jan.kratochvil@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-init.h: Regenerated.
|
|
|
|
|
|
* i386-tbl.h: Regenerated
|
|
|
|
|
|
|
Add support for TBM instructions.
gas/
2011-01-17 Quentin Neill <quentin.neill@amd.com>
* config/tc-i386.c (cpu_arch): Add CPU_TBM_FLAGS.
* doc/c-i386.texi (i386-TBM): New section.
opcodes/
2011-01-17 Quentin Neill <quentin.neill@amd.com>
* i386-dis.c (REG_XOP_TBM_01): New.
(REG_XOP_TBM_02): New.
(reg_table): Add REG_XOP_TBM_01 and REG_XOP_TBM_02 tables.
(xop_table): Redirect to REG_XOP_TBM_01 and REG_XOP_TBM_02
entries, and add bextr instruction.
* i386-gen.c (cpu_flag_init): Add CPU_TBM_FLAGS, CpuTBM.
(cpu_flags): Add CpuTBM.
* i386-opc.h (CpuTBM) New.
(i386_cpu_flags): Add bit cputbm.
* i386-opc.tbl: Add bextr, blcfill, blci, blcic, blcmsk,
blcs, blsfill, blsic, t1mskc, and tzmsk.
* i386-init.h: Regenerated.
* i386-tbl.h: Regenerated
gas/testsuite
2011-01-17 Quentin Neill <quentin.neill@amd.com>
* gas/i386/tbm.s: New.
* gas/i386/tbm.d: New.
* gas/i386/tbm-intel.d: New.
* gas/i386/x86-64-tbm.s: New.
* gas/i386/x86-64-tbm.d: New.
* gas/i386/x86-64-tbm-intel.d: New.
* gas/i386/arch-10.d: Add tbm flag and TBM instruction pattern.
* gas/i386/arch-10.s: Add a TBM instruction.
* gas/i386/arch-10-1.l: Add TBM instruction pattern.
* gas/i386/arch-10-2.l: Likewise.
* gas/i386/arch-10-3.l: Likewise.
* gas/i386/arch-10-4.l: Likewise.
* gas/i386/x86-64-arch-2.s: Likewise.
* gas/i386/x86-64-arch-2.d: Likewise.
2011-01-17 18:40:36 +00:00
|
|
|
|
2011-01-17 Quentin Neill <quentin.neill@amd.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-dis.c (REG_XOP_TBM_01): New.
|
|
|
|
|
|
(REG_XOP_TBM_02): New.
|
|
|
|
|
|
(reg_table): Add REG_XOP_TBM_01 and REG_XOP_TBM_02 tables.
|
|
|
|
|
|
(xop_table): Redirect to REG_XOP_TBM_01 and REG_XOP_TBM_02
|
|
|
|
|
|
entries, and add bextr instruction.
|
|
|
|
|
|
|
|
|
|
|
|
* i386-gen.c (cpu_flag_init): Add CPU_TBM_FLAGS, CpuTBM.
|
|
|
|
|
|
(cpu_flags): Add CpuTBM.
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.h (CpuTBM) New.
|
|
|
|
|
|
(i386_cpu_flags): Add bit cputbm.
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl: Add bextr, blcfill, blci, blcic, blcmsk,
|
|
|
|
|
|
blcs, blsfill, blsic, t1mskc, and tzmsk.
|
|
|
|
|
|
|
2011-01-12 07:06:29 +00:00
|
|
|
|
2011-01-12 DJ Delorie <dj@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* rx-dis.c (print_insn_rx): Support RX_Operand_TwoReg.
|
|
|
|
|
|
|
2011-01-11 07:22:09 +00:00
|
|
|
|
2011-01-11 Mingjie Xing <mingjie.xing@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* mips-dis.c (print_insn_args): Adjust the value to print the real
|
|
|
|
|
|
offset for "+c" argument.
|
|
|
|
|
|
|
2011-01-10 13:51:10 +00:00
|
|
|
|
2011-01-10 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* po/da.po: Updated Danish translation.
|
|
|
|
|
|
|
2011-01-06 14:30:43 +00:00
|
|
|
|
2011-01-05 Nathan Sidwell <nathan@codesourcery.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arm-dis.c (thumb32_opcodes): BLX must have bit zero clear.
|
|
|
|
|
|
|
2011-01-05 00:16:57 +00:00
|
|
|
|
2011-01-04 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-dis.c (REG_VEX_38F3): New.
|
|
|
|
|
|
(PREFIX_0FBC): Likewise.
|
|
|
|
|
|
(PREFIX_VEX_38F2): Likewise.
|
|
|
|
|
|
(PREFIX_VEX_38F3_REG_1): Likewise.
|
|
|
|
|
|
(PREFIX_VEX_38F3_REG_2): Likewise.
|
|
|
|
|
|
(PREFIX_VEX_38F3_REG_3): Likewise.
|
|
|
|
|
|
(PREFIX_VEX_38F7): Likewise.
|
|
|
|
|
|
(VEX_LEN_38F2_P_0): Likewise.
|
|
|
|
|
|
(VEX_LEN_38F3_R_1_P_0): Likewise.
|
|
|
|
|
|
(VEX_LEN_38F3_R_2_P_0): Likewise.
|
|
|
|
|
|
(VEX_LEN_38F3_R_3_P_0): Likewise.
|
|
|
|
|
|
(VEX_LEN_38F7_P_0): Likewise.
|
|
|
|
|
|
(dis386_twobyte): Use PREFIX_0FBC.
|
|
|
|
|
|
(reg_table): Add REG_VEX_38F3.
|
|
|
|
|
|
(prefix_table): Add PREFIX_0FBC, PREFIX_VEX_38F2,
|
|
|
|
|
|
PREFIX_VEX_38F3_REG_1, PREFIX_VEX_38F3_REG_2,
|
|
|
|
|
|
PREFIX_VEX_38F3_REG_3 and PREFIX_VEX_38F7.
|
|
|
|
|
|
(vex_table): Use PREFIX_VEX_38F2, REG_VEX_38F3 and
|
|
|
|
|
|
PREFIX_VEX_38F7.
|
|
|
|
|
|
(vex_len_table): Add VEX_LEN_38F2_P_0, VEX_LEN_38F3_R_1_P_0,
|
|
|
|
|
|
VEX_LEN_38F3_R_2_P_0, VEX_LEN_38F3_R_3_P_0 and
|
|
|
|
|
|
VEX_LEN_38F7_P_0.
|
|
|
|
|
|
|
|
|
|
|
|
* i386-gen.c (cpu_flag_init): Add CPU_BMI_FLAGS.
|
|
|
|
|
|
(cpu_flags): Add CpuBMI.
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.h (CpuBMI): New.
|
|
|
|
|
|
(i386_cpu_flags): Add cpubmi.
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl: Add andn, bextr, blsi, blsmsk, blsr and tzcnt.
|
|
|
|
|
|
* i386-init.h: Regenerated.
|
|
|
|
|
|
* i386-tbl.h: Likewise.
|
|
|
|
|
|
|
2011-01-04 20:53:32 +00:00
|
|
|
|
2011-01-04 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-dis.c (VexGdq): New.
|
|
|
|
|
|
(OP_VEX): Handle dq_mode.
|
|
|
|
|
|
|
2011-01-01 20:55:48 +00:00
|
|
|
|
2011-01-01 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-gen.c (process_copyright): Update copyright to 2011.
|
|
|
|
|
|
|
2011-01-01 16:43:53 +00:00
|
|
|
|
For older changes see ChangeLog-2010
|
1999-05-03 07:29:11 +00:00
|
|
|
|
|
|
|
|
|
|
Local Variables:
|
2001-01-11 19:01:42 +00:00
|
|
|
|
mode: change-log
|
|
|
|
|
|
left-margin: 8
|
|
|
|
|
|
fill-column: 74
|
1999-05-03 07:29:11 +00:00
|
|
|
|
version-control: never
|
|
|
|
|
|
End:
|
