darkkirb/old-cross-binutils
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity
old-cross-binutils/sim/testsuite/d10v-elf/ChangeLog

67 lines
1.6 KiB
Text
Raw Normal View History

Test switching between SPI/SPU.
1998-02-13 05:19:02 +00:00
Fri Feb 13 16:21:13 1998 Andrew Cagney <cagney@b1.cygnus.com>
* t-sp.s: New test.
* Makefile.in (TESTS): Update.
Update tests to match recently modified ABI
1998-02-11 07:12:48 +00:00
Wed Feb 11 17:58:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
* t-macros.i: Update trap calls, func in r4, args in
r0...
(start): Force r0 to zero.
* t-sub2w.s: Ditto.
Fix typo, REP_S was refering to REP_E register. Add test.
1997-12-08 23:44:11 +00:00
Tue Dec 9 10:41:44 1997 Andrew Cagney <cagney@b1.cygnus.com>
Update tests to match recently modified ABI
1998-02-11 07:12:48 +00:00
* t-rte.s (success): New file.
* Makefile.in: Update.
Fix typo, REP_S was refering to REP_E register. Add test.
1997-12-08 23:44:11 +00:00
* t-rep.s: Check rep repeats correct number of times.
For "trap", IBT and RIE exceptions, mask all PSW.SM. NB: Stepping through an exception may not work correctly. For GDB reads/writes to the control registers, ensure the cpu state is updated correctly.
1997-12-08 03:22:58 +00:00
Fri Dec 5 10:11:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
* t-mvtc.s: Check for stuck-zero in MOD_E, MOD_S.
* t-trap.s: New file.
* Makefile.in (TESTS): Update.
Add DM (bit 4) to PSW. See 7-1 for more info. Test.
1997-12-04 07:01:30 +00:00
Thu Dec 4 16:56:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
* t-macros.i: Add definitions for PSW bits.
* t-mvtc.s: New file.
* Makefile.in (TESTS): Update.
* d10v_sim.h (SEXT56): Define. * simops.c (OP_4201): For "rac", sign extend 56 bit value before it is shifted. * d10v_sim.h (MAX32, MIN32, MASK32, MASK40): Re-define using SIGNED64 macro.
1997-12-03 08:03:33 +00:00
Wed Dec 3 16:35:24 1997 Andrew Cagney <cagney@b1.cygnus.com>
* t-rac.s: New files.
* t-macros.i: Add macros for checking psw and 2w quantities.
* Makefile.in (TESTS): Update.
For sub2w, compute carry according to negated addition rules. Test.
1997-12-02 00:27:27 +00:00
Tue Dec 2 11:01:36 1997 Andrew Cagney <cagney@b1.cygnus.com>
* d10v_sim.h (SEXT56): Define. * simops.c (OP_4201): For "rac", sign extend 56 bit value before it is shifted. * d10v_sim.h (MAX32, MIN32, MASK32, MASK40): Re-define using SIGNED64 macro.
1997-12-03 08:03:33 +00:00
* t-sub2w.s, t-mulxu.s, t-mac.s, t-mvtac.s, t-msbu.s, t-sub.s: New
files.
For "mulxu", store unsigned product in ACC. Test.
1997-12-02 06:37:09 +00:00
For sub2w, compute carry according to negated addition rules. Test.
1997-12-02 00:27:27 +00:00
* Makefile.in: Update.
Mon Nov 17 20:14:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
* t-subi.s (test_subi): New file.
* Makefile.in: Update.
Fri Nov 14 14:06:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
* t-rep.s: New file. Test case of branch to RPT_E address.
Test rachi instruction.
1997-11-10 08:27:15 +00:00
Mon Nov 10 19:21:26 1997 Andrew Cagney <cagney@b1.cygnus.com>
* t-macros.i (_start): New file.
* t-rachi.s: New file.
* Makefile.in (RUN_FOR_TARGET): Look for simulator in d10v
directory.
Reference in a new issue Copy permalink