darkkirb/mtgos-mtgos-3ds9
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity

I heard it helps to adjust the code to 64 bits

Browse source
This commit is contained in:
Morten Delenk 2017-04-30 19:15:41 +00:00
parent efa5e16ea4
commit d14a3e5919
4 changed files with 15 additions and 3 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

1
kernel/arch/arm/3ds9/start.cpp
View file

@ -1,4 +1,5 @@
#include "../../../hw/3ds9/picafb/picafb.hpp"
#include "../../../hw/3ds9/vectorinit/vectorinit.hpp"
#include <base.hpp>
#include <config.h>

10
kernel/arch/arm/interrupt.cpp Normal file
View file

@ -0,0 +1,10 @@
#include <base.hpp>
#include <regs.hpp>
void print_regdump(cpu_state *state) {
(*out << "r0: ").puti(state->r0);
(*out << " r1: ").puti(state->r1);
(*out << " r2: ").puti(state->r2);
(*out << " r3: ").puti(state->r3);
(*out << " r4: ").puti(state->r4);
(*out << " r5: ").puti(state->r5);
}

2
kernel/arch/x86_64/pc/start.cpp
View file

@ -26,5 +26,5 @@ void drivers_init() {
initIDT();
PIC::initPIC(0x20, 0x28);
asm volatile("sti");
asm volatile("int $0");
asm volatile("int $32");
}

5
kernel/arch/x86_64/sourcegen.py
View file

@ -24,7 +24,8 @@ if config["ENABLE_FPU"] and not config["ENABLE_SSE"]:
if config["ENABLE_SSE"]:
data_section+=".align 16\nfxsave_reg:\n .space 512"
all_regs_push.append("fxsave fxsave_reg")
all_regs_pop.append("fxrstor fxsave_reg")
all_regs_pop.append("fxrstor (%rax)")
all_regs_pop.append("pop %rax")
all_regs_push.append("pushq $fxsave_reg")
print("Writing interrupt handler")
@ -33,7 +34,7 @@ for ins in all_regs_push:
int_handler.write(" mov %rsp, %rdi\n call handleINT\n mov %rax, %rsp\n")
for ins in reversed(all_regs_pop):
int_handler.write(" "+ins+"\n")
int_handler.write(" add $8, %esp\n iret\n")
int_handler.write(" add $16, %rsp\n iretq\n")
print("Writing panic handler")
int_handler.write(".global panic\n.extern panic2\npanic:\n")