diff --git a/kernel/arch/arm/3ds9/start.cpp b/kernel/arch/arm/3ds9/start.cpp
index 11e18d0..cbdf47f 100644
--- a/kernel/arch/arm/3ds9/start.cpp
+++ b/kernel/arch/arm/3ds9/start.cpp
@@ -1,4 +1,5 @@
 #include "../../../hw/3ds9/picafb/picafb.hpp"
+#include "../../../hw/3ds9/vectorinit/vectorinit.hpp"
 #include <base.hpp>
 #include <config.h>
 
diff --git a/kernel/arch/arm/interrupt.cpp b/kernel/arch/arm/interrupt.cpp
new file mode 100644
index 0000000..d0acc1d
--- /dev/null
+++ b/kernel/arch/arm/interrupt.cpp
@@ -0,0 +1,10 @@
+#include <base.hpp>
+#include <regs.hpp>
+void print_regdump(cpu_state *state) {
+    (*out << "r0: ").puti(state->r0);
+    (*out << " r1: ").puti(state->r1);
+    (*out << " r2: ").puti(state->r2);
+    (*out << " r3: ").puti(state->r3);
+    (*out << " r4: ").puti(state->r4);
+    (*out << " r5: ").puti(state->r5);
+}
diff --git a/kernel/arch/x86_64/pc/start.cpp b/kernel/arch/x86_64/pc/start.cpp
index 58f3798..40571f4 100644
--- a/kernel/arch/x86_64/pc/start.cpp
+++ b/kernel/arch/x86_64/pc/start.cpp
@@ -26,5 +26,5 @@ void drivers_init() {
     initIDT();
     PIC::initPIC(0x20, 0x28);
     asm volatile("sti");
-    asm volatile("int $0");
+    asm volatile("int $32");
 }
diff --git a/kernel/arch/x86_64/sourcegen.py b/kernel/arch/x86_64/sourcegen.py
index 301fd60..e98a996 100644
--- a/kernel/arch/x86_64/sourcegen.py
+++ b/kernel/arch/x86_64/sourcegen.py
@@ -24,7 +24,8 @@ if config["ENABLE_FPU"] and not config["ENABLE_SSE"]:
 if config["ENABLE_SSE"]:
     data_section+=".align 16\nfxsave_reg:\n    .space 512"
     all_regs_push.append("fxsave fxsave_reg")
-    all_regs_pop.append("fxrstor fxsave_reg")
+    all_regs_pop.append("fxrstor (%rax)")
+    all_regs_pop.append("pop %rax")
     all_regs_push.append("pushq $fxsave_reg")
 
 print("Writing interrupt handler")
@@ -33,7 +34,7 @@ for ins in all_regs_push:
 int_handler.write("    mov %rsp, %rdi\n    call handleINT\n    mov %rax, %rsp\n")
 for ins in reversed(all_regs_pop):
     int_handler.write("    "+ins+"\n")
-int_handler.write("    add $8, %esp\n    iret\n")
+int_handler.write("    add $16, %rsp\n    iretq\n")
 
 print("Writing panic handler")
 int_handler.write(".global panic\n.extern panic2\npanic:\n")